1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ISA_INLINES_H
  7#define ISA_INLINES_H
  8
  9#include "macros.h"
 10
 11#include "arm.h"
 12
 13#define ARM_COND_EQ (ARMPSRIsZ(cpu->cpsr))
 14#define ARM_COND_NE (!ARMPSRIsZ(cpu->cpsr))
 15#define ARM_COND_CS (ARMPSRIsC(cpu->cpsr))
 16#define ARM_COND_CC (!ARMPSRIsC(cpu->cpsr))
 17#define ARM_COND_MI (ARMPSRIsN(cpu->cpsr))
 18#define ARM_COND_PL (!ARMPSRIsN(cpu->cpsr))
 19#define ARM_COND_VS (ARMPSRIsV(cpu->cpsr))
 20#define ARM_COND_VC (!ARMPSRIsV(cpu->cpsr))
 21#define ARM_COND_HI (ARMPSRIsC(cpu->cpsr) && !ARMPSRIsZ(cpu->cpsr))
 22#define ARM_COND_LS (!ARMPSRIsC(cpu->cpsr) || ARMPSRIsZ(cpu->cpsr))
 23#define ARM_COND_GE (!ARMPSRIsN(cpu->cpsr) == !ARMPSRIsV(cpu->cpsr))
 24#define ARM_COND_LT (!ARMPSRIsN(cpu->cpsr) != !ARMPSRIsV(cpu->cpsr))
 25#define ARM_COND_GT (!ARMPSRIsZ(cpu->cpsr) && !ARMPSRIsN(cpu->cpsr) == !ARMPSRIsV(cpu->cpsr))
 26#define ARM_COND_LE (ARMPSRIsZ(cpu->cpsr) || !ARMPSRIsN(cpu->cpsr) != !ARMPSRIsV(cpu->cpsr))
 27#define ARM_COND_AL 1
 28
 29#define ARM_SIGN(I) ((I) >> 31)
 30#define ARM_SXT_8(I) (((int8_t) (I) << 24) >> 24)
 31#define ARM_SXT_16(I) (((int16_t) (I) << 16) >> 16)
 32#define ARM_UXT_64(I) (uint64_t)(uint32_t) (I)
 33
 34#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
 35#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
 36#define ARM_BORROW_FROM_CARRY(M, N, D, C) (ARM_UXT_64(M) >= (ARM_UXT_64(N)) + (uint64_t) (C))
 37#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
 38#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
 39
 40#define ARM_WAIT_MUL(R)                                                   \
 41	{                                                                     \
 42		int32_t wait;                                                     \
 43		if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) {        \
 44			wait = 1;                                                     \
 45		} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
 46			wait = 2;                                                     \
 47		} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
 48			wait = 3;                                                     \
 49		} else {                                                          \
 50			wait = 4;                                                     \
 51		}                                                                 \
 52		currentCycles += cpu->memory.stall(cpu, wait);                    \
 53	}
 54
 55#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
 56#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
 57
 58#define ARM_WRITE_PC                                                                                 \
 59	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM);                                        \
 60	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);                                             \
 61	LOAD_32(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 62	cpu->gprs[ARM_PC] += WORD_SIZE_ARM;                                                              \
 63	LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 64	currentCycles += 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
 65
 66#define THUMB_WRITE_PC                                                                               \
 67	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB);                                      \
 68	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);                                             \
 69	LOAD_16(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 70	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;                                                            \
 71	LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 72	currentCycles += 2 + cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
 73
 74static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 75	return mode != MODE_SYSTEM && mode != MODE_USER;
 76}
 77
 78static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
 79	if (executionMode == cpu->executionMode) {
 80		return;
 81	}
 82
 83	cpu->executionMode = executionMode;
 84	switch (executionMode) {
 85	case MODE_ARM:
 86		cpu->cpsr = ARMPSRClearT(cpu->cpsr);
 87		break;
 88	case MODE_THUMB:
 89		cpu->cpsr = ARMPSRFillT(cpu->cpsr);
 90	}
 91	cpu->nextEvent = cpu->cycles;
 92}
 93
 94static inline void _ARMReadCPSR(struct ARMCore* cpu) {
 95	_ARMSetMode(cpu, ARMPSRGetT(cpu->cpsr));
 96	ARMSetPrivilegeMode(cpu, ARMPSRGetPriv(cpu->cpsr));
 97	cpu->irqh.readCPSR(cpu);
 98}
 99
100static inline uint32_t _ARMPCAddress(struct ARMCore* cpu) {
101	int instructionLength;
102	if (ARMPSRIsT(cpu->cpsr)) {
103		instructionLength = WORD_SIZE_ARM;
104	} else {
105		instructionLength = WORD_SIZE_THUMB;
106	}
107	return cpu->gprs[ARM_PC] - instructionLength * 2;
108}
109
110#endif