src/arm/isa-thumb.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-thumb.h>
7
8#include <mgba/internal/arm/isa-inlines.h>
9#include <mgba/internal/arm/emitter-thumb.h>
10
11// Instruction definitions
12// Beware pre-processor insanity
13
14#define THUMB_ADDITION_S(M, N, D) \
15 { \
16 ARMPSR cpsr = 0; \
17 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
18 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
19 cpsr = ARMPSROrUnsafeC(cpsr, ARM_CARRY_FROM(M, N, D)); \
20 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_ADDITION(M, N, D)); \
21 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
22 }
23
24#define THUMB_SUBTRACTION_S(M, N, D) \
25 { \
26 ARMPSR cpsr = 0; \
27 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
28 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
29 cpsr = ARMPSROrUnsafeC(cpsr, ARM_BORROW_FROM(M, N, D)); \
30 cpsr = ARMPSROrUnsafeV(cpsr, ARM_V_SUBTRACTION(M, N, D)); \
31 cpu->cpsr = (cpu->cpsr & (0x0FFFFFFF)) | cpsr; \
32 }
33
34#define THUMB_NEUTRAL_S(M, N, D) \
35{ \
36 ARMPSR cpsr = 0; \
37 cpsr = ARMPSROrUnsafeN(cpsr, ARM_SIGN(D)); \
38 cpsr = ARMPSROrUnsafeZ(cpsr, !(D)); \
39 cpu->cpsr = (cpu->cpsr & (0x3FFFFFFF)) | cpsr; \
40 }
41
42#define THUMB_ADDITION(D, M, N) \
43 int n = N; \
44 int m = M; \
45 D = M + N; \
46 THUMB_ADDITION_S(m, n, D)
47
48#define THUMB_SUBTRACTION(D, M, N) \
49 int n = N; \
50 int m = M; \
51 D = M - N; \
52 THUMB_SUBTRACTION_S(m, n, D)
53
54#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
55
56#define THUMB_LOAD_POST_BODY \
57 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
58
59#define THUMB_STORE_POST_BODY \
60 currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
61
62#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
63 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
64 int currentCycles = THUMB_PREFETCH_CYCLES; \
65 BODY; \
66 cpu->cycles += currentCycles; \
67 }
68
69#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
70 DEFINE_INSTRUCTION_THUMB(NAME, \
71 int immediate = (opcode >> 6) & 0x001F; \
72 int rd = opcode & 0x0007; \
73 int rm = (opcode >> 3) & 0x0007; \
74 BODY;)
75
76DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
77 if (!immediate) {
78 cpu->gprs[rd] = cpu->gprs[rm];
79 } else {
80 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (32 - immediate)) & 1);
81 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
82 }
83 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
84
85DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
86 if (!immediate) {
87 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rm]));
88 cpu->gprs[rd] = 0;
89 } else {
90 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (immediate - 1)) & 1);
91 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
92 }
93 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
94
95DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
96 if (!immediate) {
97 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rm]));
98 if (ARMPSRIsC(cpu->cpsr)) {
99 cpu->gprs[rd] = 0xFFFFFFFF;
100 } else {
101 cpu->gprs[rd] = 0;
102 }
103 } else {
104 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rm] >> (immediate - 1)) & 1);
105 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
106 }
107 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
108
109DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, ¤tCycles); THUMB_LOAD_POST_BODY;)
110DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, ¤tCycles); THUMB_LOAD_POST_BODY;)
112DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
113DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
114DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
115
116#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
117 DEFINE_INSTRUCTION_THUMB(NAME, \
118 int rm = (opcode >> 6) & 0x0007; \
119 int rd = opcode & 0x0007; \
120 int rn = (opcode >> 3) & 0x0007; \
121 BODY;)
122
123DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
124DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
125
126#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
127 DEFINE_INSTRUCTION_THUMB(NAME, \
128 int immediate = (opcode >> 6) & 0x0007; \
129 int rd = opcode & 0x0007; \
130 int rn = (opcode >> 3) & 0x0007; \
131 BODY;)
132
133DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
134DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
135
136#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
137 DEFINE_INSTRUCTION_THUMB(NAME, \
138 int rd = (opcode >> 8) & 0x0007; \
139 int immediate = opcode & 0x00FF; \
140 BODY;)
141
142DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
143DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
144DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
145DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
146
147#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
148 DEFINE_INSTRUCTION_THUMB(NAME, \
149 int rd = opcode & 0x0007; \
150 int rn = (opcode >> 3) & 0x0007; \
151 BODY;)
152
153DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
154DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
155DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
156 int rs = cpu->gprs[rn] & 0xFF;
157 if (rs) {
158 if (rs < 32) {
159 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (32 - rs)) & 1);
160 cpu->gprs[rd] <<= rs;
161 } else {
162 if (rs > 32) {
163 cpu->cpsr = ARMPSRClearC(cpu->cpsr);
164 } else {
165 cpu->cpsr = ARMPSRSetC(cpu->cpsr, cpu->gprs[rd] & 0x00000001);
166 }
167 cpu->gprs[rd] = 0;
168 }
169 }
170 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
171
172DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
173 int rs = cpu->gprs[rn] & 0xFF;
174 if (rs) {
175 if (rs < 32) {
176 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (rs - 1)) & 1);
177 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
178 } else {
179 if (rs > 32) {
180 cpu->cpsr = ARMPSRClearC(cpu->cpsr);
181 } else {
182 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
183 }
184 cpu->gprs[rd] = 0;
185 }
186 }
187 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
188
189DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
190 int rs = cpu->gprs[rn] & 0xFF;
191 if (rs) {
192 if (rs < 32) {
193 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (rs - 1)) & 1);
194 cpu->gprs[rd] >>= rs;
195 } else {
196 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
197 if (ARMPSRIsC(cpu->cpsr)) {
198 cpu->gprs[rd] = 0xFFFFFFFF;
199 } else {
200 cpu->gprs[rd] = 0;
201 }
202 }
203 }
204 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
205
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
207 int n = cpu->gprs[rn];
208 int d = cpu->gprs[rd];
209 cpu->gprs[rd] = d + n + ARMPSRGetC(cpu->cpsr);
210 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
211
212DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
213 int n = cpu->gprs[rn] + !ARMPSRIsC(cpu->cpsr);
214 int d = cpu->gprs[rd];
215 cpu->gprs[rd] = d - n;
216 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
217DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
218 int rs = cpu->gprs[rn] & 0xFF;
219 if (rs) {
220 int r4 = rs & 0x1F;
221 if (r4 > 0) {
222 cpu->cpsr = ARMPSRSetC(cpu->cpsr, (cpu->gprs[rd] >> (r4 - 1)) & 1);
223 cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
224 } else {
225 cpu->cpsr = ARMPSRSetC(cpu->cpsr, ARM_SIGN(cpu->gprs[rd]));
226 }
227 }
228 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
231DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
232DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
233DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
234DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
235DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
236DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
237
238#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
239 DEFINE_INSTRUCTION_THUMB(NAME, \
240 int rd = (opcode & 0x0007) | H1; \
241 int rm = ((opcode >> 3) & 0x0007) | H2; \
242 BODY;)
243
244#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
245 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
246 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
247 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
248 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
249
250DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
251 cpu->gprs[rd] += cpu->gprs[rm];
252 if (rd == ARM_PC) {
253 THUMB_WRITE_PC;
254 })
255
256DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
257DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
258 cpu->gprs[rd] = cpu->gprs[rm];
259 if (rd == ARM_PC) {
260 THUMB_WRITE_PC;
261 })
262
263#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
264 DEFINE_INSTRUCTION_THUMB(NAME, \
265 int rd = (opcode >> 8) & 0x0007; \
266 int immediate = (opcode & 0x00FF) << 2; \
267 BODY;)
268
269DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
270DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
271DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
272
273DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
274DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
275
276#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
277 DEFINE_INSTRUCTION_THUMB(NAME, \
278 int rm = (opcode >> 6) & 0x0007; \
279 int rd = opcode & 0x0007; \
280 int rn = (opcode >> 3) & 0x0007; \
281 BODY;)
282
283DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
284DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
285DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
286DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles)); THUMB_LOAD_POST_BODY;)
287DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, rm = cpu->gprs[rn] + cpu->gprs[rm]; cpu->gprs[rd] = rm & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, rm, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, rm, ¤tCycles)); THUMB_LOAD_POST_BODY;)
288DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
289DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
290DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
291
292#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
293 DEFINE_INSTRUCTION_THUMB(NAME, \
294 int rn = RN; \
295 UNUSED(rn); \
296 int rs = opcode & 0xFF; \
297 int32_t address = cpu->gprs[RN]; \
298 PRE_BODY; \
299 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
300 WRITEBACK;)
301
302DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
303 (opcode >> 8) & 0x0007,
304 load,
305 IA,
306 ,
307 THUMB_LOAD_POST_BODY;
308 if (!((1 << rn) & rs)) {
309 cpu->gprs[rn] = address;
310 })
311
312DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
313 (opcode >> 8) & 0x0007,
314 store,
315 IA,
316 ,
317 THUMB_STORE_POST_BODY;
318 cpu->gprs[rn] = address;)
319
320#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
321 DEFINE_INSTRUCTION_THUMB(B ## COND, \
322 if (ARM_COND_ ## COND) { \
323 int8_t immediate = opcode; \
324 cpu->gprs[ARM_PC] += (int32_t) immediate << 1; \
325 THUMB_WRITE_PC; \
326 })
327
328DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
329DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
330DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
331DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
332DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
333DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
334DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
335DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
336DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
337DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
338DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
339DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
340DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
341DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
342
343DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
344DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
345
346DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
347 ARM_SP,
348 load,
349 IA,
350 ,
351 THUMB_LOAD_POST_BODY;
352 cpu->gprs[ARM_SP] = address)
353
354DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
355 ARM_SP,
356 load,
357 IA,
358 rs |= 1 << ARM_PC,
359 THUMB_LOAD_POST_BODY;
360 cpu->gprs[ARM_SP] = address;
361 THUMB_WRITE_PC;)
362
363DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
364 ARM_SP,
365 store,
366 DB,
367 ,
368 THUMB_STORE_POST_BODY;
369 cpu->gprs[ARM_SP] = address)
370
371DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
372 ARM_SP,
373 store,
374 DB,
375 rs |= 1 << ARM_LR,
376 THUMB_STORE_POST_BODY;
377 cpu->gprs[ARM_SP] = address)
378
379DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
380DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
381DEFINE_INSTRUCTION_THUMB(B,
382 int16_t immediate = (opcode & 0x07FF) << 5;
383 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
384 THUMB_WRITE_PC;)
385
386DEFINE_INSTRUCTION_THUMB(BL1,
387 int16_t immediate = (opcode & 0x07FF) << 5;
388 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
389
390DEFINE_INSTRUCTION_THUMB(BL2,
391 uint16_t immediate = (opcode & 0x07FF) << 1;
392 uint32_t pc = cpu->gprs[ARM_PC];
393 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
394 cpu->gprs[ARM_LR] = pc - 1;
395 THUMB_WRITE_PC;)
396
397DEFINE_INSTRUCTION_THUMB(BX,
398 int rm = (opcode >> 3) & 0xF;
399 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
400 int misalign = 0;
401 if (rm == ARM_PC) {
402 misalign = cpu->gprs[rm] & 0x00000002;
403 }
404 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
405 if (cpu->executionMode == MODE_THUMB) {
406 THUMB_WRITE_PC;
407 } else {
408 ARM_WRITE_PC;
409 })
410
411DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
412
413const ThumbInstruction _thumbTable[0x400] = {
414 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
415};