src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int shift = cpu->gprs[rs];
23 if (rs == ARM_PC) {
24 shift += 4;
25 }
26 shift &= 0xFF;
27 int32_t shiftVal = cpu->gprs[rm];
28 if (rm == ARM_PC) {
29 shiftVal += 4;
30 }
31 if (!shift) {
32 cpu->shifterOperand = shiftVal;
33 cpu->shifterCarryOut = cpu->cpsr.c;
34 } else if (shift < 32) {
35 cpu->shifterOperand = shiftVal << shift;
36 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
37 } else if (shift == 32) {
38 cpu->shifterOperand = 0;
39 cpu->shifterCarryOut = shiftVal & 1;
40 } else {
41 cpu->shifterOperand = 0;
42 cpu->shifterCarryOut = 0;
43 }
44 } else {
45 int immediate = (opcode & 0x00000F80) >> 7;
46 if (!immediate) {
47 cpu->shifterOperand = cpu->gprs[rm];
48 cpu->shifterCarryOut = cpu->cpsr.c;
49 } else {
50 cpu->shifterOperand = cpu->gprs[rm] << immediate;
51 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
52 }
53 }
54}
55
56static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
57 int rm = opcode & 0x0000000F;
58 if (opcode & 0x00000010) {
59 int rs = (opcode >> 8) & 0x0000000F;
60 ++cpu->cycles;
61 int shift = cpu->gprs[rs];
62 if (rs == ARM_PC) {
63 shift += 4;
64 }
65 shift &= 0xFF;
66 uint32_t shiftVal = cpu->gprs[rm];
67 if (rm == ARM_PC) {
68 shiftVal += 4;
69 }
70 if (!shift) {
71 cpu->shifterOperand = shiftVal;
72 cpu->shifterCarryOut = cpu->cpsr.c;
73 } else if (shift < 32) {
74 cpu->shifterOperand = shiftVal >> shift;
75 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
76 } else if (shift == 32) {
77 cpu->shifterOperand = 0;
78 cpu->shifterCarryOut = shiftVal >> 31;
79 } else {
80 cpu->shifterOperand = 0;
81 cpu->shifterCarryOut = 0;
82 }
83 } else {
84 int immediate = (opcode & 0x00000F80) >> 7;
85 if (immediate) {
86 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
87 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
88 } else {
89 cpu->shifterOperand = 0;
90 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
91 }
92 }
93}
94
95static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
96 int rm = opcode & 0x0000000F;
97 if (opcode & 0x00000010) {
98 int rs = (opcode >> 8) & 0x0000000F;
99 ++cpu->cycles;
100 int shift = cpu->gprs[rs];
101 if (rs == ARM_PC) {
102 shift += 4;
103 }
104 shift &= 0xFF;
105 int shiftVal = cpu->gprs[rm];
106 if (rm == ARM_PC) {
107 shiftVal += 4;
108 }
109 if (!shift) {
110 cpu->shifterOperand = shiftVal;
111 cpu->shifterCarryOut = cpu->cpsr.c;
112 } else if (shift < 32) {
113 cpu->shifterOperand = shiftVal >> shift;
114 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
115 } else if (cpu->gprs[rm] >> 31) {
116 cpu->shifterOperand = 0xFFFFFFFF;
117 cpu->shifterCarryOut = 1;
118 } else {
119 cpu->shifterOperand = 0;
120 cpu->shifterCarryOut = 0;
121 }
122 } else {
123 int immediate = (opcode & 0x00000F80) >> 7;
124 if (immediate) {
125 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
126 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
127 } else {
128 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
129 cpu->shifterOperand = cpu->shifterCarryOut;
130 }
131 }
132}
133
134static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
135 int rm = opcode & 0x0000000F;
136 if (opcode & 0x00000010) {
137 int rs = (opcode >> 8) & 0x0000000F;
138 ++cpu->cycles;
139 int shift = cpu->gprs[rs];
140 if (rs == ARM_PC) {
141 shift += 4;
142 }
143 shift &= 0xFF;
144 int shiftVal = cpu->gprs[rm];
145 if (rm == ARM_PC) {
146 shiftVal += 4;
147 }
148 int rotate = shift & 0x1F;
149 if (!shift) {
150 cpu->shifterOperand = shiftVal;
151 cpu->shifterCarryOut = cpu->cpsr.c;
152 } else if (rotate) {
153 cpu->shifterOperand = ROR(shiftVal, rotate);
154 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
155 } else {
156 cpu->shifterOperand = shiftVal;
157 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
158 }
159 } else {
160 int immediate = (opcode & 0x00000F80) >> 7;
161 if (immediate) {
162 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
163 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
164 } else {
165 // RRX
166 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
167 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
168 }
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
188 cpu->cpsr.flags = 0;
189 cpu->cpsr.n = ARM_SIGN(d);
190 cpu->cpsr.z = !d;
191 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
192 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
193}
194
195ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
196 cpu->cpsr.flags = 0;
197 cpu->cpsr.n = ARM_SIGN(d);
198 cpu->cpsr.z = !d;
199 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
200 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
201}
202
203ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
204 cpu->cpsr.n = ARM_SIGN(d);
205 cpu->cpsr.z = !d; \
206 cpu->cpsr.c = cpu->shifterCarryOut; \
207}
208
209#define ARM_ADDITION_S(M, N, D) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 _additionS(cpu, M, N, D); \
215 }
216
217#define ARM_SUBTRACTION_S(M, N, D) \
218 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
219 cpu->cpsr = cpu->spsr; \
220 _ARMReadCPSR(cpu); \
221 } else { \
222 _subtractionS(cpu, M, N, D); \
223 }
224
225#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
226 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
227 cpu->cpsr = cpu->spsr; \
228 _ARMReadCPSR(cpu); \
229 } else { \
230 cpu->cpsr.n = ARM_SIGN(D); \
231 cpu->cpsr.z = !(D); \
232 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
233 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
234 }
235
236#define ARM_NEUTRAL_S(M, N, D) \
237 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
238 cpu->cpsr = cpu->spsr; \
239 _ARMReadCPSR(cpu); \
240 } else { \
241 _neutralS(cpu, D); \
242 }
243
244#define ARM_NEUTRAL_HI_S(DLO, DHI) \
245 cpu->cpsr.n = ARM_SIGN(DHI); \
246 cpu->cpsr.z = !((DHI) | (DLO));
247
248#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
249#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
250#define ADDR_MODE_2_ADDRESS (address)
251#define ADDR_MODE_2_RN (cpu->gprs[rn])
252#define ADDR_MODE_2_RM (cpu->gprs[rm])
253#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
254#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
255#define ADDR_MODE_2_WRITEBACK(ADDR) \
256 cpu->gprs[rn] = ADDR; \
257 if (UNLIKELY(rn == ARM_PC)) { \
258 currentCycles += ARMWritePC(cpu); \
259 }
260
261#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
262#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
263#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
264#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
265
266#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
267#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
268#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
269#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
270
271#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
272#define ADDR_MODE_3_RN ADDR_MODE_2_RN
273#define ADDR_MODE_3_RM ADDR_MODE_2_RM
274#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
275#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
276#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
277
278#define ADDR_MODE_4_WRITEBACK_LDM \
279 if (!((1 << rn) & rs)) { \
280 cpu->gprs[rn] = address; \
281 }
282
283#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
284
285#define ARM_LOAD_POST_BODY \
286 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
287 if (rd == ARM_PC) { \
288 currentCycles += ARMWritePC(cpu); \
289 }
290
291#define ARM_STORE_POST_BODY \
292 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
293
294#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
295 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
296 int currentCycles = ARM_PREFETCH_CYCLES; \
297 BODY; \
298 cpu->cycles += currentCycles; \
299 }
300
301#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
302 DEFINE_INSTRUCTION_ARM(NAME, \
303 int rd = (opcode >> 12) & 0xF; \
304 int rn = (opcode >> 16) & 0xF; \
305 int32_t n = cpu->gprs[rn]; \
306 if (UNLIKELY(rn == ARM_PC && (opcode & 0x02000010) == 0x00000010)) { \
307 n += WORD_SIZE_ARM; \
308 } \
309 SHIFTER(cpu, opcode); \
310 BODY; \
311 S_BODY; \
312 if (rd == ARM_PC) { \
313 if (cpu->executionMode == MODE_ARM) { \
314 currentCycles += ARMWritePC(cpu); \
315 } else { \
316 currentCycles += ThumbWritePC(cpu); \
317 } \
318 })
319
320#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
322 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
323 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
324 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
325 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
326 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
327 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
328 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
329 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
330 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
331
332#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
333 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
334 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
335 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
336 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
337 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
338
339#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
340 DEFINE_INSTRUCTION_ARM(NAME, \
341 int rd = (opcode >> 16) & 0xF; \
342 int rs = (opcode >> 8) & 0xF; \
343 int rm = opcode & 0xF; \
344 if (rd == ARM_PC) { \
345 return; \
346 } \
347 ARM_WAIT_MUL(cpu->gprs[rs]); \
348 BODY; \
349 S_BODY; \
350 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
351
352#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
353 DEFINE_INSTRUCTION_ARM(NAME, \
354 int rd = (opcode >> 12) & 0xF; \
355 int rdHi = (opcode >> 16) & 0xF; \
356 int rs = (opcode >> 8) & 0xF; \
357 int rm = opcode & 0xF; \
358 if (rdHi == ARM_PC || rd == ARM_PC) { \
359 return; \
360 } \
361 currentCycles += cpu->memory.stall(cpu, WAIT); \
362 BODY; \
363 S_BODY; \
364 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
365
366#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
367 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
368 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
369
370#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
371 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
372 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
373
374#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
375 DEFINE_INSTRUCTION_ARM(NAME, \
376 uint32_t address; \
377 int rn = (opcode >> 16) & 0xF; \
378 int rd = (opcode >> 12) & 0xF; \
379 int32_t d = cpu->gprs[rd]; \
380 if (UNLIKELY(rd == ARM_PC)) { \
381 d += WORD_SIZE_ARM; \
382 } \
383 int rm = opcode & 0xF; \
384 UNUSED(rm); \
385 address = ADDRESS; \
386 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
387 BODY; \
388 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
389
390#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
397
398#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
405 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
406 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
409
410#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
412 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
413 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
414 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
417 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
418 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
419 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
420 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
421 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
422 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
423
424#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
425 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
426 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
427
428#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
429 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
430 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
431 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
432 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
433 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
434 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
435
436#define ARM_MS_PRE_store \
437 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
438 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
439
440#define ARM_MS_PRE_load \
441 enum PrivilegeMode privilegeMode; \
442 if (!(rs & 0x8000)) { \
443 privilegeMode = cpu->privilegeMode; \
444 ARMSetPrivilegeMode(cpu, MODE_SYSTEM); \
445 }
446
447#define ARM_MS_POST_store ARMSetPrivilegeMode(cpu, privilegeMode);
448
449#define ARM_MS_POST_load \
450 if (!(rs & 0x8000)) { \
451 ARMSetPrivilegeMode(cpu, privilegeMode); \
452 } else if (_ARMModeHasSPSR(cpu->cpsr.priv)) { \
453 cpu->cpsr = cpu->spsr; \
454 _ARMReadCPSR(cpu); \
455 }
456
457#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
458 DEFINE_INSTRUCTION_ARM(NAME, \
459 int rn = (opcode >> 16) & 0xF; \
460 int rs = opcode & 0x0000FFFF; \
461 uint32_t address = cpu->gprs[rn]; \
462 S_PRE; \
463 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
464 WRITEBACK; \
465 S_POST; \
466 POST_BODY;)
467
468
469#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
470 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
471 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
472 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
473 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
474 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
475 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
476 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
477 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
478 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
479 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
480 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
481 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
482 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
483 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
484 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY) \
485 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY)
486
487// Begin ALU definitions
488
489DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
490 cpu->gprs[rd] = n + cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
493 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
494
495DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
496 cpu->gprs[rd] = n & cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = n & ~cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(n, cpu->shifterOperand, aluOut),
502 int32_t aluOut = n + cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(n, cpu->shifterOperand, aluOut),
505 int32_t aluOut = n - cpu->shifterOperand;)
506
507DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
508 cpu->gprs[rd] = n ^ cpu->shifterOperand;)
509
510DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
511 cpu->gprs[rd] = cpu->shifterOperand;)
512
513DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
514 cpu->gprs[rd] = ~cpu->shifterOperand;)
515
516DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
517 cpu->gprs[rd] = n | cpu->shifterOperand;)
518
519DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
520 cpu->gprs[rd] = cpu->shifterOperand - n;)
521
522DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
523 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
524
525DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
526 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
527
528DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
529 cpu->gprs[rd] = n - cpu->shifterOperand;)
530
531DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
532 int32_t aluOut = n ^ cpu->shifterOperand;)
533
534DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
535 int32_t aluOut = n & cpu->shifterOperand;)
536
537// End ALU definitions
538
539// Begin multiply definitions
540
541DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
542DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
543
544DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
545 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
546 int32_t dm = cpu->gprs[rd];
547 int32_t dn = d;
548 cpu->gprs[rd] = dm + dn;
549 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
550 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
551
552DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
553 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
554 cpu->gprs[rd] = d;
555 cpu->gprs[rdHi] = d >> 32;,
556 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
557
558DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
559 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
560 int32_t dm = cpu->gprs[rd];
561 int32_t dn = d;
562 cpu->gprs[rd] = dm + dn;
563 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
564 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
565
566DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
567 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
568 cpu->gprs[rd] = d;
569 cpu->gprs[rdHi] = d >> 32;,
570 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
571
572// End multiply definitions
573
574// Begin load/store definitions
575
576DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
577DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
578DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
579DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
580DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
581DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
582DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
583DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
584
585DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
586 enum PrivilegeMode priv = cpu->privilegeMode;
587 ARMSetPrivilegeMode(cpu, MODE_USER);
588 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
589 ARMSetPrivilegeMode(cpu, priv);
590 cpu->gprs[rd] = r;
591 ARM_LOAD_POST_BODY;)
592
593DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
594 enum PrivilegeMode priv = cpu->privilegeMode;
595 ARMSetPrivilegeMode(cpu, MODE_USER);
596 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
597 ARMSetPrivilegeMode(cpu, priv);
598 cpu->gprs[rd] = r;
599 ARM_LOAD_POST_BODY;)
600
601DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
602 enum PrivilegeMode priv = cpu->privilegeMode;
603 int32_t r = cpu->gprs[rd];
604 ARMSetPrivilegeMode(cpu, MODE_USER);
605 cpu->memory.store8(cpu, address, r, ¤tCycles);
606 ARMSetPrivilegeMode(cpu, priv);
607 ARM_STORE_POST_BODY;)
608
609DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
610 enum PrivilegeMode priv = cpu->privilegeMode;
611 int32_t r = cpu->gprs[rd];
612 ARMSetPrivilegeMode(cpu, MODE_USER);
613 cpu->memory.store32(cpu, address, r, ¤tCycles);
614 ARMSetPrivilegeMode(cpu, priv);
615 ARM_STORE_POST_BODY;)
616
617DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
618 load,
619 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
620 if ((rs & 0x8000) || !rs) {
621 if (cpu->executionMode == MODE_THUMB) {
622 currentCycles += ThumbWritePC(cpu);
623 } else {
624 currentCycles += ARMWritePC(cpu);
625 }
626 })
627
628DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
629 store,
630 ARM_STORE_POST_BODY;)
631
632DEFINE_INSTRUCTION_ARM(SWP,
633 int rm = opcode & 0xF;
634 int rd = (opcode >> 12) & 0xF;
635 int rn = (opcode >> 16) & 0xF;
636 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
637 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
638 cpu->gprs[rd] = d;)
639
640DEFINE_INSTRUCTION_ARM(SWPB,
641 int rm = opcode & 0xF;
642 int rd = (opcode >> 12) & 0xF;
643 int rn = (opcode >> 16) & 0xF;
644 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
645 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
646 cpu->gprs[rd] = d;)
647
648// End load/store definitions
649
650// Begin branch definitions
651
652DEFINE_INSTRUCTION_ARM(B,
653 int32_t offset = opcode << 8;
654 offset >>= 6;
655 cpu->gprs[ARM_PC] += offset;
656 currentCycles += ARMWritePC(cpu);)
657
658DEFINE_INSTRUCTION_ARM(BL,
659 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
660 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
661 cpu->gprs[ARM_PC] += immediate >> 6;
662 currentCycles += ARMWritePC(cpu);)
663
664DEFINE_INSTRUCTION_ARM(BX,
665 int rm = opcode & 0x0000000F;
666 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
667 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
668 if (cpu->executionMode == MODE_THUMB) {
669 currentCycles += ThumbWritePC(cpu);
670 } else {
671 currentCycles += ARMWritePC(cpu);
672 })
673
674// End branch definitions
675
676// Begin coprocessor definitions
677
678DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
679DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
680DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
681DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
682DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
683
684// Begin miscellaneous definitions
685
686DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
687DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
688
689DEFINE_INSTRUCTION_ARM(MSR,
690 int c = opcode & 0x00010000;
691 int f = opcode & 0x00080000;
692 int32_t operand = cpu->gprs[opcode & 0x0000000F];
693 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
694 if (mask & PSR_USER_MASK) {
695 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
696 }
697 if (mask & PSR_STATE_MASK) {
698 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
699 }
700 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
701 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
702 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
703 }
704 _ARMReadCPSR(cpu);
705 if (cpu->executionMode == MODE_THUMB) {
706 cpu->prefetch[0] = 0x46C0; // nop
707 cpu->prefetch[1] &= 0xFFFF;
708 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
709 } else {
710 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
711 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
712 })
713
714DEFINE_INSTRUCTION_ARM(MSRR,
715 int c = opcode & 0x00010000;
716 int f = opcode & 0x00080000;
717 int32_t operand = cpu->gprs[opcode & 0x0000000F];
718 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
719 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
720 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
721
722DEFINE_INSTRUCTION_ARM(MRS, \
723 int rd = (opcode >> 12) & 0xF; \
724 cpu->gprs[rd] = cpu->cpsr.packed;)
725
726DEFINE_INSTRUCTION_ARM(MRSR, \
727 int rd = (opcode >> 12) & 0xF; \
728 cpu->gprs[rd] = cpu->spsr.packed;)
729
730DEFINE_INSTRUCTION_ARM(MSRI,
731 int c = opcode & 0x00010000;
732 int f = opcode & 0x00080000;
733 int rotate = (opcode & 0x00000F00) >> 7;
734 int32_t operand = ROR(opcode & 0x000000FF, rotate);
735 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
736 if (mask & PSR_USER_MASK) {
737 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
738 }
739 if (mask & PSR_STATE_MASK) {
740 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
741 }
742 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
743 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
744 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
745 }
746 _ARMReadCPSR(cpu);
747 if (cpu->executionMode == MODE_THUMB) {
748 cpu->prefetch[0] = 0x46C0; // nop
749 cpu->prefetch[1] &= 0xFFFF;
750 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
751 } else {
752 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
753 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
754 })
755
756DEFINE_INSTRUCTION_ARM(MSRRI,
757 int c = opcode & 0x00010000;
758 int f = opcode & 0x00080000;
759 int rotate = (opcode & 0x00000F00) >> 7;
760 int32_t operand = ROR(opcode & 0x000000FF, rotate);
761 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
762 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
763 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
764
765DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
766
767const ARMInstruction _armTable[0x1000] = {
768 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
769};