src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 int rs = (opcode >> 8) & 0x0000000F;
28 ++cpu->cycles;
29 int shift = cpu->gprs[rs];
30 if (rs == ARM_PC) {
31 shift += 4;
32 }
33 shift &= 0xFF;
34 int32_t shiftVal = cpu->gprs[rm];
35 if (rm == ARM_PC) {
36 shiftVal += 4;
37 }
38 if (!shift) {
39 cpu->shifterOperand = shiftVal;
40 cpu->shifterCarryOut = cpu->cpsr.c;
41 } else if (shift < 32) {
42 cpu->shifterOperand = shiftVal << shift;
43 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
44 } else if (shift == 32) {
45 cpu->shifterOperand = 0;
46 cpu->shifterCarryOut = shiftVal & 1;
47 } else {
48 cpu->shifterOperand = 0;
49 cpu->shifterCarryOut = 0;
50 }
51}
52
53static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
54 int rm = opcode & 0x0000000F;
55 int immediate = (opcode & 0x00000F80) >> 7;
56 if (immediate) {
57 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
58 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
59 } else {
60 cpu->shifterOperand = 0;
61 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
62 }
63}
64
65static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
66 int rm = opcode & 0x0000000F;
67 int rs = (opcode >> 8) & 0x0000000F;
68 ++cpu->cycles;
69 int shift = cpu->gprs[rs];
70 if (rs == ARM_PC) {
71 shift += 4;
72 }
73 shift &= 0xFF;
74 uint32_t shiftVal = cpu->gprs[rm];
75 if (rm == ARM_PC) {
76 shiftVal += 4;
77 }
78 if (!shift) {
79 cpu->shifterOperand = shiftVal;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else if (shift < 32) {
82 cpu->shifterOperand = shiftVal >> shift;
83 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
84 } else if (shift == 32) {
85 cpu->shifterOperand = 0;
86 cpu->shifterCarryOut = shiftVal >> 31;
87 } else {
88 cpu->shifterOperand = 0;
89 cpu->shifterCarryOut = 0;
90 }
91}
92
93static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
94 int rm = opcode & 0x0000000F;
95 int immediate = (opcode & 0x00000F80) >> 7;
96 if (immediate) {
97 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
98 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
99 } else {
100 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
101 cpu->shifterOperand = cpu->shifterCarryOut;
102 }
103}
104
105static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
106 int rm = opcode & 0x0000000F;
107 int rs = (opcode >> 8) & 0x0000000F;
108 ++cpu->cycles;
109 int shift = cpu->gprs[rs];
110 if (rs == ARM_PC) {
111 shift += 4;
112 }
113 shift &= 0xFF;
114 int shiftVal = cpu->gprs[rm];
115 if (rm == ARM_PC) {
116 shiftVal += 4;
117 }
118 if (!shift) {
119 cpu->shifterOperand = shiftVal;
120 cpu->shifterCarryOut = cpu->cpsr.c;
121 } else if (shift < 32) {
122 cpu->shifterOperand = shiftVal >> shift;
123 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
124 } else if (cpu->gprs[rm] >> 31) {
125 cpu->shifterOperand = 0xFFFFFFFF;
126 cpu->shifterCarryOut = 1;
127 } else {
128 cpu->shifterOperand = 0;
129 cpu->shifterCarryOut = 0;
130 }
131}
132
133static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
134 int rm = opcode & 0x0000000F;
135 int immediate = (opcode & 0x00000F80) >> 7;
136 if (immediate) {
137 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
138 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
139 } else {
140 // RRX
141 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
142 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
143 }
144}
145
146static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
147 int rm = opcode & 0x0000000F;
148 int rs = (opcode >> 8) & 0x0000000F;
149 ++cpu->cycles;
150 int shift = cpu->gprs[rs];
151 if (rs == ARM_PC) {
152 shift += 4;
153 }
154 shift &= 0xFF;
155 int shiftVal = cpu->gprs[rm];
156 if (rm == ARM_PC) {
157 shiftVal += 4;
158 }
159 int rotate = shift & 0x1F;
160 if (!shift) {
161 cpu->shifterOperand = shiftVal;
162 cpu->shifterCarryOut = cpu->cpsr.c;
163 } else if (rotate) {
164 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
165 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
166 } else {
167 cpu->shifterOperand = shiftVal;
168 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ARM_ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184// Instruction definitions
185// Beware pre-processor antics
186
187#define NO_EXTEND64(V) (uint64_t)(uint32_t) (V)
188
189#define ARM_ADDITION_S(M, N, D) \
190 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
191 cpu->cpsr = cpu->spsr; \
192 _ARMReadCPSR(cpu); \
193 } else { \
194 cpu->cpsr.n = ARM_SIGN(D); \
195 cpu->cpsr.z = !(D); \
196 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
197 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
198 }
199
200#define ARM_SUBTRACTION_S(M, N, D) \
201 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
202 cpu->cpsr = cpu->spsr; \
203 _ARMReadCPSR(cpu); \
204 } else { \
205 cpu->cpsr.n = ARM_SIGN(D); \
206 cpu->cpsr.z = !(D); \
207 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
208 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
209 }
210
211#define ARM_NEUTRAL_S(M, N, D) \
212 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
213 cpu->cpsr = cpu->spsr; \
214 _ARMReadCPSR(cpu); \
215 } else { \
216 cpu->cpsr.n = ARM_SIGN(D); \
217 cpu->cpsr.z = !(D); \
218 cpu->cpsr.c = cpu->shifterCarryOut; \
219 }
220
221#define ARM_NEUTRAL_HI_S(DLO, DHI) \
222 cpu->cpsr.n = ARM_SIGN(DHI); \
223 cpu->cpsr.z = !((DHI) | (DLO));
224
225#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
226#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
227#define ADDR_MODE_2_ADDRESS (address)
228#define ADDR_MODE_2_RN (cpu->gprs[rn])
229#define ADDR_MODE_2_RM (cpu->gprs[rm])
230#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
231#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
232#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
233#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
234#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
235#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
236#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
237
238#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
239#define ADDR_MODE_3_RN ADDR_MODE_2_RN
240#define ADDR_MODE_3_RM ADDR_MODE_2_RM
241#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
242#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
243#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
244
245#define ARM_LOAD_POST_BODY \
246 if (rd == ARM_PC) { \
247 ARM_WRITE_PC; \
248 }
249
250#define ARM_STORE_POST_BODY \
251 currentCycles -= ARM_PREFETCH_CYCLES; \
252 currentCycles += 1 + cpu->memory->activeNonseqCycles32;
253
254#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
255 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
256 int currentCycles = ARM_PREFETCH_CYCLES; \
257 BODY; \
258 cpu->cycles += currentCycles; \
259 }
260
261#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
262 DEFINE_INSTRUCTION_ARM(NAME, \
263 int rd = (opcode >> 12) & 0xF; \
264 int rn = (opcode >> 16) & 0xF; \
265 UNUSED(rn); \
266 SHIFTER(cpu, opcode); \
267 BODY; \
268 S_BODY; \
269 if (rd == ARM_PC) { \
270 if (cpu->executionMode == MODE_ARM) { \
271 ARM_WRITE_PC; \
272 } else { \
273 THUMB_WRITE_PC; \
274 } \
275 })
276
277#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
278 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
279 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
280 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
281 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
282 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
283 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
284 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
285 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
286 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
287 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
288 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
289 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
290 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
291 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
292 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
293 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
294 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
295 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
296
297#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
298 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
299 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
300 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
301 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
307
308#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
309 DEFINE_INSTRUCTION_ARM(NAME, \
310 int rd = (opcode >> 12) & 0xF; \
311 int rdHi = (opcode >> 16) & 0xF; \
312 int rs = (opcode >> 8) & 0xF; \
313 int rm = opcode & 0xF; \
314 UNUSED(rdHi); \
315 ARM_WAIT_MUL(cpu->gprs[rs]); \
316 BODY; \
317 S_BODY; \
318 if (rd == ARM_PC) { \
319 ARM_WRITE_PC; \
320 })
321
322#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
323 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
324 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
325
326#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
327 DEFINE_INSTRUCTION_ARM(NAME, \
328 uint32_t address; \
329 int rn = (opcode >> 16) & 0xF; \
330 int rd = (opcode >> 12) & 0xF; \
331 int rm = opcode & 0xF; \
332 UNUSED(rm); \
333 address = ADDRESS; \
334 WRITEBACK; \
335 BODY;)
336
337#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
338 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
339 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
340 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
341 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
342 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
343 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
344
345#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
346 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
347 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
348 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
349 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
350 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
351 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
352 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
353 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
354 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
355 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
356
357#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
358 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
359 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
360 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
361 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
362 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
363 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
364 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
365 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
366 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
367 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
370
371#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
374
375#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
376 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
377 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
378 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
379 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
382
383#define ARM_MS_PRE \
384 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
385 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
386
387#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
388
389#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
390#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
391#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
392#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
393#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
394#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
395#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
396#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
397
398#define ARM_M_INCREMENT(BODY) \
399 for (m = rs, i = 0; m; m >>= 1, ++i) { \
400 if (m & 1) { \
401 BODY; \
402 addr += 4; \
403 total += 1; \
404 } \
405 }
406
407#define ARM_M_DECREMENT(BODY) \
408 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
409 if (rs & m) { \
410 BODY; \
411 addr -= 4; \
412 total += 1; \
413 } \
414 }
415
416#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
417 DEFINE_INSTRUCTION_ARM(NAME, \
418 int rn = (opcode >> 16) & 0xF; \
419 int rs = opcode & 0x0000FFFF; \
420 int m; \
421 int i; \
422 int total = 0; \
423 ADDRESS; \
424 S_PRE; \
425 LOOP(BODY); \
426 S_POST; \
427 currentCycles += cpu->memory->waitMultiple(cpu->memory, addr, total); \
428 POST_BODY; \
429 WRITEBACK;)
430
431
432#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
433 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
434 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
435 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
436 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
437 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
438 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
439 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
440 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
441 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
442 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
443 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
444 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
445 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
446 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
449
450// Begin ALU definitions
451
452DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
453 int32_t n = cpu->gprs[rn];
454 cpu->gprs[rd] = n + cpu->shifterOperand;)
455
456DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
457 int32_t n = cpu->gprs[rn];
458 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
459
460DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
461 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
462
463DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
464 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
465
466DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
467 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
468
469DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
470 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
471
472DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
473 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
474
475DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
476 cpu->gprs[rd] = cpu->shifterOperand;)
477
478DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
479 cpu->gprs[rd] = ~cpu->shifterOperand;)
480
481DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
482 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
483
484DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
485 int32_t n = cpu->gprs[rn];
486 cpu->gprs[rd] = cpu->shifterOperand - n;)
487
488DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
489 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
490 cpu->gprs[rd] = cpu->shifterOperand - n;)
491
492DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
493 int32_t n = cpu->gprs[rn];
494 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
495 cpu->gprs[rd] = n - shifterOperand;)
496
497DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
498 int32_t n = cpu->gprs[rn];
499 cpu->gprs[rd] = n - cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
502 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
503
504DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
505 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
506
507// End ALU definitions
508
509// Begin multiply definitions
510
511DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
512DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
513
514DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
515 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
516 int32_t dm = cpu->gprs[rd];
517 int32_t dn = d;
518 cpu->gprs[rd] = dm + dn;
519 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
520 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
521
522DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
523 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
524 cpu->gprs[rd] = d;
525 cpu->gprs[rdHi] = d >> 32;,
526 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
527
528DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
529 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
530 int32_t dm = cpu->gprs[rd];
531 int32_t dn = d;
532 cpu->gprs[rd] = dm + dn;
533 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
534 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
535
536DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
537 uint64_t d = NO_EXTEND64(cpu->gprs[rm]) * NO_EXTEND64(cpu->gprs[rs]);
538 cpu->gprs[rd] = d;
539 cpu->gprs[rdHi] = d >> 32;,
540 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
541
542// End multiply definitions
543
544// Begin load/store definitions
545
546DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
547DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
548DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
549DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
550DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address, ¤tCycles); ARM_LOAD_POST_BODY;)
551DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
552DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
553DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
554
555DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
556 enum PrivilegeMode priv = cpu->privilegeMode;
557 ARMSetPrivilegeMode(cpu, MODE_USER);
558 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address, ¤tCycles);
559 ARMSetPrivilegeMode(cpu, priv);
560 ARM_LOAD_POST_BODY;)
561
562DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
563 enum PrivilegeMode priv = cpu->privilegeMode;
564 ARMSetPrivilegeMode(cpu, MODE_USER);
565 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address, ¤tCycles);
566 ARMSetPrivilegeMode(cpu, priv);
567 ARM_LOAD_POST_BODY;)
568
569DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
570 enum PrivilegeMode priv = cpu->privilegeMode;
571 ARMSetPrivilegeMode(cpu, MODE_USER);
572 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
573 ARMSetPrivilegeMode(cpu, priv);
574 ARM_STORE_POST_BODY;)
575
576DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
577 enum PrivilegeMode priv = cpu->privilegeMode;
578 ARMSetPrivilegeMode(cpu, MODE_USER);
579 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd], ¤tCycles);
580 ARMSetPrivilegeMode(cpu, priv);
581 ARM_STORE_POST_BODY;)
582
583DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
584 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr & 0xFFFFFFFC, 0);,
585 ++currentCycles;
586 if (rs & 0x8000) {
587 ARM_WRITE_PC;
588 })
589
590DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
591 cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);,
592 currentCycles += cpu->memory->activeNonseqCycles32 - cpu->memory->activePrefetchCycles32)
593
594DEFINE_INSTRUCTION_ARM(SWP,
595 int rm = opcode & 0xF;
596 int rd = (opcode >> 12) & 0xF;
597 int rn = (opcode >> 16) & 0xF;
598 int32_t d = cpu->memory->load32(cpu->memory, cpu->gprs[rn], ¤tCycles);
599 cpu->memory->store32(cpu->memory, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
600 cpu->gprs[rd] = d;)
601
602DEFINE_INSTRUCTION_ARM(SWPB,
603 int rm = opcode & 0xF;
604 int rd = (opcode >> 12) & 0xF;
605 int rn = (opcode >> 16) & 0xF;
606 int32_t d = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn], ¤tCycles);
607 cpu->memory->store8(cpu->memory, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
608 cpu->gprs[rd] = d;)
609
610// End load/store definitions
611
612// Begin branch definitions
613
614DEFINE_INSTRUCTION_ARM(B,
615 int32_t offset = opcode << 8;
616 offset >>= 6;
617 cpu->gprs[ARM_PC] += offset;
618 ARM_WRITE_PC;)
619
620DEFINE_INSTRUCTION_ARM(BL,
621 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
622 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
623 cpu->gprs[ARM_PC] += immediate >> 6;
624 ARM_WRITE_PC;)
625
626DEFINE_INSTRUCTION_ARM(BX,
627 int rm = opcode & 0x0000000F;
628 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
629 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
630 if (cpu->executionMode == MODE_THUMB) {
631 THUMB_WRITE_PC;
632 } else {
633 ARM_WRITE_PC;
634 })
635
636// End branch definitions
637
638// Begin coprocessor definitions
639
640DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
641DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
642DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
643DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
644DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
645
646// Begin miscellaneous definitions
647
648DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
649DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
650
651DEFINE_INSTRUCTION_ARM(MSR,
652 int c = opcode & 0x00010000;
653 int f = opcode & 0x00080000;
654 int32_t operand = cpu->gprs[opcode & 0x0000000F];
655 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
656 if (mask & PSR_USER_MASK) {
657 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
658 }
659 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
660 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
661 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
662 }
663 _ARMReadCPSR(cpu);)
664
665DEFINE_INSTRUCTION_ARM(MSRR,
666 int c = opcode & 0x00010000;
667 int f = opcode & 0x00080000;
668 int32_t operand = cpu->gprs[opcode & 0x0000000F];
669 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
670 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
671 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
672
673DEFINE_INSTRUCTION_ARM(MRS, \
674 int rd = (opcode >> 12) & 0xF; \
675 cpu->gprs[rd] = cpu->cpsr.packed;)
676
677DEFINE_INSTRUCTION_ARM(MRSR, \
678 int rd = (opcode >> 12) & 0xF; \
679 cpu->gprs[rd] = cpu->spsr.packed;)
680
681DEFINE_INSTRUCTION_ARM(MSRI,
682 int c = opcode & 0x00010000;
683 int f = opcode & 0x00080000;
684 int rotate = (opcode & 0x00000F00) >> 7;
685 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
686 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
687 if (mask & PSR_USER_MASK) {
688 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
689 }
690 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
691 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
692 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
693 }
694 _ARMReadCPSR(cpu);)
695
696DEFINE_INSTRUCTION_ARM(MSRRI,
697 int c = opcode & 0x00010000;
698 int f = opcode & 0x00080000;
699 int rotate = (opcode & 0x00000F00) >> 7;
700 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
701 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
702 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
703 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
704
705DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
706
707#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
708 EMITTER ## NAME
709
710#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
711 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
712 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
713
714#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
715 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
716 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
717 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
718 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
719 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
720 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
721 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
722 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
723 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
724 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
725 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
726 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
727 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
728 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
729 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
730 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
731
732#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
733 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
734 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
735
736#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
737 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
738 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
739 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
740 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
741 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
742 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
743 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
744 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
745 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
746 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
747 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
748 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
749 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
750 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
751 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
752 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
753
754#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
755 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
756 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
757
758#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
759 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
760
761// TODO: Support coprocessors
762#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
763 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
764 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
765
766#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
767 DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
768
769#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
770 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
771
772#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
773 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
774 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
775 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
776 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
777 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
778 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
779 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
780 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
781 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
782 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
783 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
784 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
785 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
786 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
787 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
788 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
789 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
790 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
791 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
792 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
793 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
794 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
795 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
796 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
797 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
798 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
799 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
800 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
801 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
802 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
803 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
804 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
805 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
806 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
807 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
808 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
809 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
822 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
823 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
825 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
826 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
827 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
828 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
829 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
830 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
831 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
832 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
833 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
834 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
835 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
836 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
837 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
838 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
839 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
840 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
841 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
842 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
843 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
844 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
845 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
846 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
847 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
848 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
849 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
850 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
851 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
852 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
853 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
854 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
855 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
856 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
857 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
858 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
859 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
860 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
861 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
862 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
863 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
864 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
865 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
866 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
867 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
868 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
869 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
870 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
871 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
872 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
873 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
874 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
875 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
876 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
877 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
878 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
879 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
880 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
881 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
882 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
883 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
884 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
885 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
886 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
887 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
888 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
889 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
890 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
891 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
892 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
893 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
894 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
895 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
896 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
897 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
898 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
899 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
900 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
901 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
902 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
903 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
904 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
905 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
906 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
907 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
908 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
909 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
910 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
911 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
912 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
913 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
914 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
915 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
916 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
917 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
918 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
919 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
920 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
921 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
922 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
923 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
924 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
925 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
926 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
927 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
928 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
929 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
930 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
931 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
932 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
933 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
934 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
935 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
936 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
937 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
938 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
939 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
940 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
941 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
942 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
943 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
944 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
945 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
946 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
947 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
948 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
949 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
950 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
951 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
952 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
953 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
954 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
955 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
956 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
957 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
958 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
959 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
960 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
961 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
962 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
963 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
964 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
965 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
966 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
967 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
968 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
969 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
970 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
971 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
972 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
973 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
974 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
975 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
976 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
977 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
978 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
979 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
980 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
981 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
982 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
983 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
984 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
985 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
986 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
987 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
988 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
989 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
990 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
991 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
992 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
993 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
994 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
995 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
996 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
997 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
998 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
999 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1000 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1001 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1002 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1003 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1004 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1005 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1006 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1007 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1008 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1009 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1010 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1011 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1012 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1013 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1014 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1015 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1016 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1017 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1018 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1019 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1020 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1021 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1022 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1023 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1024 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1025 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1026 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1027 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1028 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
1029 DECLARE_ARM_SWI_BLOCK(EMITTER)
1030
1031const ARMInstruction _armTable[0x1000] = {
1032 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1033};