1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/intr_timing.gb".
  3
  4[labels]
  501:47f0 check_asserts_cb
  601:4842 check_asserts_cb@check_asserts
  701:4864 check_asserts_cb@fail0
  801:4870 check_asserts_cb@ok0
  901:487a check_asserts_cb@skip0
 1001:4885 check_asserts_cb@out0
 1101:489c check_asserts_cb@fail1
 1201:48a8 check_asserts_cb@ok1
 1301:48b2 check_asserts_cb@skip1
 1401:48bd check_asserts_cb@out1
 1501:48dd check_asserts_cb@fail2
 1601:48e9 check_asserts_cb@ok2
 1701:48f3 check_asserts_cb@skip2
 1801:48fe check_asserts_cb@out2
 1901:4915 check_asserts_cb@fail3
 2001:4921 check_asserts_cb@ok3
 2101:492b check_asserts_cb@skip3
 2201:4936 check_asserts_cb@out3
 2301:4956 check_asserts_cb@fail4
 2401:4962 check_asserts_cb@ok4
 2501:496c check_asserts_cb@skip4
 2601:4977 check_asserts_cb@out4
 2701:498e check_asserts_cb@fail5
 2801:499a check_asserts_cb@ok5
 2901:49a4 check_asserts_cb@skip5
 3001:49af check_asserts_cb@out5
 3101:49cf check_asserts_cb@fail6
 3201:49db check_asserts_cb@ok6
 3301:49e5 check_asserts_cb@skip6
 3401:49f0 check_asserts_cb@out6
 3501:4a07 check_asserts_cb@fail7
 3601:4a13 check_asserts_cb@ok7
 3701:4a1d check_asserts_cb@skip7
 3801:4a28 check_asserts_cb@out7
 3900:ff80 hram.regs_save
 4000:ff80 hram.regs_save.reg_f
 4100:ff81 hram.regs_save.reg_a
 4200:ff82 hram.regs_save.reg_c
 4300:ff83 hram.regs_save.reg_b
 4400:ff84 hram.regs_save.reg_e
 4500:ff85 hram.regs_save.reg_d
 4600:ff86 hram.regs_save.reg_l
 4700:ff87 hram.regs_save.reg_h
 4800:ff88 hram.regs_flags
 4900:ff89 hram.regs_assert
 5000:ff89 hram.regs_assert.reg_f
 5100:ff8a hram.regs_assert.reg_a
 5200:ff8b hram.regs_assert.reg_c
 5300:ff8c hram.regs_assert.reg_b
 5400:ff8d hram.regs_assert.reg_e
 5500:ff8e hram.regs_assert.reg_d
 5600:ff8f hram.regs_assert.reg_l
 5700:ff90 hram.regs_assert.reg_h
 5801:4b85 clear_vram
 5901:4b44 disable_lcd_safe
 6001:4b4a disable_lcd_safe@wait_ly_0
 6101:4b99 memcpy
 6201:4ba2 memset
 6301:4b62 print_hex4
 6401:4b8f print_hex8
 6501:4bb2 print_inline_string
 6601:4b6e print_load_font
 6701:4b7a print_newline
 6801:4a2b print_reg_dump
 6901:4bab print_string
 7001:4ab0 quit
 7101:4ac5 quit@cb_return
 7201:4aca quit@wait_ly_1
 7301:4ad0 quit@wait_ly_2
 7401:4ad6 quit@wait_ly_3
 7501:4adc quit@wait_ly_4
 7601:4ae6 quit@success
 7701:4b0d quit@failure
 7801:4b2c quit@halt
 7901:4b2d quit@halt_execution_0
 8001:4b30 reset_screen
 8101:4b53 serial_send_byte
 8201:4000 font
 8300:0150 main
 8400:0157 test_round1
 8500:019a test_round1@quit_inline_1
 8600:01b1 finish_round1
 8700:01b3 test_round2
 8800:01f7 test_round2@quit_inline_2
 8900:020e finish_round2
 9000:0213 test_finish
 91
 92[definitions]
 930000023b _sizeof_check_asserts_cb
 9400000008 _sizeof_hram.regs_save
 9500000001 _sizeof_hram.regs_save.reg_f
 9600000001 _sizeof_hram.regs_save.reg_a
 9700000001 _sizeof_hram.regs_save.reg_c
 9800000001 _sizeof_hram.regs_save.reg_b
 9900000001 _sizeof_hram.regs_save.reg_e
10000000001 _sizeof_hram.regs_save.reg_d
10100000001 _sizeof_hram.regs_save.reg_l
10200000001 _sizeof_hram.regs_save.reg_h
10300000001 _sizeof_hram.regs_flags
10400000008 _sizeof_hram.regs_assert
10500000001 _sizeof_hram.regs_assert.reg_f
10600000001 _sizeof_hram.regs_assert.reg_a
10700000001 _sizeof_hram.regs_assert.reg_c
10800000001 _sizeof_hram.regs_assert.reg_b
10900000001 _sizeof_hram.regs_assert.reg_e
11000000001 _sizeof_hram.regs_assert.reg_d
11100000001 _sizeof_hram.regs_assert.reg_l
11200000001 _sizeof_hram.regs_assert.reg_h
1130000000a _sizeof_clear_vram
1140000000f _sizeof_disable_lcd_safe
11500000009 _sizeof_memcpy
11600000009 _sizeof_memset
1170000000c _sizeof_print_hex4
1180000000a _sizeof_print_hex8
11900000006 _sizeof_print_inline_string
1200000000c _sizeof_print_load_font
1210000000b _sizeof_print_newline
12200000085 _sizeof_print_reg_dump
12300000007 _sizeof_print_string
12400000080 _sizeof_quit
12500000014 _sizeof_reset_screen
1260000000f _sizeof_serial_send_byte
127000007f0 _sizeof_font
12800000007 _sizeof_main
1290000005a _sizeof_test_round1
13000000002 _sizeof_finish_round1
1310000005b _sizeof_test_round2
13200000005 _sizeof_finish_round2