1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_VRAM = 0x4000,
 48	GB_SIZE_VRAM_BANK0 = 0x2000,
 49	GB_SIZE_EXTERNAL_RAM = 0x2000,
 50	GB_SIZE_WORKING_RAM = 0x8000,
 51	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 52	GB_SIZE_OAM = 0xA0,
 53	GB_SIZE_IO = 0x80,
 54	GB_SIZE_HRAM = 0x7F,
 55};
 56
 57enum GBMemoryBankControllerType {
 58	GB_MBC_NONE = 0,
 59	GB_MBC1 = 1,
 60	GB_MBC2 = 2,
 61	GB_MBC3 = 3,
 62	GB_MBC5 = 5,
 63	GB_MBC6 = 6,
 64	GB_MBC7 = 7,
 65	GB_MMM01 = 0x10,
 66	GB_HuC1 = 0x11,
 67	GB_HuC3 = 0x12,
 68	GB_MBC5_RUMBLE = 0x105
 69};
 70
 71struct GBMemory;
 72typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 73
 74DECL_BITFIELD(GBMBC7Field, uint8_t);
 75DECL_BIT(GBMBC7Field, SK, 6);
 76DECL_BIT(GBMBC7Field, CS, 7);
 77DECL_BIT(GBMBC7Field, IO, 1);
 78
 79enum GBMBC7MachineState {
 80	GBMBC7_STATE_NULL = -1,
 81	GBMBC7_STATE_IDLE = 0,
 82	GBMBC7_STATE_READ_COMMAND = 1,
 83	GBMBC7_STATE_READ_ADDRESS = 2,
 84	GBMBC7_STATE_COMMAND_0 = 3,
 85	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 86	GBMBC7_STATE_COMMAND_SR_READ = 5,
 87	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 88	GBMBC7_STATE_READ = 7,
 89	GBMBC7_STATE_WRITE = 8,
 90};
 91
 92struct GBMBC7State {
 93	enum GBMBC7MachineState state;
 94	uint32_t sr;
 95	uint8_t address;
 96	bool writable;
 97	int srBits;
 98	int command;
 99	GBMBC7Field field;
100};
101
102union GBMBCState {
103	struct GBMBC7State mbc7;
104};
105
106struct mRotationSource;
107struct GBMemory {
108	uint8_t* rom;
109	uint8_t* romBank;
110	enum GBMemoryBankControllerType mbcType;
111	GBMemoryBankController mbc;
112	union GBMBCState mbcState;
113	int currentBank;
114
115	uint8_t* wram;
116	uint8_t* wramBank;
117	int wramCurrentBank;
118
119	bool sramAccess;
120	uint8_t* sram;
121	uint8_t* sramBank;
122	int sramCurrentBank;
123
124	uint8_t io[GB_SIZE_IO];
125	bool ime;
126	uint8_t ie;
127
128	uint8_t hram[GB_SIZE_HRAM];
129
130	int32_t dmaNext;
131	uint16_t dmaSource;
132	uint16_t dmaDest;
133	int dmaRemaining;
134
135	int32_t hdmaNext;
136	uint16_t hdmaSource;
137	uint16_t hdmaDest;
138	int hdmaRemaining;
139	bool isHdma;
140
141	size_t romSize;
142
143	bool rtcAccess;
144	int activeRtcReg;
145	int rtcLatched;
146	uint8_t rtcRegs[5];
147	struct mRTCSource* rtc;
148	struct mRotationSource* rotation;
149	struct mRumble* rumble;
150};
151
152void GBMemoryInit(struct GB* gb);
153void GBMemoryDeinit(struct GB* gb);
154
155void GBMemoryReset(struct GB* gb);
156void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
157
158uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
159void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
160
161int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
162void GBMemoryDMA(struct GB* gb, uint16_t base);
163void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
164
165uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
166void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
167
168uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
169uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
170
171void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
172void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
173
174#endif