src/gb/io.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/io.h>
7
8#include <mgba/internal/gb/gb.h>
9#include <mgba/internal/gb/sio.h>
10#include <mgba/internal/gb/serialize.h>
11
12mLOG_DEFINE_CATEGORY(GB_IO, "GB I/O", "gb.io");
13
14const char* const GBIORegisterNames[] = {
15 [REG_JOYP] = "JOYP",
16 [REG_SB] = "SB",
17 [REG_SC] = "SC",
18 [REG_DIV] = "DIV",
19 [REG_TIMA] = "TIMA",
20 [REG_TMA] = "TMA",
21 [REG_TAC] = "TAC",
22 [REG_IF] = "IF",
23 [REG_NR10] = "NR10",
24 [REG_NR11] = "NR11",
25 [REG_NR12] = "NR12",
26 [REG_NR13] = "NR13",
27 [REG_NR14] = "NR14",
28 [REG_NR21] = "NR21",
29 [REG_NR22] = "NR22",
30 [REG_NR23] = "NR23",
31 [REG_NR24] = "NR24",
32 [REG_NR30] = "NR30",
33 [REG_NR31] = "NR31",
34 [REG_NR32] = "NR32",
35 [REG_NR33] = "NR33",
36 [REG_NR34] = "NR34",
37 [REG_NR41] = "NR41",
38 [REG_NR42] = "NR42",
39 [REG_NR43] = "NR43",
40 [REG_NR44] = "NR44",
41 [REG_NR50] = "NR50",
42 [REG_NR51] = "NR51",
43 [REG_NR52] = "NR52",
44 [REG_LCDC] = "LCDC",
45 [REG_STAT] = "STAT",
46 [REG_SCY] = "SCY",
47 [REG_SCX] = "SCX",
48 [REG_LY] = "LY",
49 [REG_LYC] = "LYC",
50 [REG_DMA] = "DMA",
51 [REG_BGP] = "BGP",
52 [REG_OBP0] = "OBP0",
53 [REG_OBP1] = "OBP1",
54 [REG_WY] = "WY",
55 [REG_WX] = "WX",
56 [REG_KEY1] = "KEY1",
57 [REG_VBK] = "VBK",
58 [REG_HDMA1] = "HDMA1",
59 [REG_HDMA2] = "HDMA2",
60 [REG_HDMA3] = "HDMA3",
61 [REG_HDMA4] = "HDMA4",
62 [REG_HDMA5] = "HDMA5",
63 [REG_RP] = "RP",
64 [REG_BCPS] = "BCPS",
65 [REG_BCPD] = "BCPD",
66 [REG_OCPS] = "OCPS",
67 [REG_OCPD] = "OCPD",
68 [REG_SVBK] = "SVBK",
69 [REG_IE] = "IE",
70};
71
72static const uint8_t _registerMask[] = {
73 [REG_SC] = 0x7E, // TODO: GBC differences
74 [REG_IF] = 0xE0,
75 [REG_TAC] = 0xF8,
76 [REG_NR10] = 0x80,
77 [REG_NR11] = 0x3F,
78 [REG_NR12] = 0x00,
79 [REG_NR13] = 0xFF,
80 [REG_NR14] = 0xBF,
81 [REG_NR21] = 0x3F,
82 [REG_NR22] = 0x00,
83 [REG_NR23] = 0xFF,
84 [REG_NR24] = 0xBF,
85 [REG_NR30] = 0x7F,
86 [REG_NR31] = 0xFF,
87 [REG_NR32] = 0x9F,
88 [REG_NR33] = 0xFF,
89 [REG_NR34] = 0xBF,
90 [REG_NR41] = 0xFF,
91 [REG_NR42] = 0x00,
92 [REG_NR43] = 0x00,
93 [REG_NR44] = 0xBF,
94 [REG_NR50] = 0x00,
95 [REG_NR51] = 0x00,
96 [REG_NR52] = 0x70,
97 [REG_STAT] = 0x80,
98 [REG_KEY1] = 0x7E,
99 [REG_VBK] = 0xFE,
100 [REG_OCPS] = 0x40,
101 [REG_BCPS] = 0x40,
102 [REG_UNK6C] = 0xFE,
103 [REG_SVBK] = 0xF8,
104 [REG_UNK75] = 0x8F,
105 [REG_IE] = 0xE0,
106};
107
108void GBIOInit(struct GB* gb) {
109 memset(gb->memory.io, 0, sizeof(gb->memory.io));
110}
111
112void GBIOReset(struct GB* gb) {
113 memset(gb->memory.io, 0, sizeof(gb->memory.io));
114
115 GBIOWrite(gb, REG_TIMA, 0);
116 GBIOWrite(gb, REG_TMA, 0);
117 GBIOWrite(gb, REG_TAC, 0);
118 GBIOWrite(gb, REG_IF, 1);
119 GBIOWrite(gb, REG_NR52, 0xF1);
120 GBIOWrite(gb, REG_NR14, 0xBF);
121 GBIOWrite(gb, REG_NR10, 0x80);
122 GBIOWrite(gb, REG_NR11, 0xBF);
123 GBIOWrite(gb, REG_NR12, 0xF3);
124 GBIOWrite(gb, REG_NR13, 0xF3);
125 GBIOWrite(gb, REG_NR24, 0xBF);
126 GBIOWrite(gb, REG_NR21, 0x3F);
127 GBIOWrite(gb, REG_NR22, 0x00);
128 GBIOWrite(gb, REG_NR34, 0xBF);
129 GBIOWrite(gb, REG_NR30, 0x7F);
130 GBIOWrite(gb, REG_NR31, 0xFF);
131 GBIOWrite(gb, REG_NR32, 0x9F);
132 GBIOWrite(gb, REG_NR44, 0xBF);
133 GBIOWrite(gb, REG_NR41, 0xFF);
134 GBIOWrite(gb, REG_NR42, 0x00);
135 GBIOWrite(gb, REG_NR43, 0x00);
136 GBIOWrite(gb, REG_NR50, 0x77);
137 GBIOWrite(gb, REG_NR51, 0xF3);
138 GBIOWrite(gb, REG_LCDC, 0x91);
139 GBIOWrite(gb, REG_SCY, 0x00);
140 GBIOWrite(gb, REG_SCX, 0x00);
141 GBIOWrite(gb, REG_LYC, 0x00);
142 GBIOWrite(gb, REG_BGP, 0xFC);
143 GBIOWrite(gb, REG_OBP0, 0xFF);
144 GBIOWrite(gb, REG_OBP1, 0xFF);
145 GBIOWrite(gb, REG_WY, 0x00);
146 GBIOWrite(gb, REG_WX, 0x00);
147 if (gb->model >= GB_MODEL_CGB) {
148 GBIOWrite(gb, REG_VBK, 0);
149 GBIOWrite(gb, REG_BCPS, 0);
150 GBIOWrite(gb, REG_OCPS, 0);
151 GBIOWrite(gb, REG_SVBK, 1);
152 GBIOWrite(gb, REG_HDMA1, 0xFF);
153 GBIOWrite(gb, REG_HDMA2, 0xFF);
154 GBIOWrite(gb, REG_HDMA3, 0xFF);
155 GBIOWrite(gb, REG_HDMA4, 0xFF);
156 gb->memory.io[REG_HDMA5] = 0xFF;
157 }
158 GBIOWrite(gb, REG_IE, 0x00);
159}
160
161void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
162 switch (address) {
163 case REG_SB:
164 GBSIOWriteSB(&gb->sio, value);
165 break;
166 case REG_SC:
167 GBSIOWriteSC(&gb->sio, value);
168 break;
169 case REG_DIV:
170 GBTimerDivReset(&gb->timer);
171 return;
172 case REG_NR10:
173 if (gb->audio.enable) {
174 GBAudioWriteNR10(&gb->audio, value);
175 } else {
176 value = 0;
177 }
178 break;
179 case REG_NR11:
180 if (gb->audio.enable) {
181 GBAudioWriteNR11(&gb->audio, value);
182 } else {
183 if (gb->audio.style == GB_AUDIO_DMG) {
184 GBAudioWriteNR11(&gb->audio, value & _registerMask[REG_NR11]);
185 }
186 value = 0;
187 }
188 break;
189 case REG_NR12:
190 if (gb->audio.enable) {
191 GBAudioWriteNR12(&gb->audio, value);
192 } else {
193 value = 0;
194 }
195 break;
196 case REG_NR13:
197 if (gb->audio.enable) {
198 GBAudioWriteNR13(&gb->audio, value);
199 } else {
200 value = 0;
201 }
202 break;
203 case REG_NR14:
204 if (gb->audio.enable) {
205 GBAudioWriteNR14(&gb->audio, value);
206 } else {
207 value = 0;
208 }
209 break;
210 case REG_NR21:
211 if (gb->audio.enable) {
212 GBAudioWriteNR21(&gb->audio, value);
213 } else {
214 if (gb->audio.style == GB_AUDIO_DMG) {
215 GBAudioWriteNR21(&gb->audio, value & _registerMask[REG_NR21]);
216 }
217 value = 0;
218 }
219 break;
220 case REG_NR22:
221 if (gb->audio.enable) {
222 GBAudioWriteNR22(&gb->audio, value);
223 } else {
224 value = 0;
225 }
226 break;
227 case REG_NR23:
228 if (gb->audio.enable) {
229 GBAudioWriteNR23(&gb->audio, value);
230 } else {
231 value = 0;
232 }
233 break;
234 case REG_NR24:
235 if (gb->audio.enable) {
236 GBAudioWriteNR24(&gb->audio, value);
237 } else {
238 value = 0;
239 }
240 break;
241 case REG_NR30:
242 if (gb->audio.enable) {
243 GBAudioWriteNR30(&gb->audio, value);
244 } else {
245 value = 0;
246 }
247 break;
248 case REG_NR31:
249 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
250 GBAudioWriteNR31(&gb->audio, value);
251 } else {
252 value = 0;
253 }
254 break;
255 case REG_NR32:
256 if (gb->audio.enable) {
257 GBAudioWriteNR32(&gb->audio, value);
258 } else {
259 value = 0;
260 }
261 break;
262 case REG_NR33:
263 if (gb->audio.enable) {
264 GBAudioWriteNR33(&gb->audio, value);
265 } else {
266 value = 0;
267 }
268 break;
269 case REG_NR34:
270 if (gb->audio.enable) {
271 GBAudioWriteNR34(&gb->audio, value);
272 } else {
273 value = 0;
274 }
275 break;
276 case REG_NR41:
277 if (gb->audio.enable || gb->audio.style == GB_AUDIO_DMG) {
278 GBAudioWriteNR41(&gb->audio, value);
279 } else {
280 value = 0;
281 }
282 break;
283 case REG_NR42:
284 if (gb->audio.enable) {
285 GBAudioWriteNR42(&gb->audio, value);
286 } else {
287 value = 0;
288 }
289 break;
290 case REG_NR43:
291 if (gb->audio.enable) {
292 GBAudioWriteNR43(&gb->audio, value);
293 } else {
294 value = 0;
295 }
296 break;
297 case REG_NR44:
298 if (gb->audio.enable) {
299 GBAudioWriteNR44(&gb->audio, value);
300 } else {
301 value = 0;
302 }
303 break;
304 case REG_NR50:
305 if (gb->audio.enable) {
306 GBAudioWriteNR50(&gb->audio, value);
307 } else {
308 value = 0;
309 }
310 break;
311 case REG_NR51:
312 if (gb->audio.enable) {
313 GBAudioWriteNR51(&gb->audio, value);
314 } else {
315 value = 0;
316 }
317 break;
318 case REG_NR52:
319 GBAudioWriteNR52(&gb->audio, value);
320 value &= 0x80;
321 value |= gb->memory.io[REG_NR52] & 0x0F;
322 break;
323 case REG_WAVE_0:
324 case REG_WAVE_1:
325 case REG_WAVE_2:
326 case REG_WAVE_3:
327 case REG_WAVE_4:
328 case REG_WAVE_5:
329 case REG_WAVE_6:
330 case REG_WAVE_7:
331 case REG_WAVE_8:
332 case REG_WAVE_9:
333 case REG_WAVE_A:
334 case REG_WAVE_B:
335 case REG_WAVE_C:
336 case REG_WAVE_D:
337 case REG_WAVE_E:
338 case REG_WAVE_F:
339 if (!gb->audio.playingCh3 || gb->audio.style != GB_AUDIO_DMG) {
340 gb->audio.ch3.wavedata8[address - REG_WAVE_0] = value;
341 } else if(gb->audio.ch3.readable) {
342 gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1] = value;
343 }
344 break;
345 case REG_JOYP:
346 case REG_TIMA:
347 case REG_TMA:
348 // Handled transparently by the registers
349 break;
350 case REG_TAC:
351 value = GBTimerUpdateTAC(&gb->timer, value);
352 break;
353 case REG_IF:
354 gb->memory.io[REG_IF] = value | 0xE0;
355 GBUpdateIRQs(gb);
356 return;
357 case REG_LCDC:
358 // TODO: handle GBC differences
359 GBVideoProcessDots(&gb->video);
360 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
361 GBVideoWriteLCDC(&gb->video, value);
362 break;
363 case REG_LYC:
364 GBVideoWriteLYC(&gb->video, value);
365 break;
366 case REG_DMA:
367 GBMemoryDMA(gb, value << 8);
368 break;
369 case REG_SCY:
370 case REG_SCX:
371 case REG_WY:
372 case REG_WX:
373 GBVideoProcessDots(&gb->video);
374 value = gb->video.renderer->writeVideoRegister(gb->video.renderer, address, value);
375 break;
376 case REG_BGP:
377 case REG_OBP0:
378 case REG_OBP1:
379 GBVideoProcessDots(&gb->video);
380 GBVideoWritePalette(&gb->video, address, value);
381 break;
382 case REG_STAT:
383 GBVideoWriteSTAT(&gb->video, value);
384 value = gb->video.stat;
385 break;
386 case 0x50:
387 if (gb->memory.romBase < gb->memory.rom || gb->memory.romBase > &gb->memory.rom[gb->memory.romSize - 1]) {
388 free(gb->memory.romBase);
389 gb->memory.romBase = gb->memory.rom;
390 }
391 break;
392 case REG_IE:
393 gb->memory.ie = value;
394 GBUpdateIRQs(gb);
395 return;
396 default:
397 if (gb->model >= GB_MODEL_CGB) {
398 switch (address) {
399 case REG_KEY1:
400 value &= 0x1;
401 value |= gb->memory.io[address] & 0x80;
402 break;
403 case REG_VBK:
404 GBVideoSwitchBank(&gb->video, value);
405 break;
406 case REG_HDMA1:
407 case REG_HDMA2:
408 case REG_HDMA3:
409 case REG_HDMA4:
410 // Handled transparently by the registers
411 break;
412 case REG_HDMA5:
413 value = GBMemoryWriteHDMA5(gb, value);
414 break;
415 case REG_BCPS:
416 gb->video.bcpIndex = value & 0x3F;
417 gb->video.bcpIncrement = value & 0x80;
418 gb->memory.io[REG_BCPD] = gb->video.palette[gb->video.bcpIndex >> 1] >> (8 * (gb->video.bcpIndex & 1));
419 break;
420 case REG_BCPD:
421 GBVideoProcessDots(&gb->video);
422 GBVideoWritePalette(&gb->video, address, value);
423 return;
424 case REG_OCPS:
425 gb->video.ocpIndex = value & 0x3F;
426 gb->video.ocpIncrement = value & 0x80;
427 gb->memory.io[REG_OCPD] = gb->video.palette[8 * 4 + (gb->video.ocpIndex >> 1)] >> (8 * (gb->video.ocpIndex & 1));
428 break;
429 case REG_OCPD:
430 GBVideoProcessDots(&gb->video);
431 GBVideoWritePalette(&gb->video, address, value);
432 return;
433 case REG_SVBK:
434 GBMemorySwitchWramBank(&gb->memory, value);
435 value = gb->memory.wramCurrentBank;
436 break;
437 default:
438 goto failed;
439 }
440 goto success;
441 }
442 failed:
443 mLOG(GB_IO, STUB, "Writing to unknown register FF%02X:%02X", address, value);
444 if (address >= GB_SIZE_IO) {
445 return;
446 }
447 break;
448 }
449 success:
450 gb->memory.io[address] = value;
451}
452
453static uint8_t _readKeys(struct GB* gb) {
454 uint8_t keys = *gb->keySource;
455 switch (gb->memory.io[REG_JOYP] & 0x30) {
456 case 0x30:
457 keys = 0;
458 break;
459 case 0x20:
460 keys >>= 4;
461 break;
462 case 0x10:
463 break;
464 case 0x00:
465 keys |= keys >> 4;
466 break;
467 }
468 return (0xC0 | (gb->memory.io[REG_JOYP] | 0xF)) ^ (keys & 0xF);
469}
470
471uint8_t GBIORead(struct GB* gb, unsigned address) {
472 switch (address) {
473 case REG_JOYP:
474 return _readKeys(gb);
475 case REG_IE:
476 return gb->memory.ie;
477 case REG_WAVE_0:
478 case REG_WAVE_1:
479 case REG_WAVE_2:
480 case REG_WAVE_3:
481 case REG_WAVE_4:
482 case REG_WAVE_5:
483 case REG_WAVE_6:
484 case REG_WAVE_7:
485 case REG_WAVE_8:
486 case REG_WAVE_9:
487 case REG_WAVE_A:
488 case REG_WAVE_B:
489 case REG_WAVE_C:
490 case REG_WAVE_D:
491 case REG_WAVE_E:
492 case REG_WAVE_F:
493 if (gb->audio.playingCh3) {
494 if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
495 return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
496 } else {
497 return 0xFF;
498 }
499 } else {
500 return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
501 }
502 break;
503 case REG_SB:
504 case REG_SC:
505 case REG_IF:
506 case REG_NR10:
507 case REG_NR11:
508 case REG_NR12:
509 case REG_NR14:
510 case REG_NR21:
511 case REG_NR22:
512 case REG_NR24:
513 case REG_NR30:
514 case REG_NR32:
515 case REG_NR34:
516 case REG_NR41:
517 case REG_NR42:
518 case REG_NR43:
519 case REG_NR44:
520 case REG_NR50:
521 case REG_NR51:
522 case REG_NR52:
523 case REG_DIV:
524 case REG_TIMA:
525 case REG_TMA:
526 case REG_TAC:
527 case REG_STAT:
528 case REG_LCDC:
529 case REG_SCY:
530 case REG_SCX:
531 case REG_LY:
532 case REG_LYC:
533 case REG_BGP:
534 case REG_OBP0:
535 case REG_OBP1:
536 case REG_WY:
537 case REG_WX:
538 // Handled transparently by the registers
539 break;
540 default:
541 if (gb->model >= GB_MODEL_CGB) {
542 switch (address) {
543 case REG_KEY1:
544 case REG_VBK:
545 case REG_HDMA1:
546 case REG_HDMA2:
547 case REG_HDMA3:
548 case REG_HDMA4:
549 case REG_HDMA5:
550 case REG_BCPS:
551 case REG_BCPD:
552 case REG_OCPS:
553 case REG_OCPD:
554 case REG_SVBK:
555 // Handled transparently by the registers
556 goto success;
557 default:
558 break;
559 }
560 }
561 mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
562 return 0xFF;
563 }
564 success:
565 return gb->memory.io[address] | _registerMask[address];
566}
567
568void GBTestKeypadIRQ(struct GB* gb) {
569 if (_readKeys(gb)) {
570 gb->memory.io[REG_IF] |= (1 << GB_IRQ_KEYPAD);
571 GBUpdateIRQs(gb);
572 }
573}
574
575struct GBSerializedState;
576void GBIOSerialize(const struct GB* gb, struct GBSerializedState* state) {
577 memcpy(state->io, gb->memory.io, GB_SIZE_IO);
578 state->ie = gb->memory.ie;
579}
580
581void GBIODeserialize(struct GB* gb, const struct GBSerializedState* state) {
582 memcpy(gb->memory.io, state->io, GB_SIZE_IO);
583 gb->memory.ie = state->ie;
584 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_LCDC, state->io[REG_LCDC]);
585 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCY, state->io[REG_SCY]);
586 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_SCX, state->io[REG_SCX]);
587 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WY, state->io[REG_WY]);
588 gb->video.renderer->writeVideoRegister(gb->video.renderer, REG_WX, state->io[REG_WX]);
589 gb->video.stat = state->io[REG_STAT];
590}