all repos — mgba @ 9295c3c893646713d8fce7f9d15be320787b9d97

mGBA Game Boy Advance Emulator

src/arm/isa-thumb.c (view raw)

  1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#include <mgba/internal/arm/isa-thumb.h>
  7
  8#include <mgba/internal/arm/isa-inlines.h>
  9#include <mgba/internal/arm/emitter-thumb.h>
 10
 11// Instruction definitions
 12// Beware pre-processor insanity
 13
 14#define THUMB_ADDITION_S(M, N, D) \
 15	cpu->cpsr.flags = 0; \
 16	cpu->cpsr.n = ARM_SIGN(D); \
 17	cpu->cpsr.z = !(D); \
 18	cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
 19	cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
 20
 21#define THUMB_SUBTRACTION_S(M, N, D) \
 22	cpu->cpsr.flags = 0; \
 23	cpu->cpsr.n = ARM_SIGN(D); \
 24	cpu->cpsr.z = !(D); \
 25	cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
 26	cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
 27
 28#define THUMB_NEUTRAL_S(M, N, D) \
 29	cpu->cpsr.n = ARM_SIGN(D); \
 30	cpu->cpsr.z = !(D);
 31
 32#define THUMB_ADDITION(D, M, N) \
 33	int n = N; \
 34	int m = M; \
 35	D = M + N; \
 36	THUMB_ADDITION_S(m, n, D)
 37
 38#define THUMB_SUBTRACTION(D, M, N) \
 39	int n = N; \
 40	int m = M; \
 41	D = M - N; \
 42	THUMB_SUBTRACTION_S(m, n, D)
 43
 44#define THUMB_PREFETCH_CYCLES (1 + cpu->memory.activeSeqCycles16)
 45
 46#define THUMB_LOAD_POST_BODY \
 47	currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
 48
 49#define THUMB_STORE_POST_BODY \
 50	currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16;
 51
 52#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
 53	static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) {  \
 54		int currentCycles = THUMB_PREFETCH_CYCLES; \
 55		BODY; \
 56		cpu->cycles += currentCycles; \
 57	}
 58
 59#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
 60	DEFINE_INSTRUCTION_THUMB(NAME, \
 61		int immediate = (opcode >> 6) & 0x001F; \
 62		int rd = opcode & 0x0007; \
 63		int rm = (opcode >> 3) & 0x0007; \
 64		BODY;)
 65
 66DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
 67	if (!immediate) {
 68		cpu->gprs[rd] = cpu->gprs[rm];
 69	} else {
 70		cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
 71		cpu->gprs[rd] = cpu->gprs[rm] << immediate;
 72	}
 73	THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
 74
 75DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
 76	if (!immediate) {
 77		cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
 78		cpu->gprs[rd] = 0;
 79	} else {
 80		cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
 81		cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
 82	}
 83	THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
 84
 85DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, 
 86	if (!immediate) {
 87		cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
 88		if (cpu->cpsr.c) {
 89			cpu->gprs[rd] = 0xFFFFFFFF;
 90		} else {
 91			cpu->gprs[rd] = 0;
 92		}
 93	} else {
 94		cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
 95		cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
 96	}
 97	THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
 98
 99DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rm] + immediate * 4, &currentCycles); THUMB_LOAD_POST_BODY;)
100DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rm] + immediate, &currentCycles); THUMB_LOAD_POST_BODY;)
101DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rm] + immediate * 2, &currentCycles); THUMB_LOAD_POST_BODY;)
102DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
103DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
105
106#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
107	DEFINE_INSTRUCTION_THUMB(NAME, \
108		int rm = (opcode >> 6) & 0x0007; \
109		int rd = opcode & 0x0007; \
110		int rn = (opcode >> 3) & 0x0007; \
111		BODY;)
112
113DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
114DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
115
116#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
117	DEFINE_INSTRUCTION_THUMB(NAME, \
118		int immediate = (opcode >> 6) & 0x0007; \
119		int rd = opcode & 0x0007; \
120		int rn = (opcode >> 3) & 0x0007; \
121		BODY;)
122
123DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
124DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
125
126#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
127	DEFINE_INSTRUCTION_THUMB(NAME, \
128		int rd = (opcode >> 8) & 0x0007; \
129		int immediate = opcode & 0x00FF; \
130		BODY;)
131
132DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
133DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
134DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
135DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
136
137#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
138	DEFINE_INSTRUCTION_THUMB(NAME, \
139		int rd = opcode & 0x0007; \
140		int rn = (opcode >> 3) & 0x0007; \
141		BODY;)
142
143DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
144DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
145DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
146	int rs = cpu->gprs[rn] & 0xFF;
147	if (rs) {
148		if (rs < 32) {
149			cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
150			cpu->gprs[rd] <<= rs;
151		} else {
152			if (rs > 32) {
153				cpu->cpsr.c = 0;
154			} else {
155				cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
156			}
157			cpu->gprs[rd] = 0;
158		}
159	}
160	++currentCycles;
161	THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
162
163DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
164	int rs = cpu->gprs[rn] & 0xFF;
165	if (rs) {
166		if (rs < 32) {
167			cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
168			cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
169		} else {
170			if (rs > 32) {
171				cpu->cpsr.c = 0;
172			} else {
173				cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
174			}
175			cpu->gprs[rd] = 0;
176		}
177	}
178	++currentCycles;
179	THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
180
181DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
182	int rs = cpu->gprs[rn] & 0xFF;
183	if (rs) {
184		if (rs < 32) {
185			cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
186			cpu->gprs[rd] >>= rs;
187		} else {
188			cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
189			if (cpu->cpsr.c) {
190				cpu->gprs[rd] = 0xFFFFFFFF;
191			} else {
192				cpu->gprs[rd] = 0;
193			}
194		}
195	}
196	++currentCycles;
197	THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
198
199DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
200	int n = cpu->gprs[rn];
201	int d = cpu->gprs[rd];
202	cpu->gprs[rd] = d + n + cpu->cpsr.c;
203	THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
204
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
206	int n = cpu->gprs[rn] + !cpu->cpsr.c;
207	int d = cpu->gprs[rd];
208	cpu->gprs[rd] = d - n;
209	THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
210DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
211	int rs = cpu->gprs[rn] & 0xFF;
212	if (rs) {
213		int r4 = rs & 0x1F;
214		if (r4 > 0) {
215			cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
216			cpu->gprs[rd] = ROR(cpu->gprs[rd], r4);
217		} else {
218			cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
219		}
220	}
221	++currentCycles;
222	THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
223DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
224DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
225DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
226DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
227DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
228DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
229DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
230DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
231
232#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
233	DEFINE_INSTRUCTION_THUMB(NAME, \
234		int rd = (opcode & 0x0007) | H1; \
235		int rm = ((opcode >> 3) & 0x0007) | H2; \
236		BODY;)
237
238#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
239	DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
240	DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
241	DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
242	DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
243
244DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
245	cpu->gprs[rd] += cpu->gprs[rm];
246	if (rd == ARM_PC) {
247		currentCycles += ThumbWritePC(cpu);
248	})
249
250DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
251DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
252	cpu->gprs[rd] = cpu->gprs[rm];
253	if (rd == ARM_PC) {
254		currentCycles += ThumbWritePC(cpu);
255	})
256
257#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
258	DEFINE_INSTRUCTION_THUMB(NAME, \
259		int rd = (opcode >> 8) & 0x0007; \
260		int immediate = (opcode & 0x00FF) << 2; \
261		BODY;)
262
263DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, &currentCycles); THUMB_LOAD_POST_BODY;)
264DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, &currentCycles); THUMB_LOAD_POST_BODY;)
265DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
266
267DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
268DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
269
270#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
271	DEFINE_INSTRUCTION_THUMB(NAME, \
272		int rm = (opcode >> 6) & 0x0007; \
273		int rd = opcode & 0x0007; \
274		int rn = (opcode >> 3) & 0x0007; \
275		BODY;)
276
277DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles); THUMB_LOAD_POST_BODY;)
278DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles); THUMB_LOAD_POST_BODY;)
279DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles); THUMB_LOAD_POST_BODY;)
280DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], &currentCycles)); THUMB_LOAD_POST_BODY;)
281DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, rm = cpu->gprs[rn] + cpu->gprs[rm]; cpu->gprs[rd] = rm & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, rm, &currentCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, rm, &currentCycles)); THUMB_LOAD_POST_BODY;)
282DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
283DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
284DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], &currentCycles); THUMB_STORE_POST_BODY;)
285
286#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
287	DEFINE_INSTRUCTION_THUMB(NAME, \
288		int rn = RN; \
289		UNUSED(rn); \
290		int rs = opcode & 0xFF; \
291		int32_t address = cpu->gprs[RN]; \
292		PRE_BODY; \
293		address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, &currentCycles); \
294		WRITEBACK;)
295
296DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
297	(opcode >> 8) & 0x0007,
298	load,
299	IA,
300	,
301	THUMB_LOAD_POST_BODY;
302	if (!rs) {
303		currentCycles += ThumbWritePC(cpu);
304	}
305	if (!((1 << rn) & rs)) {
306		cpu->gprs[rn] = address;
307	})
308
309DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
310	(opcode >> 8) & 0x0007,
311	store,
312	IA,
313	,
314	THUMB_STORE_POST_BODY;
315	cpu->gprs[rn] = address;)
316
317#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
318	DEFINE_INSTRUCTION_THUMB(B ## COND, \
319		if (ARM_COND_ ## COND) { \
320			int8_t immediate = opcode; \
321			cpu->gprs[ARM_PC] += (int32_t) immediate << 1; \
322			currentCycles += ThumbWritePC(cpu); \
323		})
324
325DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
326DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
327DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
328DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
329DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
330DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
331DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
332DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
333DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
334DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
335DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
336DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
337DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
338DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
339
340DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
341DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
342
343DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
344	ARM_SP,
345	load,
346	IA,
347	,
348	THUMB_LOAD_POST_BODY;
349	cpu->gprs[ARM_SP] = address)
350
351DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
352	ARM_SP,
353	load,
354	IA,
355	rs |= 1 << ARM_PC,
356	THUMB_LOAD_POST_BODY;
357	cpu->gprs[ARM_SP] = address;
358	currentCycles += ThumbWritePC(cpu);)
359
360DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
361	ARM_SP,
362	store,
363	DB,
364	,
365	THUMB_STORE_POST_BODY;
366	cpu->gprs[ARM_SP] = address)
367
368DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
369	ARM_SP,
370	store,
371	DB,
372	rs |= 1 << ARM_LR,
373	THUMB_STORE_POST_BODY;
374	cpu->gprs[ARM_SP] = address)
375
376DEFINE_INSTRUCTION_THUMB(ILL, ARM_ILL)
377DEFINE_INSTRUCTION_THUMB(BKPT, cpu->irqh.bkpt16(cpu, opcode & 0xFF);)
378DEFINE_INSTRUCTION_THUMB(B,
379	int16_t immediate = (opcode & 0x07FF) << 5;
380	cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
381	currentCycles += ThumbWritePC(cpu);)
382
383DEFINE_INSTRUCTION_THUMB(BL1,
384	int16_t immediate = (opcode & 0x07FF) << 5;
385	cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
386
387DEFINE_INSTRUCTION_THUMB(BL2,
388	uint16_t immediate = (opcode & 0x07FF) << 1;
389	uint32_t pc = cpu->gprs[ARM_PC];
390	cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
391	cpu->gprs[ARM_LR] = pc - 1;
392	currentCycles += ThumbWritePC(cpu);)
393
394DEFINE_INSTRUCTION_THUMB(BX,
395	int rm = (opcode >> 3) & 0xF;
396	_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
397	int misalign = 0;
398	if (rm == ARM_PC) {
399		misalign = cpu->gprs[rm] & 0x00000002;
400	}
401	cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
402	if (cpu->executionMode == MODE_THUMB) {
403		currentCycles += ThumbWritePC(cpu);
404	} else {
405		currentCycles += ARMWritePC(cpu);
406	})
407
408DEFINE_INSTRUCTION_THUMB(SWI, cpu->irqh.swi16(cpu, opcode & 0xFF))
409
410const ThumbInstruction _thumbTable[0x400] = {
411	DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
412};