1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_IO_H
  7#define GB_IO_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13mLOG_DECLARE_CATEGORY(GB_IO);
 14
 15enum GBIORegisters {
 16	REG_JOYP = 0x00,
 17	REG_SB = 0x01,
 18	REG_SC = 0x02,
 19
 20	// Timing
 21	REG_DIV = 0x04,
 22	REG_TIMA = 0x05,
 23	REG_TMA = 0x06,
 24	REG_TAC = 0x07,
 25
 26	// Interrupts
 27	REG_IF = 0x0F,
 28	REG_IE = 0xFF,
 29
 30	// Audio
 31	REG_NR10 = 0x10,
 32	REG_NR11 = 0x11,
 33	REG_NR12 = 0x12,
 34	REG_NR13 = 0x13,
 35	REG_NR14 = 0x14,
 36	REG_NR21 = 0x16,
 37	REG_NR22 = 0x17,
 38	REG_NR23 = 0x18,
 39	REG_NR24 = 0x19,
 40	REG_NR30 = 0x1A,
 41	REG_NR31 = 0x1B,
 42	REG_NR32 = 0x1C,
 43	REG_NR33 = 0x1D,
 44	REG_NR34 = 0x1E,
 45	REG_NR41 = 0x20,
 46	REG_NR42 = 0x21,
 47	REG_NR43 = 0x22,
 48	REG_NR44 = 0x23,
 49	REG_NR50 = 0x24,
 50	REG_NR51 = 0x25,
 51	REG_NR52 = 0x26,
 52
 53	REG_WAVE_0 = 0x30,
 54	REG_WAVE_1 = 0x31,
 55	REG_WAVE_2 = 0x32,
 56	REG_WAVE_3 = 0x33,
 57	REG_WAVE_4 = 0x34,
 58	REG_WAVE_5 = 0x35,
 59	REG_WAVE_6 = 0x36,
 60	REG_WAVE_7 = 0x37,
 61	REG_WAVE_8 = 0x38,
 62	REG_WAVE_9 = 0x39,
 63	REG_WAVE_A = 0x3A,
 64	REG_WAVE_B = 0x3B,
 65	REG_WAVE_C = 0x3C,
 66	REG_WAVE_D = 0x3D,
 67	REG_WAVE_E = 0x3E,
 68	REG_WAVE_F = 0x3F,
 69
 70	// Video
 71	REG_LCDC = 0x40,
 72	REG_STAT = 0x41,
 73	REG_SCY = 0x42,
 74	REG_SCX = 0x43,
 75	REG_LY = 0x44,
 76	REG_LYC = 0x45,
 77	REG_DMA = 0x46,
 78	REG_BGP = 0x47,
 79	REG_OBP0 = 0x48,
 80	REG_OBP1 = 0x49,
 81	REG_WY = 0x4A,
 82	REG_WX = 0x4B,
 83
 84	// CGB
 85	REG_KEY1 = 0x4D,
 86	REG_VBK = 0x4F,
 87	REG_HDMA1 = 0x51,
 88	REG_HDMA2 = 0x52,
 89	REG_HDMA3 = 0x53,
 90	REG_HDMA4 = 0x54,
 91	REG_HDMA5 = 0x55,
 92	REG_RP = 0x56,
 93	REG_BCPS = 0x68,
 94	REG_BCPD = 0x69,
 95	REG_OCPS = 0x6A,
 96	REG_OCPD = 0x6B,
 97	REG_UNK6C = 0x6C,
 98	REG_SVBK = 0x70,
 99	REG_UNK72 = 0x72,
100	REG_UNK73 = 0x73,
101	REG_UNK74 = 0x74,
102	REG_UNK75 = 0x75,
103	REG_UNK76 = 0x76,
104	REG_UNK77 = 0x77
105};
106
107struct GB;
108void GBIOInit(struct GB* gb);
109void GBIOReset(struct GB* gb);
110
111void GBIOWrite(struct GB* gb, unsigned address, uint8_t value);
112uint8_t GBIORead(struct GB* gb, unsigned address);
113
114#endif