1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_CART_MAX = 0x800000,
 48	GB_SIZE_VRAM = 0x4000,
 49	GB_SIZE_VRAM_BANK0 = 0x2000,
 50	GB_SIZE_EXTERNAL_RAM = 0x2000,
 51	GB_SIZE_WORKING_RAM = 0x8000,
 52	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 53	GB_SIZE_OAM = 0xA0,
 54	GB_SIZE_IO = 0x80,
 55	GB_SIZE_HRAM = 0x7F,
 56};
 57
 58enum GBMemoryBankControllerType {
 59	GB_MBC_NONE = 0,
 60	GB_MBC1 = 1,
 61	GB_MBC2 = 2,
 62	GB_MBC3 = 3,
 63	GB_MBC5 = 5,
 64	GB_MBC6 = 6,
 65	GB_MBC7 = 7,
 66	GB_MMM01 = 0x10,
 67	GB_HuC1 = 0x11,
 68	GB_HuC3 = 0x12,
 69	GB_MBC5_RUMBLE = 0x105
 70};
 71
 72struct GBMemory;
 73typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 74
 75DECL_BITFIELD(GBMBC7Field, uint8_t);
 76DECL_BIT(GBMBC7Field, SK, 6);
 77DECL_BIT(GBMBC7Field, CS, 7);
 78DECL_BIT(GBMBC7Field, IO, 1);
 79
 80enum GBMBC7MachineState {
 81	GBMBC7_STATE_NULL = -1,
 82	GBMBC7_STATE_IDLE = 0,
 83	GBMBC7_STATE_READ_COMMAND = 1,
 84	GBMBC7_STATE_READ_ADDRESS = 2,
 85	GBMBC7_STATE_COMMAND_0 = 3,
 86	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 87	GBMBC7_STATE_COMMAND_SR_READ = 5,
 88	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 89	GBMBC7_STATE_READ = 7,
 90	GBMBC7_STATE_WRITE = 8,
 91};
 92
 93struct GBMBC1State {
 94	int mode;
 95};
 96
 97struct GBMBC7State {
 98	enum GBMBC7MachineState state;
 99	uint32_t sr;
100	uint8_t address;
101	bool writable;
102	int srBits;
103	int command;
104	GBMBC7Field field;
105};
106
107union GBMBCState {
108	struct GBMBC1State mbc1;
109	struct GBMBC7State mbc7;
110};
111
112struct mRotationSource;
113struct GBMemory {
114	uint8_t* rom;
115	uint8_t* romBank;
116	enum GBMemoryBankControllerType mbcType;
117	GBMemoryBankController mbc;
118	union GBMBCState mbcState;
119	int currentBank;
120
121	uint8_t* wram;
122	uint8_t* wramBank;
123	int wramCurrentBank;
124
125	bool sramAccess;
126	uint8_t* sram;
127	uint8_t* sramBank;
128	int sramCurrentBank;
129
130	uint8_t io[GB_SIZE_IO];
131	bool ime;
132	uint8_t ie;
133
134	uint8_t hram[GB_SIZE_HRAM];
135
136	int32_t dmaNext;
137	uint16_t dmaSource;
138	uint16_t dmaDest;
139	int dmaRemaining;
140
141	int32_t hdmaNext;
142	uint16_t hdmaSource;
143	uint16_t hdmaDest;
144	int hdmaRemaining;
145	bool isHdma;
146
147	size_t romSize;
148
149	bool rtcAccess;
150	int activeRtcReg;
151	int rtcLatched;
152	uint8_t rtcRegs[5];
153	struct mRTCSource* rtc;
154	struct mRotationSource* rotation;
155	struct mRumble* rumble;
156};
157
158void GBMemoryInit(struct GB* gb);
159void GBMemoryDeinit(struct GB* gb);
160
161void GBMemoryReset(struct GB* gb);
162void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
163
164uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
165void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
166
167int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
168void GBMemoryDMA(struct GB* gb, uint16_t base);
169void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
170
171uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
172void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
173
174uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
175uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
176
177void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
178void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
179
180#endif