src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 cpu->currentPC = cpu->gprs[ARM_PC] - WORD_SIZE_THUMB;
9 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
10 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(cpu->currentPC & cpu->memory->activeMask) >> 1];
11 ThumbInstruction instruction = _thumbTable[opcode >> 6];
12 instruction(cpu, opcode);
13}
14
15// Instruction definitions
16// Beware pre-processor insanity
17
18#define THUMB_ADDITION_S(M, N, D) \
19 cpu->cpsr.n = ARM_SIGN(D); \
20 cpu->cpsr.z = !(D); \
21 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
22 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
23
24#define THUMB_SUBTRACTION_S(M, N, D) \
25 cpu->cpsr.n = ARM_SIGN(D); \
26 cpu->cpsr.z = !(D); \
27 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
28 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
29
30#define THUMB_NEUTRAL_S(M, N, D) \
31 cpu->cpsr.n = ARM_SIGN(D); \
32 cpu->cpsr.z = !(D);
33
34#define THUMB_ADDITION(D, M, N) \
35 int n = N; \
36 int m = M; \
37 D = M + N; \
38 THUMB_ADDITION_S(m, n, D)
39
40#define THUMB_SUBTRACTION(D, M, N) \
41 int n = N; \
42 int m = M; \
43 D = M - N; \
44 THUMB_SUBTRACTION_S(m, n, D)
45
46#define THUMB_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles16)
47
48#define THUMB_STORE_POST_BODY \
49 currentCycles += cpu->memory->activeNonseqCycles16 - cpu->memory->activePrefetchCycles16;
50
51#define APPLY(F, ...) F(__VA_ARGS__)
52
53#define COUNT_1(EMITTER, PREFIX, ...) \
54 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
55 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
56
57#define COUNT_2(EMITTER, PREFIX, ...) \
58 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
59 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
60 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
61
62#define COUNT_3(EMITTER, PREFIX, ...) \
63 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
64 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
65 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
66 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
67 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
68
69#define COUNT_4(EMITTER, PREFIX, ...) \
70 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
71 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
72 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
73 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
74 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
75 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
76 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
77 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
78 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
79
80#define COUNT_5(EMITTER, PREFIX, ...) \
81 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
82 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
83 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
84 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
85 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
86 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
87 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
88 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
89 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
90 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
91 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
92 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
93 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
94 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
95 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
96 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
97 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
98
99#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
100 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
101 int currentCycles = THUMB_PREFETCH_CYCLES; \
102 BODY; \
103 cpu->cycles += currentCycles; \
104 }
105
106#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
107 DEFINE_INSTRUCTION_THUMB(NAME, \
108 int immediate = IMMEDIATE; \
109 int rd = opcode & 0x0007; \
110 int rm = (opcode >> 3) & 0x0007; \
111 BODY;)
112
113#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
114 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
115
116DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
117 if (!immediate) {
118 cpu->gprs[rd] = cpu->gprs[rm];
119 } else {
120 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
121 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
122 }
123 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
124
125DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
126 if (!immediate) {
127 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
128 cpu->gprs[rd] = 0;
129 } else {
130 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
131 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
132 }
133 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
134
135DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
136 if (!immediate) {
137 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
138 if (cpu->cpsr.c) {
139 cpu->gprs[rd] = 0xFFFFFFFF;
140 } else {
141 cpu->gprs[rd] = 0;
142 }
143 } else {
144 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
145 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
146 }
147 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
148
149DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4, ¤tCycles))
150DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate, ¤tCycles))
151DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2, ¤tCycles))
152DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
153DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
154DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
155
156#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
157 DEFINE_INSTRUCTION_THUMB(NAME, \
158 int rm = RM; \
159 int rd = opcode & 0x0007; \
160 int rn = (opcode >> 3) & 0x0007; \
161 BODY;)
162
163#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
164 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
165
166DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
167DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
168
169#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
170 DEFINE_INSTRUCTION_THUMB(NAME, \
171 int immediate = IMMEDIATE; \
172 int rd = opcode & 0x0007; \
173 int rn = (opcode >> 3) & 0x0007; \
174 BODY;)
175
176#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
177 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
178
179DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
180DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
181
182#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
183 DEFINE_INSTRUCTION_THUMB(NAME, \
184 int rd = RD; \
185 int immediate = opcode & 0x00FF; \
186 BODY;)
187
188#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
189 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
190
191DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
192DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
193DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
194DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
195
196#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
197 DEFINE_INSTRUCTION_THUMB(NAME, \
198 int rd = opcode & 0x0007; \
199 int rn = (opcode >> 3) & 0x0007; \
200 BODY;)
201
202DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
203DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
204DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
205 int rs = cpu->gprs[rn] & 0xFF;
206 if (rs) {
207 if (rs < 32) {
208 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
209 cpu->gprs[rd] <<= rs;
210 } else {
211 if (rs > 32) {
212 cpu->cpsr.c = 0;
213 } else {
214 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
215 }
216 cpu->gprs[rd] = 0;
217 }
218 }
219 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
220
221DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
222 int rs = cpu->gprs[rn] & 0xFF;
223 if (rs) {
224 if (rs < 32) {
225 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
226 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
227 } else {
228 if (rs > 32) {
229 cpu->cpsr.c = 0;
230 } else {
231 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
232 }
233 cpu->gprs[rd] = 0;
234 }
235 }
236 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
237
238DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
239 int rs = cpu->gprs[rn] & 0xFF;
240 if (rs) {
241 if (rs < 32) {
242 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
243 cpu->gprs[rd] >>= rs;
244 } else {
245 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
246 if (cpu->cpsr.c) {
247 cpu->gprs[rd] = 0xFFFFFFFF;
248 } else {
249 cpu->gprs[rd] = 0;
250 }
251 }
252 }
253 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
254
255DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
256 int n = cpu->gprs[rn];
257 int d = cpu->gprs[rd];
258 cpu->gprs[rd] = d + n + cpu->cpsr.c;
259 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
260
261DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
262 int n = cpu->gprs[rn] + !cpu->cpsr.c;
263 int d = cpu->gprs[rd];
264 cpu->gprs[rd] = d - n;
265 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
266DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
267 int rs = cpu->gprs[rn] & 0xFF;
268 if (rs) {
269 int r4 = rs & 0x1F;
270 if (r4 > 0) {
271 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
272 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
273 } else {
274 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
275 }
276 }
277 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
278DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
279DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
280DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
281DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
282DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
283DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rn]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
284DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
285DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
286
287#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
288 DEFINE_INSTRUCTION_THUMB(NAME, \
289 int rd = (opcode & 0x0007) | H1; \
290 int rm = ((opcode >> 3) & 0x0007) | H2; \
291 BODY;)
292
293#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
294 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
295 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
296 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
297 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
298
299DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
300 cpu->gprs[rd] += cpu->gprs[rm];
301 if (rd == ARM_PC) {
302 THUMB_WRITE_PC;
303 })
304
305DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
306DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
307 cpu->gprs[rd] = cpu->gprs[rm];
308 if (rd == ARM_PC) {
309 THUMB_WRITE_PC;
310 })
311
312#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
313 DEFINE_INSTRUCTION_THUMB(NAME, \
314 int rd = RD; \
315 int immediate = (opcode & 0x00FF) << 2; \
316 BODY;)
317
318#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
319 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
320
321DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles))
322DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate, ¤tCycles))
323DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
324
325DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
326DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
327
328#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
329 DEFINE_INSTRUCTION_THUMB(NAME, \
330 int rm = RM; \
331 int rd = opcode & 0x0007; \
332 int rn = (opcode >> 3) & 0x0007; \
333 BODY;)
334
335#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
336 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
337
338DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
339DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
340DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
341DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
342DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles))
343DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
344DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
345DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
346
347#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
348 DEFINE_INSTRUCTION_THUMB(NAME, \
349 int rn = RN; \
350 UNUSED(rn); \
351 int rs = opcode & 0xFF; \
352 int32_t address = ADDRESS; \
353 int m; \
354 int i; \
355 int total = 0; \
356 PRE_BODY; \
357 for LOOP { \
358 if (rs & m) { \
359 BODY; \
360 address OP 4; \
361 ++total; \
362 } \
363 } \
364 POST_BODY; \
365 currentCycles += cpu->memory->waitMultiple(cpu->memory, address, total); \
366 WRITEBACK;)
367
368#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
369 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
370
371DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
372 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
373 if (!((1 << rn) & rs)) {
374 cpu->gprs[rn] = address;
375 })
376
377DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
378 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
379 THUMB_STORE_POST_BODY;
380 cpu->gprs[rn] = address;)
381
382#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
383 DEFINE_INSTRUCTION_THUMB(B ## COND, \
384 if (ARM_COND_ ## COND) { \
385 int8_t immediate = opcode; \
386 cpu->gprs[ARM_PC] += immediate << 1; \
387 THUMB_WRITE_PC; \
388 })
389
390DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
391DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
392DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
393DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
394DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
395DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
396DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
397DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
398DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
399DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
400DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
401DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
402DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
403DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
404
405DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
406DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
407
408DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
409 opcode & 0x00FF,
410 cpu->gprs[ARM_SP],
411 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
412 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
413 +=,
414 , ,
415 cpu->gprs[ARM_SP] = address)
416
417DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
418 opcode & 0x00FF,
419 cpu->gprs[ARM_SP],
420 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
421 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address, 0),
422 +=,
423 ,
424 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address, 0) & 0xFFFFFFFE;
425 address += 4;,
426 cpu->gprs[ARM_SP] = address;
427 THUMB_WRITE_PC;)
428
429DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
430 opcode & 0x00FF,
431 cpu->gprs[ARM_SP] - 4,
432 (m = 0x80, i = 7; m; m >>= 1, --i),
433 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
434 -=,
435 ,
436 THUMB_STORE_POST_BODY,
437 cpu->gprs[ARM_SP] = address + 4)
438
439DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
440 opcode & 0x00FF,
441 cpu->gprs[ARM_SP] - 4,
442 (m = 0x80, i = 7; m; m >>= 1, --i),
443 cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0),
444 -=,
445 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR], 0);
446 address -= 4;,
447 THUMB_STORE_POST_BODY,
448 cpu->gprs[ARM_SP] = address + 4)
449
450DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
451DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
452DEFINE_INSTRUCTION_THUMB(B,
453 int16_t immediate = (opcode & 0x07FF) << 5;
454 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
455 THUMB_WRITE_PC;)
456
457DEFINE_INSTRUCTION_THUMB(BL1,
458 int16_t immediate = (opcode & 0x07FF) << 5;
459 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
460
461DEFINE_INSTRUCTION_THUMB(BL2,
462 uint16_t immediate = (opcode & 0x07FF) << 1;
463 uint32_t pc = cpu->gprs[ARM_PC];
464 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
465 cpu->gprs[ARM_LR] = pc - 1;
466 THUMB_WRITE_PC;)
467
468DEFINE_INSTRUCTION_THUMB(BX,
469 int rm = (opcode >> 3) & 0xF;
470 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
471 int misalign = 0;
472 if (rm == ARM_PC) {
473 misalign = cpu->gprs[rm] & 0x00000002;
474 }
475 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
476 if (cpu->executionMode == MODE_THUMB) {
477 THUMB_WRITE_PC;
478 } else {
479 ARM_WRITE_PC;
480 })
481
482DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
483
484#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
485 EMITTER ## NAME
486
487#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
488 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
489 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
490 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
491 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
492
493#define DUMMY(X, ...) X,
494#define DUMMY_4(...) \
495 DUMMY(__VA_ARGS__) \
496 DUMMY(__VA_ARGS__) \
497 DUMMY(__VA_ARGS__) \
498 DUMMY(__VA_ARGS__)
499
500#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
501 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
502 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
503 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
504 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
505 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
506 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
507 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
508 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
509 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
510 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
511 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
512 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
513 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
514 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
515 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
516 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
517 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
518 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
519 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
520 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
521 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
522 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
523 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
524 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
525 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
526 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
527 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
528 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
529 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
530 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
531 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
532 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
533 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
534 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
535 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
536 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
537 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
538 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
539 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
540 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
541 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
542 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
543 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
544 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
545 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
546 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
547 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
548 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
549 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
550 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
551 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
552 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
553 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
554 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
555 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
556 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
557 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
558 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
559 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
560 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
561 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
562 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
563 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
564 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
565 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
566 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
567 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
568 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
569 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
570 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
571 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
572 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
573 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
574 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
575 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
576 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
577 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
578 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
579 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
580 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
581 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
582 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
583 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
584 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
585 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
586 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
587 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
588 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
589 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
590 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
591 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
592
593static const ThumbInstruction _thumbTable[0x400] = {
594 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
595};