src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "gba-serialize.h"
6#include "hle-bios.h"
7#include "util/memory.h"
8
9static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
10static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count);
11static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
12
13static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
14static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
17static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
18static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
19static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
20
21void GBAMemoryInit(struct GBA* gba) {
22 struct ARMCore* cpu = gba->cpu;
23 cpu->memory.load32 = GBALoad32;
24 cpu->memory.load16 = GBALoad16;
25 cpu->memory.loadU16 = GBALoadU16;
26 cpu->memory.load8 = GBALoad8;
27 cpu->memory.loadU8 = GBALoadU8;
28 cpu->memory.store32 = GBAStore32;
29 cpu->memory.store16 = GBAStore16;
30 cpu->memory.store8 = GBAStore8;
31
32 gba->memory.bios = (uint32_t*) hleBios;
33 gba->memory.fullBios = 0;
34 gba->memory.wram = 0;
35 gba->memory.iwram = 0;
36 gba->memory.rom = 0;
37 gba->memory.gpio.p = gba;
38
39 int i;
40 for (i = 0; i < 16; ++i) {
41 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
42 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
43 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
44 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
45 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
46 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
47 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
48 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
49 }
50 for (; i < 256; ++i) {
51 gba->memory.waitstatesNonseq16[i] = 0;
52 gba->memory.waitstatesSeq16[i] = 0;
53 gba->memory.waitstatesNonseq32[i] = 0;
54 gba->memory.waitstatesSeq32[i] = 0;
55 }
56
57 gba->memory.activeRegion = -1;
58 cpu->memory.activeRegion = 0;
59 cpu->memory.activeMask = 0;
60 cpu->memory.setActiveRegion = GBASetActiveRegion;
61 cpu->memory.activeSeqCycles32 = 0;
62 cpu->memory.activeSeqCycles16 = 0;
63 cpu->memory.activeNonseqCycles32 = 0;
64 cpu->memory.activeNonseqCycles16 = 0;
65 cpu->memory.activeUncachedCycles32 = 0;
66 cpu->memory.activeUncachedCycles16 = 0;
67 gba->memory.biosPrefetch = 0;
68 cpu->memory.waitMultiple = GBAWaitMultiple;
69}
70
71void GBAMemoryDeinit(struct GBA* gba) {
72 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
73 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
74 if (gba->memory.rom) {
75 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
76 }
77 GBASavedataDeinit(&gba->memory.savedata);
78}
79
80void GBAMemoryReset(struct GBA* gba) {
81 if (gba->memory.wram) {
82 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
83 }
84 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
85
86 if (gba->memory.iwram) {
87 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
88 }
89 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
90
91 memset(gba->memory.io, 0, sizeof(gba->memory.io));
92 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
93 int i;
94 for (i = 0; i < 4; ++i) {
95 gba->memory.dma[i].count = 0x10000;
96 gba->memory.dma[i].nextEvent = INT_MAX;
97 }
98 gba->memory.activeDMA = -1;
99 gba->memory.nextDMA = INT_MAX;
100 gba->memory.eventDiff = 0;
101
102 if (!gba->memory.wram || !gba->memory.iwram) {
103 GBAMemoryDeinit(gba);
104 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
105 }
106}
107
108static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
109 struct GBA* gba = (struct GBA*) cpu->master;
110 struct GBAMemory* memory = &gba->memory;
111
112 if (cpu->currentPC == gba->busyLoop) {
113 GBAHalt(gba);
114 }
115
116 int newRegion = address >> BASE_OFFSET;
117 if (newRegion == memory->activeRegion) {
118 return;
119 }
120 if (memory->activeRegion == REGION_BIOS) {
121 memory->biosPrefetch = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
122 }
123 memory->activeRegion = newRegion;
124 switch (address & ~OFFSET_MASK) {
125 case BASE_BIOS:
126 cpu->memory.activeRegion = memory->bios;
127 cpu->memory.activeMask = SIZE_BIOS - 1;
128 break;
129 case BASE_WORKING_RAM:
130 cpu->memory.activeRegion = memory->wram;
131 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
132 break;
133 case BASE_WORKING_IRAM:
134 cpu->memory.activeRegion = memory->iwram;
135 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
136 break;
137 case BASE_CART0:
138 case BASE_CART0_EX:
139 case BASE_CART1:
140 case BASE_CART1_EX:
141 case BASE_CART2:
142 case BASE_CART2_EX:
143 cpu->memory.activeRegion = memory->rom;
144 cpu->memory.activeMask = SIZE_CART0 - 1;
145 break;
146 default:
147 cpu->memory.activeRegion = 0;
148 cpu->memory.activeMask = 0;
149 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
150 break;
151 }
152 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
153 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
154 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
155 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
156 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
157 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
158}
159
160int32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
161 struct GBA* gba = (struct GBA*) cpu->master;
162 struct GBAMemory* memory = &gba->memory;
163 uint32_t value = 0;
164 int wait = 0;
165
166 switch (address & ~OFFSET_MASK) {
167 case BASE_BIOS:
168 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
169 if (address < SIZE_BIOS) {
170 LOAD_32(value, address, memory->bios);
171 } else {
172 value = 0;
173 }
174 } else {
175 value = memory->biosPrefetch;
176 }
177 break;
178 case BASE_WORKING_RAM:
179 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
180 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
181 break;
182 case BASE_WORKING_IRAM:
183 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
184 break;
185 case BASE_IO:
186 value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
187 break;
188 case BASE_PALETTE_RAM:
189 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
190 break;
191 case BASE_VRAM:
192 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
193 break;
194 case BASE_OAM:
195 LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
196 break;
197 case BASE_CART0:
198 case BASE_CART0_EX:
199 case BASE_CART1:
200 case BASE_CART1_EX:
201 case BASE_CART2:
202 case BASE_CART2_EX:
203 wait = memory->waitstatesNonseq32[address >> BASE_OFFSET];
204 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
205 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom);
206 }
207 break;
208 case BASE_CART_SRAM:
209 case BASE_CART_SRAM_MIRROR:
210 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
211 break;
212 default:
213 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
214 if (cpu->executionMode == MODE_ARM) {
215 value = cpu->memory.load32(cpu, cpu->currentPC + WORD_SIZE_ARM * 2, 0);
216 } else {
217 value = cpu->memory.load16(cpu, cpu->currentPC + WORD_SIZE_THUMB * 2, 0);
218 value |= value << 16;
219 }
220 break;
221 }
222
223
224 if (cycleCounter) {
225 *cycleCounter += 2 + wait;
226 }
227 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
228 int rotate = (address & 3) << 3;
229 return (value >> rotate) | (value << (32 - rotate));
230}
231
232uint16_t GBALoadU16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
233 return GBALoad16(cpu, address, cycleCounter);
234}
235
236int16_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
237 struct GBA* gba = (struct GBA*) cpu->master;
238 struct GBAMemory* memory = &gba->memory;
239 uint16_t value = 0;
240 int wait = 0;
241
242 switch (address & ~OFFSET_MASK) {
243 case BASE_BIOS:
244 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
245 if (address < SIZE_BIOS) {
246 LOAD_16(value, address, memory->bios);
247 } else {
248 value = 0;
249 }
250 } else {
251 value = memory->biosPrefetch;
252 }
253 break;
254 case BASE_WORKING_RAM:
255 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
256 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
257 break;
258 case BASE_WORKING_IRAM:
259 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
260 break;
261 case BASE_IO:
262 value = GBAIORead(gba, address & (SIZE_IO - 1));
263 break;
264 case BASE_PALETTE_RAM:
265 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
266 break;
267 case BASE_VRAM:
268 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
269 break;
270 case BASE_OAM:
271 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
272 break;
273 case BASE_CART0:
274 case BASE_CART0_EX:
275 case BASE_CART1:
276 case BASE_CART1_EX:
277 case BASE_CART2:
278 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
279 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
280 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
281 }
282 break;
283 case BASE_CART2_EX:
284 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
285 if (memory->savedata.type == SAVEDATA_EEPROM) {
286 value = GBASavedataReadEEPROM(&memory->savedata);
287 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
288 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
289 }
290 break;
291 case BASE_CART_SRAM:
292 case BASE_CART_SRAM_MIRROR:
293 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
294 break;
295 default:
296 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
297 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
298 break;
299 }
300
301 if (cycleCounter) {
302 *cycleCounter += 2 + wait;
303 }
304 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
305 int rotate = (address & 1) << 3;
306 return (value >> rotate) | (value << (16 - rotate));
307}
308
309uint8_t GBALoadU8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
310 return GBALoad8(cpu, address, cycleCounter);
311}
312
313int8_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
314 struct GBA* gba = (struct GBA*) cpu->master;
315 struct GBAMemory* memory = &gba->memory;
316 int8_t value = 0;
317 int wait = 0;
318
319 switch (address & ~OFFSET_MASK) {
320 case BASE_BIOS:
321 if (cpu->currentPC >> BASE_OFFSET == REGION_BIOS) {
322 if (address < SIZE_BIOS) {
323 value = ((int8_t*) memory->bios)[address];
324 } else {
325 value = 0;
326 }
327 } else {
328 value = memory->biosPrefetch;
329 }
330 break;
331 case BASE_WORKING_RAM:
332 value = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
333 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
334 break;
335 case BASE_WORKING_IRAM:
336 value = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
337 break;
338 case BASE_IO:
339 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
340 break;
341 case BASE_PALETTE_RAM:
342 value = ((int8_t*) gba->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
343 break;
344 case BASE_VRAM:
345 value = ((int8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
346 break;
347 case BASE_OAM:
348 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
349 break;
350 case BASE_CART0:
351 case BASE_CART0_EX:
352 case BASE_CART1:
353 case BASE_CART1_EX:
354 case BASE_CART2:
355 case BASE_CART2_EX:
356 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
357 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
358 value = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
359 }
360 break;
361 case BASE_CART_SRAM:
362 case BASE_CART_SRAM_MIRROR:
363 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
364 if (memory->savedata.type == SAVEDATA_NONE) {
365 GBASavedataInitSRAM(&memory->savedata);
366 }
367 if (memory->savedata.type == SAVEDATA_SRAM) {
368 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
369 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
370 value = GBASavedataReadFlash(&memory->savedata, address);
371 }
372 break;
373 default:
374 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
375 value = cpu->memory.load16(cpu, cpu->currentPC + (cpu->executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
376 break;
377 }
378
379 if (cycleCounter) {
380 *cycleCounter += 2 + wait;
381 }
382 return value;
383}
384
385void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
386 struct GBA* gba = (struct GBA*) cpu->master;
387 struct GBAMemory* memory = &gba->memory;
388 int wait = 0;
389
390 switch (address & ~OFFSET_MASK) {
391 case BASE_WORKING_RAM:
392 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
393 wait = memory->waitstatesNonseq32[REGION_WORKING_RAM];
394 break;
395 case BASE_WORKING_IRAM:
396 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
397 break;
398 case BASE_IO:
399 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
400 break;
401 case BASE_PALETTE_RAM:
402 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
403 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
404 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
405 break;
406 case BASE_VRAM:
407 if ((address & OFFSET_MASK) < SIZE_VRAM) {
408 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
409 } else if ((address & OFFSET_MASK) < 0x00020000) {
410 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
411 }
412 break;
413 case BASE_OAM:
414 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
415 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
416 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
417 break;
418 case BASE_CART0:
419 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
420 break;
421 case BASE_CART_SRAM:
422 case BASE_CART_SRAM_MIRROR:
423 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
424 break;
425 default:
426 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
427 break;
428 }
429
430 if (cycleCounter) {
431 *cycleCounter += 1 + wait;
432 }
433}
434
435void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
436 struct GBA* gba = (struct GBA*) cpu->master;
437 struct GBAMemory* memory = &gba->memory;
438 int wait = 0;
439
440 switch (address & ~OFFSET_MASK) {
441 case BASE_WORKING_RAM:
442 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
443 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
444 break;
445 case BASE_WORKING_IRAM:
446 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
447 break;
448 case BASE_IO:
449 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
450 break;
451 case BASE_PALETTE_RAM:
452 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
453 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
454 break;
455 case BASE_VRAM:
456 if ((address & OFFSET_MASK) < SIZE_VRAM) {
457 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
458 } else if ((address & OFFSET_MASK) < 0x00020000) {
459 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
460 }
461 break;
462 case BASE_OAM:
463 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
464 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
465 break;
466 case BASE_CART0:
467 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
468 uint32_t reg = address & 0xFFFFFF;
469 GBAGPIOWrite(&memory->gpio, reg, value);
470 } else {
471 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
472 }
473 break;
474 case BASE_CART2_EX:
475 if (memory->savedata.type == SAVEDATA_NONE) {
476 GBASavedataInitEEPROM(&memory->savedata);
477 }
478 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
479 break;
480 case BASE_CART_SRAM:
481 case BASE_CART_SRAM_MIRROR:
482 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
483 break;
484 default:
485 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
486 break;
487 }
488
489 if (cycleCounter) {
490 *cycleCounter += 1 + wait;
491 }
492}
493
494void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
495 struct GBA* gba = (struct GBA*) cpu->master;
496 struct GBAMemory* memory = &gba->memory;
497 int wait = 0;
498
499 switch (address & ~OFFSET_MASK) {
500 case BASE_WORKING_RAM:
501 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
502 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
503 break;
504 case BASE_WORKING_IRAM:
505 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
506 break;
507 case BASE_IO:
508 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
509 break;
510 case BASE_PALETTE_RAM:
511 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
512 break;
513 case BASE_VRAM:
514 if (address >= 0x06018000) {
515 // TODO: check BG mode
516 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
517 break;
518 }
519 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
520 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
521 break;
522 case BASE_OAM:
523 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
524 break;
525 case BASE_CART0:
526 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
527 break;
528 case BASE_CART_SRAM:
529 case BASE_CART_SRAM_MIRROR:
530 if (memory->savedata.type == SAVEDATA_NONE) {
531 if (address == SAVEDATA_FLASH_BASE) {
532 GBASavedataInitFlash(&memory->savedata);
533 } else {
534 GBASavedataInitSRAM(&memory->savedata);
535 }
536 }
537 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
538 GBASavedataWriteFlash(&memory->savedata, address, value);
539 } else if (memory->savedata.type == SAVEDATA_SRAM) {
540 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
541 }
542 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
543 break;
544 default:
545 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
546 break;
547 }
548
549 if (cycleCounter) {
550 *cycleCounter += 1 + wait;
551 }
552}
553
554static int GBAWaitMultiple(struct ARMCore* cpu, uint32_t startAddress, int count) {
555 struct GBA* gba = (struct GBA*) cpu->master;
556 struct GBAMemory* memory = &gba->memory;
557 int wait = 1 + memory->waitstatesNonseq32[startAddress >> BASE_OFFSET];
558 wait += (1 + memory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
559 return wait;
560}
561
562void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
563 struct GBAMemory* memory = &gba->memory;
564 struct ARMCore* cpu = gba->cpu;
565 int sram = parameters & 0x0003;
566 int ws0 = (parameters & 0x000C) >> 2;
567 int ws0seq = (parameters & 0x0010) >> 4;
568 int ws1 = (parameters & 0x0060) >> 5;
569 int ws1seq = (parameters & 0x0080) >> 7;
570 int ws2 = (parameters & 0x0300) >> 8;
571 int ws2seq = (parameters & 0x0400) >> 10;
572 int prefetch = parameters & 0x4000;
573
574 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
575 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
576 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
577 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
578
579 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
580 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
581 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
582
583 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
584 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
585 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
586
587 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
588 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
589 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
590
591 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
592 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
593 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
594
595 if (!prefetch) {
596 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
597 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
598 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
599
600 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
601 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
602 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
603
604 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
605 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
606 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
607
608 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
609 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
610 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
611 } else {
612 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
613 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
614 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
615
616 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
617 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
618 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
619
620 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
621 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
622 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
623
624 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
625 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
626 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
627 }
628
629 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
630 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
631
632 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
633 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
634
635 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
636 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
637}
638
639void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
640 struct GBAMemory* memory = &gba->memory;
641 memory->dma[dma].source = address & 0xFFFFFFFE;
642}
643
644void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
645 struct GBAMemory* memory = &gba->memory;
646 memory->dma[dma].dest = address & 0xFFFFFFFE;
647}
648
649void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
650 struct GBAMemory* memory = &gba->memory;
651 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
652}
653
654uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
655 struct GBAMemory* memory = &gba->memory;
656 struct GBADMA* currentDma = &memory->dma[dma];
657 int wasEnabled = currentDma->enable;
658 currentDma->packed = control;
659
660 if (currentDma->drq) {
661 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
662 }
663
664 if (!wasEnabled && currentDma->enable) {
665 currentDma->nextSource = currentDma->source;
666 currentDma->nextDest = currentDma->dest;
667 currentDma->nextCount = currentDma->count;
668 GBAMemoryScheduleDMA(gba, dma, currentDma);
669 }
670 // If the DMA has already occurred, this value might have changed since the function started
671 return currentDma->packed;
672};
673
674void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
675 struct ARMCore* cpu = gba->cpu;
676 switch (info->timing) {
677 case DMA_TIMING_NOW:
678 info->nextEvent = cpu->cycles;
679 GBAMemoryUpdateDMAs(gba, 0);
680 break;
681 case DMA_TIMING_HBLANK:
682 // Handled implicitly
683 info->nextEvent = INT_MAX;
684 break;
685 case DMA_TIMING_VBLANK:
686 // Handled implicitly
687 info->nextEvent = INT_MAX;
688 break;
689 case DMA_TIMING_CUSTOM:
690 info->nextEvent = INT_MAX;
691 switch (number) {
692 case 0:
693 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
694 break;
695 case 1:
696 case 2:
697 GBAAudioScheduleFifoDma(&gba->audio, number, info);
698 break;
699 case 3:
700 // GBAVideoScheduleVCaptureDma(dma, info);
701 break;
702 }
703 }
704}
705
706void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
707 struct GBAMemory* memory = &gba->memory;
708 struct GBADMA* dma;
709 int i;
710 for (i = 0; i < 4; ++i) {
711 dma = &memory->dma[i];
712 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
713 dma->nextEvent = cycles;
714 }
715 }
716 GBAMemoryUpdateDMAs(gba, 0);
717}
718
719void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
720 struct GBAMemory* memory = &gba->memory;
721 struct GBADMA* dma;
722 int i;
723 for (i = 0; i < 4; ++i) {
724 dma = &memory->dma[i];
725 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
726 dma->nextEvent = cycles;
727 }
728 }
729 GBAMemoryUpdateDMAs(gba, 0);
730}
731
732int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
733 struct GBAMemory* memory = &gba->memory;
734 if (memory->nextDMA == INT_MAX) {
735 return INT_MAX;
736 }
737 memory->nextDMA -= cycles;
738 memory->eventDiff += cycles;
739 if (memory->nextDMA <= 0) {
740 struct GBADMA* dma = &memory->dma[memory->activeDMA];
741 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
742 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
743 memory->eventDiff = 0;
744 }
745 return memory->nextDMA;
746}
747
748void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
749 int i;
750 struct GBAMemory* memory = &gba->memory;
751 struct ARMCore* cpu = gba->cpu;
752 memory->activeDMA = -1;
753 memory->nextDMA = INT_MAX;
754 for (i = 3; i >= 0; --i) {
755 struct GBADMA* dma = &memory->dma[i];
756 if (dma->nextEvent != INT_MAX) {
757 dma->nextEvent -= cycles;
758 if (dma->enable) {
759 memory->activeDMA = i;
760 memory->nextDMA = dma->nextEvent;
761 }
762 }
763 }
764 if (memory->nextDMA < cpu->nextEvent) {
765 cpu->nextEvent = memory->nextDMA;
766 }
767}
768
769void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
770 struct GBAMemory* memory = &gba->memory;
771 struct ARMCore* cpu = gba->cpu;
772 uint32_t width = info->width ? 4 : 2;
773 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
774 int destOffset = DMA_OFFSET[info->dstControl] * width;
775 int32_t wordsRemaining = info->nextCount;
776 uint32_t source = info->nextSource;
777 uint32_t dest = info->nextDest;
778 uint32_t sourceRegion = source >> BASE_OFFSET;
779 uint32_t destRegion = dest >> BASE_OFFSET;
780 int32_t cycles = 0;
781
782 if (source == info->source) {
783 // TODO: support 4 cycles for ROM access
784 cycles += 2;
785 if (width == 4) {
786 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
787 source &= 0xFFFFFFFC;
788 dest &= 0xFFFFFFFC;
789 } else {
790 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
791 }
792 } else {
793 if (width == 4) {
794 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
795 } else {
796 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
797 }
798 }
799
800 if (width == 4) {
801 int32_t word;
802 word = cpu->memory.load32(cpu, source, 0);
803 cpu->memory.store32(cpu, dest, word, 0);
804 source += sourceOffset;
805 dest += destOffset;
806 --wordsRemaining;
807 } else {
808 uint16_t word;
809 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
810 word = GBASavedataReadEEPROM(&memory->savedata);
811 cpu->memory.store16(cpu, dest, word, 0);
812 source += sourceOffset;
813 dest += destOffset;
814 --wordsRemaining;
815 } else if (destRegion == REGION_CART2_EX) {
816 if (memory->savedata.type == SAVEDATA_NONE) {
817 GBASavedataInitEEPROM(&memory->savedata);
818 }
819 word = cpu->memory.load16(cpu, source, 0);
820 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
821 source += sourceOffset;
822 dest += destOffset;
823 --wordsRemaining;
824 } else {
825 word = cpu->memory.load16(cpu, source, 0);
826 cpu->memory.store16(cpu, dest, word, 0);
827 source += sourceOffset;
828 dest += destOffset;
829 --wordsRemaining;
830 }
831 }
832
833 if (!wordsRemaining) {
834 if (!info->repeat) {
835 info->enable = 0;
836 info->nextEvent = INT_MAX;
837
838 // Clear the enable bit in memory
839 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
840 } else {
841 info->nextCount = info->count;
842 if (info->dstControl == DMA_INCREMENT_RELOAD) {
843 info->nextDest = info->dest;
844 }
845 GBAMemoryScheduleDMA(gba, number, info);
846 }
847 if (info->doIrq) {
848 GBARaiseIRQ(gba, IRQ_DMA0 + number);
849 }
850 } else {
851 info->nextDest = dest;
852 info->nextCount = wordsRemaining;
853 }
854 info->nextSource = source;
855
856 int i;
857 for (i = 0; i < 4; ++i) {
858 if (memory->dma[i].nextEvent != INT_MAX) {
859 memory->dma[i].nextEvent += cycles;
860 }
861 }
862 cpu->cycles += cycles;
863}
864
865void GBAMemorySerialize(struct GBAMemory* memory, struct GBASerializedState* state) {
866 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
867 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
868}
869
870void GBAMemoryDeserialize(struct GBAMemory* memory, struct GBASerializedState* state) {
871 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
872 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
873}