src/arm.c (view raw)
1#include "arm.h"
2
3#define ARM_SIGN(I) ((I) >> 31)
4#define ARM_ROR(I, ROTATE) (((I) >> ROTATE) | (I << (32 - ROTATE)))
5
6static inline void _ARMSetMode(struct ARMCore*, enum ExecutionMode);
7static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
8static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory*, uint32_t address, uint32_t* opcodeOut);
9
10static inline void _ARMReadCPSR(struct ARMCore* cpu) {
11 _ARMSetMode(cpu, cpu->cpsr.t);
12}
13
14static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
15 return mode != MODE_SYSTEM && mode != MODE_USER;
16}
17
18// Addressing mode 1
19static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
20 // TODO
21}
22
23static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
24 int rotate = (opcode & 0x00000F00) >> 7;
25 int immediate = opcode & 0x000000FF;
26 if (!rotate) {
27 cpu->shifterOperand = immediate;
28 cpu->shifterCarryOut = cpu->cpsr.c;
29 } else {
30 cpu->shifterOperand = ARM_ROR(immediate, rotate);
31 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
32 }
33}
34
35static const ARMInstruction armTable[0x10000];
36
37static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
38 if (executionMode == cpu->executionMode) {
39 return;
40 }
41
42 cpu->executionMode = executionMode;
43 switch (executionMode) {
44 case MODE_ARM:
45 cpu->cpsr.t = 0;
46 cpu->instructionWidth = WORD_SIZE_ARM;
47 cpu->loadInstruction = _ARMLoadInstructionARM;
48 break;
49 case MODE_THUMB:
50 cpu->cpsr.t = 1;
51 cpu->instructionWidth = WORD_SIZE_THUMB;
52 cpu->loadInstruction = _ARMLoadInstructionThumb;
53 }
54}
55
56static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
57 uint32_t opcode = memory->load32(memory, address);
58 *opcodeOut = opcode;
59 return 0;
60}
61
62static ARMInstruction _ARMLoadInstructionThumb(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
63 uint16_t opcode = memory->loadU16(memory, address);
64 *opcodeOut = opcode;
65 return 0;
66}
67
68void ARMInit(struct ARMCore* cpu) {
69 int i;
70 for (i = 0; i < 16; ++i) {
71 cpu->gprs[i] = 0;
72 }
73
74 cpu->cpsr.packed = MODE_SYSTEM;
75 cpu->spsr.packed = 0;
76
77 cpu->cyclesToEvent = 0;
78
79 cpu->shifterOperand = 0;
80 cpu->shifterCarryOut = 0;
81
82 cpu->memory = 0;
83 cpu->board = 0;
84
85 cpu->executionMode = MODE_THUMB;
86 _ARMSetMode(cpu, MODE_ARM);
87}
88
89void ARMAssociateMemory(struct ARMCore* cpu, struct ARMMemory* memory) {
90 cpu->memory = memory;
91}
92
93inline void ARMCycle(struct ARMCore* cpu) {
94 // TODO
95 uint32_t opcode;
96 ARMInstruction instruction = cpu->loadInstruction(cpu->memory, cpu->gprs[ARM_PC] - cpu->instructionWidth, &opcode);
97 cpu->gprs[ARM_PC] += cpu->instructionWidth;
98 instruction(cpu, opcode);
99}
100
101// Instruction definitions
102// Beware pre-processor antics
103
104#define ARM_CARRY_FROM(M, N, D) ((ARM_SIGN((M) | (N))) && !(ARM_SIGN(D)))
105#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
106#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
107#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
108
109#define ARM_COND_EQ (cpu->cpsr.z)
110#define ARM_COND_NE (!cpu->cpsr.z)
111#define ARM_COND_CS (cpu->cpsr.c)
112#define ARM_COND_CC (!cpu->cpsr.c)
113#define ARM_COND_MI (cpu->cpsr.n)
114#define ARM_COND_PL (!cpu->cpsr.n)
115#define ARM_COND_VS (cpu->cpsr.v)
116#define ARM_COND_VC (!cpu->cpsr.v)
117#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
118#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
119#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
120#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
121#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
122#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
123#define ARM_COND_AL 1
124
125#define ARM_ADDITION_S(M, N, D) \
126 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
127 cpu->cpsr = cpu->spsr; \
128 _ARMReadCPSR(cpu); \
129 } else { \
130 cpu->cpsr.n = ARM_SIGN(D); \
131 cpu->cpsr.z = !(D); \
132 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
133 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
134 }
135
136#define ARM_SUBTRACTION_S(M, N, D) \
137 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
138 cpu->cpsr = cpu->spsr; \
139 _ARMReadCPSR(cpu); \
140 } else { \
141 cpu->cpsr.n = ARM_SIGN(D); \
142 cpu->cpsr.z = !(D); \
143 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
144 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
145 }
146
147#define ARM_NEUTRAL_S(M, N, D) \
148 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
149 cpu->cpsr = cpu->spsr; \
150 _ARMReadCPSR(cpu); \
151 } else { \
152 cpu->cpsr.n = ARM_SIGN(D); \
153 cpu->cpsr.z = !(D); \
154 cpu->cpsr.c = cpu->shifterCarryOut; \
155 }
156
157#define ADDR_MODE_2_ADDRESS (address)
158#define ADDR_MODE_2_RN (cpu->gprs[rn])
159#define ADDR_MODE_2_RM (cpu->gprs[rm])
160#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
161#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
162#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
163#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
164#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
165#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
166#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
167
168#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
169#define ADDR_MODE_3_RN ADDR_MODE_2_RN
170#define ADDR_MODE_3_RM ADDR_MODE_2_RM
171#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
172#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
173#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
174
175#define DEFINE_INSTRUCTION_EX_ARM(NAME, COND, COND_BODY, BODY) \
176 static void _ARMInstruction ## NAME ## COND (struct ARMCore* cpu, uint32_t opcode) { \
177 if (!COND_BODY) { \
178 return; \
179 } \
180 BODY; \
181 }
182
183#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
184 DEFINE_INSTRUCTION_EX_ARM(NAME, EQ, ARM_COND_EQ, BODY) \
185 DEFINE_INSTRUCTION_EX_ARM(NAME, NE, ARM_COND_NE, BODY) \
186 DEFINE_INSTRUCTION_EX_ARM(NAME, CS, ARM_COND_CS, BODY) \
187 DEFINE_INSTRUCTION_EX_ARM(NAME, CC, ARM_COND_CC, BODY) \
188 DEFINE_INSTRUCTION_EX_ARM(NAME, MI, ARM_COND_MI, BODY) \
189 DEFINE_INSTRUCTION_EX_ARM(NAME, PL, ARM_COND_PL, BODY) \
190 DEFINE_INSTRUCTION_EX_ARM(NAME, VS, ARM_COND_VS, BODY) \
191 DEFINE_INSTRUCTION_EX_ARM(NAME, VC, ARM_COND_VC, BODY) \
192 DEFINE_INSTRUCTION_EX_ARM(NAME, HI, ARM_COND_HI, BODY) \
193 DEFINE_INSTRUCTION_EX_ARM(NAME, LS, ARM_COND_LS, BODY) \
194 DEFINE_INSTRUCTION_EX_ARM(NAME, GE, ARM_COND_GE, BODY) \
195 DEFINE_INSTRUCTION_EX_ARM(NAME, LT, ARM_COND_LT, BODY) \
196 DEFINE_INSTRUCTION_EX_ARM(NAME, GT, ARM_COND_GT, BODY) \
197 DEFINE_INSTRUCTION_EX_ARM(NAME, LE, ARM_COND_LE, BODY) \
198 DEFINE_INSTRUCTION_EX_ARM(NAME, AL, ARM_COND_AL, BODY)
199
200#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
201 DEFINE_INSTRUCTION_ARM(NAME, \
202 int rd = (opcode >> 12) & 0xF; \
203 int rn = (opcode >> 16) & 0xF; \
204 SHIFTER(cpu, opcode); \
205 BODY; \
206 S_BODY; \
207 POST_BODY;)
208
209#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
210 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
211 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
212 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
213 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
214
215#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
216 DEFINE_INSTRUCTION_ARM(NAME, \
217 uint32_t address; \
218 int rn = (opcode >> 16) & 0xF; \
219 int rd = (opcode >> 12) & 0xF; \
220 int rm = opcode & 0xF; \
221 address = ADDRESS; \
222 BODY; \
223 WRITEBACK;)
224
225// TODO: shifters
226#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
227 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
228 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
229 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), , BODY) \
230 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
231 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), , BODY) \
232 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
233 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
234 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
235 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
236 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
237 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
238 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
239
240#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
241 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
242 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
243 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
244 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
245 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
246 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
247 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
248 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
249 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
250 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
251 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
252 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
253
254// Begin ALU definitions
255
256DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
257 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
258
259DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
260 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
261 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
262
263DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
264 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
265
266DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
267 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
268
269DEFINE_ALU_INSTRUCTION_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
270 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
271
272DEFINE_ALU_INSTRUCTION_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
273 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
274
275DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
276 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
277
278DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
279 cpu->gprs[rd] = cpu->shifterOperand;, )
280
281DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
282 cpu->gprs[rd] = ~cpu->shifterOperand;, )
283
284DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
285 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
286
287DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
288 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
289
290DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
291 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
292 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
293
294DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
295 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
296 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
297
298DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
299 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
300
301DEFINE_ALU_INSTRUCTION_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
302 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
303
304DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
305 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
306
307// End ALU definitions
308
309// Begin multiply definitions
310
311DEFINE_INSTRUCTION_ARM(MLA,)
312DEFINE_INSTRUCTION_ARM(MLAS,)
313DEFINE_INSTRUCTION_ARM(MUL,)
314DEFINE_INSTRUCTION_ARM(MULS,)
315DEFINE_INSTRUCTION_ARM(SMLAL,)
316DEFINE_INSTRUCTION_ARM(SMLALS,)
317DEFINE_INSTRUCTION_ARM(SMULL,)
318DEFINE_INSTRUCTION_ARM(SMULLS,)
319DEFINE_INSTRUCTION_ARM(UMLAL,)
320DEFINE_INSTRUCTION_ARM(UMLALS,)
321DEFINE_INSTRUCTION_ARM(UMULL,)
322DEFINE_INSTRUCTION_ARM(UMULLS,)
323
324// End multiply definitions
325
326// Begin load/store definitions
327
328DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
329DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
330DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
331DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
332DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
333DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
334DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
335DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
336
337DEFINE_INSTRUCTION_ARM(SWP,)
338DEFINE_INSTRUCTION_ARM(SWPB,)
339
340// End load/store definitions
341
342// TODO
343DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
344DEFINE_INSTRUCTION_ARM(MSR,)
345DEFINE_INSTRUCTION_ARM(MRS,)
346DEFINE_INSTRUCTION_ARM(MSRI,)
347DEFINE_INSTRUCTION_ARM(MRSI,)
348
349#define DECLARE_INSTRUCTION_ARM(COND, NAME) \
350 _ARMInstruction ## NAME ## COND
351
352#define DO_8(DIRECTIVE) \
353 DIRECTIVE, \
354 DIRECTIVE, \
355 DIRECTIVE, \
356 DIRECTIVE, \
357 DIRECTIVE, \
358 DIRECTIVE, \
359 DIRECTIVE, \
360 DIRECTIVE
361
362#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ALU) \
363 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I)), \
364 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU ## I))
365
366#define DECLARE_ARM_ALU_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
367 DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
368 DECLARE_INSTRUCTION_ARM(COND, ALU), \
369 DECLARE_INSTRUCTION_ARM(COND, EX1), \
370 DECLARE_INSTRUCTION_ARM(COND, ALU), \
371 DECLARE_INSTRUCTION_ARM(COND, EX2), \
372 DECLARE_INSTRUCTION_ARM(COND, ALU), \
373 DECLARE_INSTRUCTION_ARM(COND, EX3), \
374 DECLARE_INSTRUCTION_ARM(COND, ALU), \
375 DECLARE_INSTRUCTION_ARM(COND, EX4)
376
377#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \
378 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) \
379 DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
380
381#define LDRHW ILL
382#define LDRSBW ILL
383#define LDRSHW ILL
384#define LDRHIW ILL
385#define LDRSBIW ILL
386#define LDRSHIW ILL
387#define LDRHUW ILL
388#define LDRSBUW ILL
389#define LDRSHUW ILL
390#define LDRHIUW ILL
391#define LDRSBIUW ILL
392#define LDRSHIUW ILL
393#define STRHIW ILL
394#define STRHIUW ILL
395#define STRHUW ILL
396#define STRHW ILL
397
398#define DECLARE_COND_BLOCK(COND) \
399 DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
400 DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
401 DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRHW, ILL, ILL), \
402 DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRHW, LDRSBW, LDRSHW), \
403 DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
404 DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
405 DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRHIW, ILL, ILL), \
406 DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRHIW, LDRSBIW, LDRSHIW), \
407 DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
408 DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
409 DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRHUW, ILL, ILL), \
410 DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRHUW, LDRSBUW, LDRSHUW), \
411 DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
412 DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
413 DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRHIUW, ILL, ILL), \
414 DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \
415 DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
416 DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
417 DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHPW, ILL, ILL), \
418 DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
419 DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \
420 DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
421 DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHIPW, ILL, ILL), \
422 DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
423 DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRHPU, ILL, ILL), \
424 DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
425 DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRHPUW, ILL, ILL), \
426 DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
427 DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRHIPU, ILL, ILL), \
428 DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
429 DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRHIPUW, ILL, ILL), \
430 DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
431 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
432 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
433 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
434 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EORS), \
435 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUB), \
436 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SUBS), \
437 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSB), \
438 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSBS), \
439 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADD), \
440 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADDS), \
441 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADC), \
442 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ADCS), \
443 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBC), \
444 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, SBCS), \
445 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSC), \
446 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, RSCS), \
447 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
448 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TST), \
449 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
450 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, TEQ), \
451 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MRS), \
452 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMP), \
453 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MSR), \
454 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, CMN), \
455 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORR), \
456 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ORRS), \
457 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOV), \
458 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MOVS), \
459 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
460 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
461 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
462 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)//, \
463 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
464 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
465 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \
466 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \
467 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
468 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
469 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \
470 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \
471 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
472 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
473 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \
474 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \
475 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
476 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
477 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \
478 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \
479 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
480 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
481 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
482 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
483 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
484 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
485 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
486 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
487 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
488 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
489 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
490 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
491 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
492 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
493 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
494 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
495 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
496 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
497 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , W), \
498 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , W), \
499 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
500 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
501 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , W), \
502 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , W), \
503 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
504 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
505 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, W), \
506 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, W), \
507 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
508 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
509 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, W), \
510 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, W), \
511 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
512 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
513 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
514 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
515 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
516 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
517 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
518 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
519 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
520 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
521 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
522 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
523 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
524 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
525 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
526 // DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
527 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , ), \
528 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , ), \
529 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , W), \
530 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , W), \
531 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, ), \
532 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, ), \
533 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, W), \
534 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, W), \
535 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , ), \
536 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , ), \
537 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , W), \
538 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , W), \
539 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, ), \
540 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, ), \
541 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, W), \
542 // DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, W), \
543 // DECLARE_ARM_BRANCH_BLOCK(COND, B), \
544 // DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
545 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
546 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \
547 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \
548 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \
549 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \
550 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \
551 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \
552 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \
553 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \
554 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \
555 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \
556 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \
557 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \
558 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \
559 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \
560 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \
561 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \
562 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \
563 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \
564 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \
565 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
566 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
567 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
568 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
569 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \
570 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \
571 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \
572 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \
573 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
574 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
575 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
576 // DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
577 // DECLARE_ARM_COPROCESSOR_BLOCK(CDP, MCR), \
578 // DECLARE_ARM_SWI_BLOCK
579
580static const ARMInstruction armTable[0x10000] = {
581 DECLARE_COND_BLOCK(EQ),
582 DECLARE_COND_BLOCK(NE),
583 DECLARE_COND_BLOCK(CS),
584 DECLARE_COND_BLOCK(CC),
585 DECLARE_COND_BLOCK(MI),
586 DECLARE_COND_BLOCK(PL),
587 DECLARE_COND_BLOCK(VS),
588 DECLARE_COND_BLOCK(VC),
589 DECLARE_COND_BLOCK(HI),
590 DECLARE_COND_BLOCK(LS),
591 DECLARE_COND_BLOCK(GE),
592 DECLARE_COND_BLOCK(LT),
593 DECLARE_COND_BLOCK(GT),
594 DECLARE_COND_BLOCK(LE),
595 DECLARE_COND_BLOCK(AL)//,
596 //DECLARE_EMPTY_BLOCK
597};