src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25
26static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
27static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
28static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
29static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
30static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
31static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
32static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
33
34void GBAMemoryInit(struct GBA* gba) {
35 struct ARMCore* cpu = gba->cpu;
36 cpu->memory.load32 = GBALoad32;
37 cpu->memory.load16 = GBALoad16;
38 cpu->memory.load8 = GBALoad8;
39 cpu->memory.loadMultiple = GBALoadMultiple;
40 cpu->memory.store32 = GBAStore32;
41 cpu->memory.store16 = GBAStore16;
42 cpu->memory.store8 = GBAStore8;
43 cpu->memory.storeMultiple = GBAStoreMultiple;
44
45 gba->memory.bios = (uint32_t*) hleBios;
46 gba->memory.fullBios = 0;
47 gba->memory.wram = 0;
48 gba->memory.iwram = 0;
49 gba->memory.rom = 0;
50 gba->memory.romSize = 0;
51 gba->memory.hw.p = gba;
52
53 int i;
54 for (i = 0; i < 16; ++i) {
55 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
56 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
57 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
60 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
61 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 }
64 for (; i < 256; ++i) {
65 gba->memory.waitstatesNonseq16[i] = 0;
66 gba->memory.waitstatesSeq16[i] = 0;
67 gba->memory.waitstatesNonseq32[i] = 0;
68 gba->memory.waitstatesSeq32[i] = 0;
69 }
70
71 gba->memory.activeRegion = -1;
72 cpu->memory.activeRegion = 0;
73 cpu->memory.activeMask = 0;
74 cpu->memory.setActiveRegion = GBASetActiveRegion;
75 cpu->memory.activeSeqCycles32 = 0;
76 cpu->memory.activeSeqCycles16 = 0;
77 cpu->memory.activeNonseqCycles32 = 0;
78 cpu->memory.activeNonseqCycles16 = 0;
79 cpu->memory.activeUncachedCycles32 = 0;
80 cpu->memory.activeUncachedCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 if (!gba->memory.wram || !gba->memory.iwram) {
117 GBAMemoryDeinit(gba);
118 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
119 }
120}
121
122static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
123 struct ARMInstructionInfo info;
124 uint32_t nextAddress = address;
125 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
126 if (cpu->executionMode == MODE_THUMB) {
127 while (true) {
128 uint16_t opcode;
129 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
130 ARMDecodeThumb(opcode, &info);
131 switch (info.branchType) {
132 case ARM_BRANCH_NONE:
133 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
134 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
135 gba->idleDetectionStep = -1;
136 return;
137 }
138 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
139 uint32_t offset = 0;
140 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
141 offset = info.memory.offset.immediate;
142 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
143 int reg = info.memory.offset.reg;
144 if (gba->cachedRegisters[reg]) {
145 gba->idleDetectionStep = -1;
146 return;
147 }
148 offset = gba->cachedRegisters[reg];
149 }
150 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
151 loadAddress -= offset;
152 } else {
153 loadAddress += offset;
154 }
155 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
156 gba->idleDetectionStep = -1;
157 return;
158 }
159 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
160 gba->taintedRegisters[info.op1.reg] = true;
161 } else {
162 switch (info.memory.width) {
163 case 1:
164 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
165 break;
166 case 2:
167 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
168 break;
169 case 4:
170 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
171 break;
172 }
173 }
174 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
175 gba->taintedRegisters[info.op1.reg] = true;
176 }
177 nextAddress += WORD_SIZE_THUMB;
178 break;
179 case ARM_BRANCH:
180 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
181 gba->idleLoop = address;
182 gba->idleOptimization = IDLE_LOOP_REMOVE;
183 }
184 gba->idleDetectionStep = -1;
185 return;
186 default:
187 gba->idleDetectionStep = -1;
188 return;
189 }
190 }
191 } else {
192 gba->idleDetectionStep = -1;
193 }
194}
195
196static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
197 struct GBA* gba = (struct GBA*) cpu->master;
198 struct GBAMemory* memory = &gba->memory;
199
200 int newRegion = address >> BASE_OFFSET;
201 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
202 if (address == gba->idleLoop) {
203 if (gba->haltPending) {
204 gba->haltPending = false;
205 GBAHalt(gba);
206 } else {
207 gba->haltPending = true;
208 }
209 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
210 if (address == gba->lastJump) {
211 switch (gba->idleDetectionStep) {
212 case 0:
213 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
214 ++gba->idleDetectionStep;
215 break;
216 case 1:
217 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
218 gba->idleDetectionStep = -1;
219 ++gba->idleDetectionFailures;
220 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
221 gba->idleOptimization = IDLE_LOOP_IGNORE;
222 }
223 break;
224 }
225 _analyzeForIdleLoop(gba, cpu, address);
226 break;
227 }
228 } else {
229 gba->idleDetectionStep = 0;
230 }
231 }
232 }
233
234 gba->lastJump = address;
235 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
236 return;
237 }
238
239 if (memory->activeRegion == REGION_BIOS) {
240 memory->biosPrefetch = cpu->prefetch[1];
241 }
242 memory->activeRegion = newRegion;
243 switch (newRegion) {
244 case REGION_BIOS:
245 cpu->memory.activeRegion = memory->bios;
246 cpu->memory.activeMask = SIZE_BIOS - 1;
247 break;
248 case REGION_WORKING_RAM:
249 cpu->memory.activeRegion = memory->wram;
250 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
251 break;
252 case REGION_WORKING_IRAM:
253 cpu->memory.activeRegion = memory->iwram;
254 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
255 break;
256 case REGION_VRAM:
257 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
258 cpu->memory.activeMask = 0x0000FFFF;
259 break;
260 case REGION_CART0:
261 case REGION_CART0_EX:
262 case REGION_CART1:
263 case REGION_CART1_EX:
264 case REGION_CART2:
265 case REGION_CART2_EX:
266 cpu->memory.activeRegion = memory->rom;
267 cpu->memory.activeMask = SIZE_CART0 - 1;
268 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
269 break;
270 }
271 // Fall through
272 default:
273 memory->activeRegion = 0;
274 cpu->memory.activeRegion = _deadbeef;
275 cpu->memory.activeMask = 0;
276 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
277 break;
278 }
279 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
280 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
281 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
282 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
283 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
284 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
285}
286
287#define LOAD_BAD \
288 if (gba->performingDMA) { \
289 value = gba->bus; \
290 } else { \
291 value = cpu->prefetch[1]; \
292 if (cpu->executionMode == MODE_THUMB) { \
293 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
294 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
295 case REGION_BIOS: \
296 case REGION_OAM: \
297 /* This isn't right half the time, but we don't have $+6 handy */ \
298 value <<= 16; \
299 value |= cpu->prefetch[0]; \
300 break; \
301 case REGION_WORKING_IRAM: \
302 /* This doesn't handle prefetch clobbering */ \
303 if (cpu->gprs[ARM_PC] & 2) { \
304 value |= cpu->prefetch[0] << 16; \
305 } else { \
306 value <<= 16; \
307 value |= cpu->prefetch[0]; \
308 } \
309 default: \
310 value |= value << 16; \
311 } \
312 } \
313 }
314
315#define LOAD_BIOS \
316 if (address < SIZE_BIOS) { \
317 if (memory->activeRegion == REGION_BIOS) { \
318 LOAD_32(value, address, memory->bios); \
319 } else { \
320 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
321 value = memory->biosPrefetch; \
322 } \
323 } else { \
324 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
325 LOAD_BAD; \
326 }
327
328#define LOAD_WORKING_RAM \
329 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
330 wait += waitstatesRegion[REGION_WORKING_RAM];
331
332#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
333#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
334
335#define LOAD_PALETTE_RAM \
336 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
337 ++wait;
338
339#define LOAD_VRAM \
340 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
341 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
342 } else { \
343 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
344 } \
345 ++wait;
346
347#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
348
349#define LOAD_CART \
350 wait += waitstatesRegion[address >> BASE_OFFSET]; \
351 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
352 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
353 } else { \
354 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
355 value = (address >> 1) & 0xFFFF; \
356 value |= ((address + 2) >> 1) << 16; \
357 }
358
359#define LOAD_SRAM \
360 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
361 value = GBALoad8(cpu, address, 0); \
362 value |= value << 8; \
363 value |= value << 16;
364
365uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
366 struct GBA* gba = (struct GBA*) cpu->master;
367 struct GBAMemory* memory = &gba->memory;
368 uint32_t value = 0;
369 int wait = 0;
370 char* waitstatesRegion = memory->waitstatesNonseq32;
371
372 switch (address >> BASE_OFFSET) {
373 case REGION_BIOS:
374 LOAD_BIOS;
375 break;
376 case REGION_WORKING_RAM:
377 LOAD_WORKING_RAM;
378 break;
379 case REGION_WORKING_IRAM:
380 LOAD_WORKING_IRAM;
381 break;
382 case REGION_IO:
383 LOAD_IO;
384 break;
385 case REGION_PALETTE_RAM:
386 LOAD_PALETTE_RAM;
387 break;
388 case REGION_VRAM:
389 LOAD_VRAM;
390 break;
391 case REGION_OAM:
392 LOAD_OAM;
393 break;
394 case REGION_CART0:
395 case REGION_CART0_EX:
396 case REGION_CART1:
397 case REGION_CART1_EX:
398 case REGION_CART2:
399 case REGION_CART2_EX:
400 LOAD_CART;
401 break;
402 case REGION_CART_SRAM:
403 case REGION_CART_SRAM_MIRROR:
404 LOAD_SRAM;
405 break;
406 default:
407 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
408 LOAD_BAD;
409 break;
410 }
411
412 if (cycleCounter) {
413 *cycleCounter += 1 + wait;
414 }
415 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
416 int rotate = (address & 3) << 3;
417 return ROR(value, rotate);
418}
419
420uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
421 struct GBA* gba = (struct GBA*) cpu->master;
422 struct GBAMemory* memory = &gba->memory;
423 uint32_t value = 0;
424 int wait = 0;
425
426 switch (address >> BASE_OFFSET) {
427 case REGION_BIOS:
428 if (address < SIZE_BIOS) {
429 if (memory->activeRegion == REGION_BIOS) {
430 LOAD_16(value, address, memory->bios);
431 } else {
432 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
433 LOAD_16(value, address & 2, &memory->biosPrefetch);
434 }
435 } else {
436 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
437 LOAD_BAD;
438 uint32_t v2 = value;
439 LOAD_16(value, address & 2, &v2);
440 }
441 break;
442 case REGION_WORKING_RAM:
443 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
444 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
445 break;
446 case REGION_WORKING_IRAM:
447 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
448 break;
449 case REGION_IO:
450 value = GBAIORead(gba, address & (SIZE_IO - 2));
451 break;
452 case REGION_PALETTE_RAM:
453 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
454 break;
455 case REGION_VRAM:
456 if ((address & 0x0001FFFF) < SIZE_VRAM) {
457 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
458 } else {
459 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
460 }
461 break;
462 case REGION_OAM:
463 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
464 break;
465 case REGION_CART0:
466 case REGION_CART0_EX:
467 case REGION_CART1:
468 case REGION_CART1_EX:
469 case REGION_CART2:
470 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
471 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
472 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
473 } else {
474 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
475 value = (address >> 1) & 0xFFFF; \
476 }
477 break;
478 case REGION_CART2_EX:
479 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
480 if (memory->savedata.type == SAVEDATA_EEPROM) {
481 value = GBASavedataReadEEPROM(&memory->savedata);
482 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
483 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
484 } else {
485 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
486 value = (address >> 1) & 0xFFFF; \
487 }
488 break;
489 case REGION_CART_SRAM:
490 case REGION_CART_SRAM_MIRROR:
491 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
492 value = GBALoad8(cpu, address, 0);
493 value |= value << 8;
494 break;
495 default:
496 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
497 LOAD_BAD;
498 uint32_t v2 = value;
499 LOAD_16(value, address & 2, &v2);
500 break;
501 }
502
503 if (cycleCounter) {
504 *cycleCounter += 1 + wait;
505 }
506 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
507 int rotate = (address & 1) << 3;
508 return ROR(value, rotate);
509}
510
511uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
512 struct GBA* gba = (struct GBA*) cpu->master;
513 struct GBAMemory* memory = &gba->memory;
514 uint32_t value = 0;
515 int wait = 0;
516
517 switch (address >> BASE_OFFSET) {
518 case REGION_BIOS:
519 if (address < SIZE_BIOS) {
520 if (memory->activeRegion == REGION_BIOS) {
521 value = ((uint8_t*) memory->bios)[address];
522 } else {
523 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
524 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
525 }
526 } else {
527 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
528 LOAD_BAD;
529 value = ((uint8_t*) &value)[address & 3];
530 }
531 break;
532 case REGION_WORKING_RAM:
533 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
534 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
535 break;
536 case REGION_WORKING_IRAM:
537 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
538 break;
539 case REGION_IO:
540 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
541 break;
542 case REGION_PALETTE_RAM:
543 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
544 break;
545 case REGION_VRAM:
546 if ((address & 0x0001FFFF) < SIZE_VRAM) {
547 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
548 } else {
549 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
550 }
551 break;
552 case REGION_OAM:
553 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
554 break;
555 case REGION_CART0:
556 case REGION_CART0_EX:
557 case REGION_CART1:
558 case REGION_CART1_EX:
559 case REGION_CART2:
560 case REGION_CART2_EX:
561 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
562 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
563 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
564 } else {
565 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
566 value = (address >> 1) & 0xFF; \
567 }
568 break;
569 case REGION_CART_SRAM:
570 case REGION_CART_SRAM_MIRROR:
571 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
572 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
573 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
574 GBASavedataInitSRAM(&memory->savedata);
575 }
576 if (memory->savedata.type == SAVEDATA_SRAM) {
577 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
578 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
579 value = GBASavedataReadFlash(&memory->savedata, address);
580 } else if (memory->hw.devices & HW_TILT) {
581 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
582 } else {
583 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
584 value = 0xFF;
585 }
586 value &= 0xFF;
587 break;
588 default:
589 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
590 LOAD_BAD;
591 value = ((uint8_t*) &value)[address & 3];
592 break;
593 }
594
595 if (cycleCounter) {
596 *cycleCounter += 1 + wait;
597 }
598 return value;
599}
600
601#define STORE_WORKING_RAM \
602 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
603 wait += waitstatesRegion[REGION_WORKING_RAM];
604
605#define STORE_WORKING_IRAM \
606 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
607
608#define STORE_IO \
609 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
610
611#define STORE_PALETTE_RAM \
612 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
613 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
614 ++wait; \
615 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
616
617#define STORE_VRAM \
618 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
619 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
620 } else { \
621 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
622 } \
623 ++wait;
624
625#define STORE_OAM \
626 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
627 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
628 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
629
630#define STORE_CART \
631 wait += waitstatesRegion[address >> BASE_OFFSET]; \
632 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
633
634#define STORE_SRAM \
635 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
636
637#define STORE_BAD \
638 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
639
640void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
641 struct GBA* gba = (struct GBA*) cpu->master;
642 struct GBAMemory* memory = &gba->memory;
643 int wait = 0;
644 char* waitstatesRegion = memory->waitstatesNonseq32;
645
646 switch (address >> BASE_OFFSET) {
647 case REGION_WORKING_RAM:
648 STORE_WORKING_RAM;
649 break;
650 case REGION_WORKING_IRAM:
651 STORE_WORKING_IRAM
652 break;
653 case REGION_IO:
654 STORE_IO;
655 break;
656 case REGION_PALETTE_RAM:
657 STORE_PALETTE_RAM;
658 break;
659 case REGION_VRAM:
660 STORE_VRAM;
661 break;
662 case REGION_OAM:
663 STORE_OAM;
664 break;
665 case REGION_CART0:
666 case REGION_CART0_EX:
667 case REGION_CART1:
668 case REGION_CART1_EX:
669 case REGION_CART2:
670 case REGION_CART2_EX:
671 STORE_CART;
672 break;
673 case REGION_CART_SRAM:
674 case REGION_CART_SRAM_MIRROR:
675 STORE_SRAM;
676 break;
677 default:
678 STORE_BAD;
679 break;
680 }
681
682 if (cycleCounter) {
683 *cycleCounter += 1 + wait;
684 }
685}
686
687void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
688 struct GBA* gba = (struct GBA*) cpu->master;
689 struct GBAMemory* memory = &gba->memory;
690 int wait = 0;
691
692 switch (address >> BASE_OFFSET) {
693 case REGION_WORKING_RAM:
694 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
695 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
696 break;
697 case REGION_WORKING_IRAM:
698 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
699 break;
700 case REGION_IO:
701 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
702 break;
703 case REGION_PALETTE_RAM:
704 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
705 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
706 break;
707 case REGION_VRAM:
708 if ((address & 0x0001FFFF) < SIZE_VRAM) {
709 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
710 } else {
711 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
712 }
713 break;
714 case REGION_OAM:
715 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
716 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
717 break;
718 case REGION_CART0:
719 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
720 uint32_t reg = address & 0xFFFFFE;
721 GBAHardwareGPIOWrite(&memory->hw, reg, value);
722 } else {
723 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
724 }
725 break;
726 case REGION_CART2_EX:
727 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
728 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
729 GBASavedataInitEEPROM(&memory->savedata);
730 }
731 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
732 break;
733 case REGION_CART_SRAM:
734 case REGION_CART_SRAM_MIRROR:
735 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
736 break;
737 default:
738 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
739 break;
740 }
741
742 if (cycleCounter) {
743 *cycleCounter += 1 + wait;
744 }
745}
746
747void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
748 struct GBA* gba = (struct GBA*) cpu->master;
749 struct GBAMemory* memory = &gba->memory;
750 int wait = 0;
751
752 switch (address >> BASE_OFFSET) {
753 case REGION_WORKING_RAM:
754 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
755 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
756 break;
757 case REGION_WORKING_IRAM:
758 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
759 break;
760 case REGION_IO:
761 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
762 break;
763 case REGION_PALETTE_RAM:
764 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
765 break;
766 case REGION_VRAM:
767 if (address >= 0x06018000) {
768 // TODO: check BG mode
769 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
770 break;
771 }
772 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
773 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
774 break;
775 case REGION_OAM:
776 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
777 break;
778 case REGION_CART0:
779 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
780 break;
781 case REGION_CART_SRAM:
782 case REGION_CART_SRAM_MIRROR:
783 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
784 if (address == SAVEDATA_FLASH_BASE) {
785 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
786 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
787 } else {
788 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
789 GBASavedataInitSRAM(&memory->savedata);
790 }
791 }
792 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
793 GBASavedataWriteFlash(&memory->savedata, address, value);
794 } else if (memory->savedata.type == SAVEDATA_SRAM) {
795 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
796 } else if (memory->hw.devices & HW_TILT) {
797 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
798 } else {
799 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
800 }
801 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
802 break;
803 default:
804 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
805 break;
806 }
807
808 if (cycleCounter) {
809 *cycleCounter += 1 + wait;
810 }
811}
812
813void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
814 struct GBA* gba = (struct GBA*) cpu->master;
815 struct GBAMemory* memory = &gba->memory;
816 int32_t oldValue = -1;
817
818 switch (address >> BASE_OFFSET) {
819 case REGION_WORKING_RAM:
820 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
821 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
822 break;
823 case REGION_WORKING_IRAM:
824 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
825 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
826 break;
827 case REGION_IO:
828 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
829 break;
830 case REGION_PALETTE_RAM:
831 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
832 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
833 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
834 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
835 break;
836 case REGION_VRAM:
837 if ((address & 0x0001FFFF) < SIZE_VRAM) {
838 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
839 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
840 } else {
841 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
842 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
843 }
844 break;
845 case REGION_OAM:
846 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
847 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
848 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
849 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
850 break;
851 case REGION_CART0:
852 case REGION_CART0_EX:
853 case REGION_CART1:
854 case REGION_CART1_EX:
855 case REGION_CART2:
856 case REGION_CART2_EX:
857 _pristineCow(gba);
858 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
859 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
860 }
861 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
862 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
863 break;
864 case REGION_CART_SRAM:
865 case REGION_CART_SRAM_MIRROR:
866 if (memory->savedata.type == SAVEDATA_SRAM) {
867 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
868 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
869 } else {
870 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
871 }
872 break;
873 default:
874 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
875 break;
876 }
877 if (old) {
878 *old = oldValue;
879 }
880}
881
882void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
883 struct GBA* gba = (struct GBA*) cpu->master;
884 struct GBAMemory* memory = &gba->memory;
885 int16_t oldValue = -1;
886
887 switch (address >> BASE_OFFSET) {
888 case REGION_WORKING_RAM:
889 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
890 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
891 break;
892 case REGION_WORKING_IRAM:
893 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
894 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
895 break;
896 case REGION_IO:
897 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
898 break;
899 case REGION_PALETTE_RAM:
900 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
901 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
902 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
903 break;
904 case REGION_VRAM:
905 if ((address & 0x0001FFFF) < SIZE_VRAM) {
906 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
907 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
908 } else {
909 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
910 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
911 }
912 break;
913 case REGION_OAM:
914 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
915 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
916 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
917 break;
918 case REGION_CART0:
919 case REGION_CART0_EX:
920 case REGION_CART1:
921 case REGION_CART1_EX:
922 case REGION_CART2:
923 case REGION_CART2_EX:
924 _pristineCow(gba);
925 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
926 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
927 }
928 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
929 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
930 break;
931 case REGION_CART_SRAM:
932 case REGION_CART_SRAM_MIRROR:
933 if (memory->savedata.type == SAVEDATA_SRAM) {
934 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
935 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
936 } else {
937 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
938 }
939 break;
940 default:
941 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
942 break;
943 }
944 if (old) {
945 *old = oldValue;
946 }
947}
948
949void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
950 struct GBA* gba = (struct GBA*) cpu->master;
951 struct GBAMemory* memory = &gba->memory;
952 int8_t oldValue = -1;
953
954 switch (address >> BASE_OFFSET) {
955 case REGION_WORKING_RAM:
956 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
957 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
958 break;
959 case REGION_WORKING_IRAM:
960 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
961 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
962 break;
963 case REGION_IO:
964 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
965 break;
966 case REGION_PALETTE_RAM:
967 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
968 break;
969 case REGION_VRAM:
970 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
971 break;
972 case REGION_OAM:
973 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
974 break;
975 case REGION_CART0:
976 case REGION_CART0_EX:
977 case REGION_CART1:
978 case REGION_CART1_EX:
979 case REGION_CART2:
980 case REGION_CART2_EX:
981 _pristineCow(gba);
982 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
983 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
984 }
985 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
986 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
987 break;
988 case REGION_CART_SRAM:
989 case REGION_CART_SRAM_MIRROR:
990 if (memory->savedata.type == SAVEDATA_SRAM) {
991 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
992 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
993 } else {
994 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
995 }
996 break;
997 default:
998 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
999 break;
1000 }
1001 if (old) {
1002 *old = oldValue;
1003 }
1004}
1005
1006#define LDM_LOOP(LDM) \
1007 for (i = 0; i < 16; i += 4) { \
1008 if (UNLIKELY(mask & (1 << i))) { \
1009 LDM; \
1010 waitstatesRegion = memory->waitstatesSeq32; \
1011 cpu->gprs[i] = value; \
1012 ++wait; \
1013 address += 4; \
1014 } \
1015 if (UNLIKELY(mask & (2 << i))) { \
1016 LDM; \
1017 waitstatesRegion = memory->waitstatesSeq32; \
1018 cpu->gprs[i + 1] = value; \
1019 ++wait; \
1020 address += 4; \
1021 } \
1022 if (UNLIKELY(mask & (4 << i))) { \
1023 LDM; \
1024 waitstatesRegion = memory->waitstatesSeq32; \
1025 cpu->gprs[i + 2] = value; \
1026 ++wait; \
1027 address += 4; \
1028 } \
1029 if (UNLIKELY(mask & (8 << i))) { \
1030 LDM; \
1031 waitstatesRegion = memory->waitstatesSeq32; \
1032 cpu->gprs[i + 3] = value; \
1033 ++wait; \
1034 address += 4; \
1035 } \
1036 }
1037
1038uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1039 struct GBA* gba = (struct GBA*) cpu->master;
1040 struct GBAMemory* memory = &gba->memory;
1041 uint32_t value;
1042 int wait = 0;
1043 char* waitstatesRegion = memory->waitstatesNonseq32;
1044
1045 int i;
1046 int offset = 4;
1047 int popcount = 0;
1048 if (direction & LSM_D) {
1049 offset = -4;
1050 popcount = _popcount32(mask);
1051 address -= (popcount << 2) - 4;
1052 }
1053
1054 if (direction & LSM_B) {
1055 address += offset;
1056 }
1057
1058 uint32_t addressMisalign = address & 0x3;
1059 address &= 0xFFFFFFFC;
1060
1061 switch (address >> BASE_OFFSET) {
1062 case REGION_BIOS:
1063 LDM_LOOP(LOAD_BIOS);
1064 break;
1065 case REGION_WORKING_RAM:
1066 LDM_LOOP(LOAD_WORKING_RAM);
1067 break;
1068 case REGION_WORKING_IRAM:
1069 LDM_LOOP(LOAD_WORKING_IRAM);
1070 break;
1071 case REGION_IO:
1072 LDM_LOOP(LOAD_IO);
1073 break;
1074 case REGION_PALETTE_RAM:
1075 LDM_LOOP(LOAD_PALETTE_RAM);
1076 break;
1077 case REGION_VRAM:
1078 LDM_LOOP(LOAD_VRAM);
1079 break;
1080 case REGION_OAM:
1081 LDM_LOOP(LOAD_OAM);
1082 break;
1083 case REGION_CART0:
1084 case REGION_CART0_EX:
1085 case REGION_CART1:
1086 case REGION_CART1_EX:
1087 case REGION_CART2:
1088 case REGION_CART2_EX:
1089 LDM_LOOP(LOAD_CART);
1090 break;
1091 case REGION_CART_SRAM:
1092 case REGION_CART_SRAM_MIRROR:
1093 LDM_LOOP(LOAD_SRAM);
1094 break;
1095 default:
1096 LDM_LOOP(LOAD_BAD);
1097 break;
1098 }
1099
1100 if (cycleCounter) {
1101 *cycleCounter += wait;
1102 }
1103
1104 if (direction & LSM_B) {
1105 address -= offset;
1106 }
1107
1108 if (direction & LSM_D) {
1109 address -= (popcount << 2) + 4;
1110 }
1111
1112 return address | addressMisalign;
1113}
1114
1115#define STM_LOOP(STM) \
1116 for (i = 0; i < 16; i += 4) { \
1117 if (UNLIKELY(mask & (1 << i))) { \
1118 value = cpu->gprs[i]; \
1119 STM; \
1120 waitstatesRegion = memory->waitstatesSeq32; \
1121 ++wait; \
1122 address += 4; \
1123 } \
1124 if (UNLIKELY(mask & (2 << i))) { \
1125 value = cpu->gprs[i + 1]; \
1126 STM; \
1127 waitstatesRegion = memory->waitstatesSeq32; \
1128 ++wait; \
1129 address += 4; \
1130 } \
1131 if (UNLIKELY(mask & (4 << i))) { \
1132 value = cpu->gprs[i + 2]; \
1133 STM; \
1134 waitstatesRegion = memory->waitstatesSeq32; \
1135 ++wait; \
1136 address += 4; \
1137 } \
1138 if (UNLIKELY(mask & (8 << i))) { \
1139 value = cpu->gprs[i + 3]; \
1140 STM; \
1141 waitstatesRegion = memory->waitstatesSeq32; \
1142 ++wait; \
1143 address += 4; \
1144 } \
1145 }
1146
1147uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1148 struct GBA* gba = (struct GBA*) cpu->master;
1149 struct GBAMemory* memory = &gba->memory;
1150 uint32_t value;
1151 int wait = 0;
1152 char* waitstatesRegion = memory->waitstatesNonseq32;
1153
1154 int i;
1155 int offset = 4;
1156 int popcount = 0;
1157 if (direction & LSM_D) {
1158 offset = -4;
1159 popcount = _popcount32(mask);
1160 address -= (popcount << 2) - 4;
1161 }
1162
1163 if (direction & LSM_B) {
1164 address += offset;
1165 }
1166
1167 uint32_t addressMisalign = address & 0x3;
1168 address &= 0xFFFFFFFC;
1169
1170 switch (address >> BASE_OFFSET) {
1171 case REGION_WORKING_RAM:
1172 STM_LOOP(STORE_WORKING_RAM);
1173 break;
1174 case REGION_WORKING_IRAM:
1175 STM_LOOP(STORE_WORKING_IRAM);
1176 break;
1177 case REGION_IO:
1178 STM_LOOP(STORE_IO);
1179 break;
1180 case REGION_PALETTE_RAM:
1181 STM_LOOP(STORE_PALETTE_RAM);
1182 break;
1183 case REGION_VRAM:
1184 STM_LOOP(STORE_VRAM);
1185 break;
1186 case REGION_OAM:
1187 STM_LOOP(STORE_OAM);
1188 break;
1189 case REGION_CART0:
1190 case REGION_CART0_EX:
1191 case REGION_CART1:
1192 case REGION_CART1_EX:
1193 case REGION_CART2:
1194 case REGION_CART2_EX:
1195 STM_LOOP(STORE_CART);
1196 break;
1197 case REGION_CART_SRAM:
1198 case REGION_CART_SRAM_MIRROR:
1199 STM_LOOP(STORE_SRAM);
1200 break;
1201 default:
1202 STM_LOOP(STORE_BAD);
1203 break;
1204 }
1205
1206 if (cycleCounter) {
1207 *cycleCounter += wait;
1208 }
1209
1210 if (direction & LSM_B) {
1211 address -= offset;
1212 }
1213
1214 if (direction & LSM_D) {
1215 address -= (popcount << 2) + 4;
1216 }
1217
1218 return address | addressMisalign;
1219}
1220
1221void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1222 struct GBAMemory* memory = &gba->memory;
1223 struct ARMCore* cpu = gba->cpu;
1224 int sram = parameters & 0x0003;
1225 int ws0 = (parameters & 0x000C) >> 2;
1226 int ws0seq = (parameters & 0x0010) >> 4;
1227 int ws1 = (parameters & 0x0060) >> 5;
1228 int ws1seq = (parameters & 0x0080) >> 7;
1229 int ws2 = (parameters & 0x0300) >> 8;
1230 int ws2seq = (parameters & 0x0400) >> 10;
1231 int prefetch = parameters & 0x4000;
1232
1233 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1234 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1235 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1236 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1237
1238 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1239 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1240 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1241
1242 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1243 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1244 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1245
1246 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1247 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1248 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1249
1250 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1251 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1252 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1253
1254 if (!prefetch) {
1255 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1256 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1257 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1258
1259 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1260 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1261 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1262
1263 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1264 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1265 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1266
1267 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1268 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1269 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1270 } else {
1271 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1272 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1273 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1274
1275 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1276 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1277 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1278
1279 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1280 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1281 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1282
1283 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1284 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1285 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1286 }
1287
1288 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1289 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1290
1291 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1292 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1293
1294 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1295 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1296}
1297
1298void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1299 struct GBAMemory* memory = &gba->memory;
1300 memory->dma[dma].source = address & 0x0FFFFFFE;
1301}
1302
1303void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1304 struct GBAMemory* memory = &gba->memory;
1305 memory->dma[dma].dest = address & 0x0FFFFFFE;
1306}
1307
1308void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1309 struct GBAMemory* memory = &gba->memory;
1310 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1311}
1312
1313uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1314 struct GBAMemory* memory = &gba->memory;
1315 struct GBADMA* currentDma = &memory->dma[dma];
1316 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1317 currentDma->reg = control;
1318
1319 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1320 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1321 }
1322
1323 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1324 currentDma->nextSource = currentDma->source;
1325 currentDma->nextDest = currentDma->dest;
1326 currentDma->nextCount = currentDma->count;
1327 GBAMemoryScheduleDMA(gba, dma, currentDma);
1328 }
1329 // If the DMA has already occurred, this value might have changed since the function started
1330 return currentDma->reg;
1331};
1332
1333void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1334 struct ARMCore* cpu = gba->cpu;
1335 switch (GBADMARegisterGetTiming(info->reg)) {
1336 case DMA_TIMING_NOW:
1337 info->nextEvent = cpu->cycles;
1338 GBAMemoryUpdateDMAs(gba, 0);
1339 break;
1340 case DMA_TIMING_HBLANK:
1341 // Handled implicitly
1342 info->nextEvent = INT_MAX;
1343 break;
1344 case DMA_TIMING_VBLANK:
1345 // Handled implicitly
1346 info->nextEvent = INT_MAX;
1347 break;
1348 case DMA_TIMING_CUSTOM:
1349 info->nextEvent = INT_MAX;
1350 switch (number) {
1351 case 0:
1352 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1353 break;
1354 case 1:
1355 case 2:
1356 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1357 break;
1358 case 3:
1359 // GBAVideoScheduleVCaptureDma(dma, info);
1360 break;
1361 }
1362 }
1363}
1364
1365void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1366 struct GBAMemory* memory = &gba->memory;
1367 struct GBADMA* dma;
1368 int i;
1369 for (i = 0; i < 4; ++i) {
1370 dma = &memory->dma[i];
1371 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1372 dma->nextEvent = cycles;
1373 }
1374 }
1375 GBAMemoryUpdateDMAs(gba, 0);
1376}
1377
1378void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1379 struct GBAMemory* memory = &gba->memory;
1380 struct GBADMA* dma;
1381 int i;
1382 for (i = 0; i < 4; ++i) {
1383 dma = &memory->dma[i];
1384 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1385 dma->nextEvent = cycles;
1386 }
1387 }
1388 GBAMemoryUpdateDMAs(gba, 0);
1389}
1390
1391int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1392 struct GBAMemory* memory = &gba->memory;
1393 if (memory->nextDMA == INT_MAX) {
1394 return INT_MAX;
1395 }
1396 memory->nextDMA -= cycles;
1397 memory->eventDiff += cycles;
1398 if (memory->nextDMA <= 0) {
1399 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1400 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1401 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1402 memory->eventDiff = 0;
1403 }
1404 return memory->nextDMA;
1405}
1406
1407void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1408 int i;
1409 struct GBAMemory* memory = &gba->memory;
1410 struct ARMCore* cpu = gba->cpu;
1411 memory->activeDMA = -1;
1412 memory->nextDMA = INT_MAX;
1413 for (i = 3; i >= 0; --i) {
1414 struct GBADMA* dma = &memory->dma[i];
1415 if (dma->nextEvent != INT_MAX) {
1416 dma->nextEvent -= cycles;
1417 if (GBADMARegisterIsEnable(dma->reg)) {
1418 memory->activeDMA = i;
1419 memory->nextDMA = dma->nextEvent;
1420 }
1421 }
1422 }
1423 if (memory->nextDMA < cpu->nextEvent) {
1424 cpu->nextEvent = memory->nextDMA;
1425 }
1426}
1427
1428void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1429 struct GBAMemory* memory = &gba->memory;
1430 struct ARMCore* cpu = gba->cpu;
1431 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1432 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1433 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1434 int32_t wordsRemaining = info->nextCount;
1435 uint32_t source = info->nextSource;
1436 uint32_t dest = info->nextDest;
1437 uint32_t sourceRegion = source >> BASE_OFFSET;
1438 uint32_t destRegion = dest >> BASE_OFFSET;
1439 int32_t cycles = 2;
1440
1441 if (source == info->source) {
1442 // TODO: support 4 cycles for ROM access
1443 cycles += 2;
1444 if (width == 4) {
1445 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1446 source &= 0xFFFFFFFC;
1447 dest &= 0xFFFFFFFC;
1448 } else {
1449 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1450 }
1451 } else {
1452 if (width == 4) {
1453 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1454 } else {
1455 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1456 }
1457 }
1458
1459 gba->performingDMA = true;
1460 int32_t word;
1461 if (width == 4) {
1462 word = cpu->memory.load32(cpu, source, 0);
1463 gba->bus = word;
1464 cpu->memory.store32(cpu, dest, word, 0);
1465 source += sourceOffset;
1466 dest += destOffset;
1467 --wordsRemaining;
1468 } else {
1469 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1470 word = GBASavedataReadEEPROM(&memory->savedata);
1471 gba->bus = word | (word << 16);
1472 cpu->memory.store16(cpu, dest, word, 0);
1473 source += sourceOffset;
1474 dest += destOffset;
1475 --wordsRemaining;
1476 } else if (destRegion == REGION_CART2_EX) {
1477 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1478 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1479 GBASavedataInitEEPROM(&memory->savedata);
1480 }
1481 word = cpu->memory.load16(cpu, source, 0);
1482 gba->bus = word | (word << 16);
1483 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1484 source += sourceOffset;
1485 dest += destOffset;
1486 --wordsRemaining;
1487 } else {
1488 word = cpu->memory.load16(cpu, source, 0);
1489 gba->bus = word | (word << 16);
1490 cpu->memory.store16(cpu, dest, word, 0);
1491 source += sourceOffset;
1492 dest += destOffset;
1493 --wordsRemaining;
1494 }
1495 }
1496 gba->performingDMA = false;
1497
1498 if (!wordsRemaining) {
1499 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1500 info->reg = GBADMARegisterClearEnable(info->reg);
1501 info->nextEvent = INT_MAX;
1502
1503 // Clear the enable bit in memory
1504 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1505 } else {
1506 info->nextCount = info->count;
1507 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1508 info->nextDest = info->dest;
1509 }
1510 GBAMemoryScheduleDMA(gba, number, info);
1511 }
1512 if (GBADMARegisterIsDoIRQ(info->reg)) {
1513 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1514 }
1515 } else {
1516 info->nextDest = dest;
1517 info->nextCount = wordsRemaining;
1518 }
1519 info->nextSource = source;
1520
1521 if (info->nextEvent != INT_MAX) {
1522 info->nextEvent += cycles;
1523 }
1524 cpu->cycles += cycles;
1525}
1526
1527void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1528 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1529 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1530}
1531
1532void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1533 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1534 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1535}
1536
1537uint32_t _popcount32(unsigned bits) {
1538 bits = bits - ((bits >> 1) & 0x55555555);
1539 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1540 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1541}
1542
1543void _pristineCow(struct GBA* gba) {
1544 if (gba->memory.rom != gba->pristineRom) {
1545 return;
1546 }
1547 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1548 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1549 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1550}