include/mgba/internal/arm/emitter-arm.h (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef EMITTER_ARM_H
7#define EMITTER_ARM_H
8
9#include "emitter-inlines.h"
10
11#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
12 EMITTER ## NAME
13
14#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
15 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
16 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
17
18#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
19 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
20 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
21 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
22 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
23 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
24 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
25 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
26 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
27 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
28 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
29 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
30 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
31 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
32 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
33 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
34 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
35
36#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
37 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
38 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
39
40#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
41 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5)), \
42 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## I ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W), V >= 5))
43
44#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
45 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
46 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
47 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
48 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
49 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
50 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
51 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
52 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
53 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
54 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
55 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
56 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
57 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
58 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
59 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
60 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
61
62#define DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, NAME, P, U, W, V) \
63 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
64 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
65 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
66 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
67 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
68 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
69 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
70 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
71 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSL_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), V >= 5), \
72 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
73 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_LSR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), V >= 5), \
74 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
75 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ASR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), V >= 5), \
76 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
77 MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5_ROR_ ## P ## U ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), V >= 5), \
78 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
79
80#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
81 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
82 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
83
84#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, NAME, MODE, W, V) \
85 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5)), \
86 DO_8(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## v5 ## MODE ## W), DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W), V >= 5))
87
88#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
89 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
90
91// TODO: Support coprocessors
92#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
93 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
94 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
95
96#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2, NAME3) \
97 DO_8(DO_INTERLACE( \
98 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))), \
99 DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME3)))))
100
101#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
102 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
103
104#define DECLARE_ARM_EMITTER_BLOCK(EMITTER, V) \
105 /* -00---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
106 /* -01---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
107 /* -02---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \
108 /* -03---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \
109 /* -04---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
110 /* -05---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
111 /* -06---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \
112 /* -07---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \
113 /* -08---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
114 /* -09---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
115 /* -0A---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \
116 /* -0B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \
117 /* -0C---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
118 /* -0D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
119 /* -0E---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \
120 /* -0F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \
121 /* -10---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
122 /* -10---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
123 /* -10---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
124 /* -10---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
125 /* -10---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
126 /* -10---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
127 /* -10---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
128 /* -10---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
129 /* -10---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
130 /* -10---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
131 /* -10---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
132 /* -10---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
133 /* -10---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLABT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
134 /* -10---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
135 /* -10---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLATT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
136 /* -10---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
137 /* -11---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
138 /* -12---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
139 /* -12---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
140 /* -12---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
141 /* -12---3- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX2), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
142 /* -12---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
143 /* -12---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
144 /* -12---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
145 /* -12---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
146 /* -12---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
147 /* -12---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
148 /* -12---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
149 /* -12---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
150 /* -12---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMLAWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
151 /* -12---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
152 /* -12---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULWT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
153 /* -12---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
154 /* -13---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
155 /* -14---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
156 /* -14---1- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
157 /* -14---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
158 /* -14---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
159 /* -14---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
160 /* -14---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
161 /* -14---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
162 /* -14---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
163 /* -14---8- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
164 /* -14---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
165 /* -14---A- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
166 /* -14---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
167 /* -14---C- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
168 /* -14---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
169 /* -14---E- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
170 /* -14---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
171 /* -15---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
172 /* -16---0- */ DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
173 /* -16---1- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, CLZ), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
174 /* -16---2- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
175 /* -16---3- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
176 /* -16---4- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
177 /* -16---5- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
178 /* -16---6- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
179 /* -16---7- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
180 /* -16---8- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
181 /* -16---9- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
182 /* -16---A- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTB), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
183 /* -16---B- */ DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
184 /* -16---C- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULBT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
185 /* -16---D- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
186 /* -16---E- */ MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, SMULTT), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5), \
187 /* -16---F- */ DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
188 /* -17---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
189 /* -18---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
190 /* -19---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
191 /* -1A---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
192 /* -1B---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
193 /* -1C---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
194 /* -1D---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
195 /* -1E---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
196 /* -1F---X- */ DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
197 /* -20---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
198 /* -21---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
199 /* -22---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
200 /* -23---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
201 /* -24---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
202 /* -25---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
203 /* -26---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
204 /* -27---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
205 /* -28---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
206 /* -29---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
207 /* -2A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
208 /* -2B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
209 /* -2C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
210 /* -2D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
211 /* -2E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
212 /* -2F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
213 /* -30---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
214 /* -31---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
215 /* -32---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
216 /* -33---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
217 /* -34---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
218 /* -35---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
219 /* -36---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
220 /* -37---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
221 /* -38---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
222 /* -39---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
223 /* -3A---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
224 /* -3B---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
225 /* -3C---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
226 /* -3D---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
227 /* -3E---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
228 /* -3F---X- */ DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
229 /* -40---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
230 /* -41---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , , , V), \
231 /* -42---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
232 /* -43---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
233 /* -44---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
234 /* -45---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
235 /* -46---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
236 /* -47---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
237 /* -48---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
238 /* -49---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, , U, , V), \
239 /* -4A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
240 /* -4B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
241 /* -4C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
242 /* -4D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
243 /* -4E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
244 /* -4F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
245 /* -50---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
246 /* -51---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , , V), \
247 /* -52---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
248 /* -53---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, , W, V), \
249 /* -54---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
250 /* -55---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
251 /* -56---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
252 /* -57---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
253 /* -58---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
254 /* -59---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, , V), \
255 /* -5A---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
256 /* -5B---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
257 /* -5C---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
258 /* -5D---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
259 /* -5E---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
260 /* -5F---X- */ DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
261 /* -60---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
262 /* -61---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , , , V), \
263 /* -62---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
264 /* -63---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
265 /* -64---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
266 /* -65---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
267 /* -66---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
268 /* -67---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
269 /* -68---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
270 /* -69---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, , U, , V), \
271 /* -6A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
272 /* -6B---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
273 /* -6C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
274 /* -6D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
275 /* -6E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
276 /* -6F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
277 /* -70---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
278 /* -71---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , , V), \
279 /* -72---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
280 /* -73---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, , W, V), \
281 /* -74---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
282 /* -75---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
283 /* -76---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
284 /* -77---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
285 /* -78---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
286 /* -79---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, , V), \
287 /* -7A---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
288 /* -7B---X- */ DECLARE_ARM_LOAD_STORE_BLOCKv5(EMITTER, LDR, P, U, W, V), \
289 /* -7C---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
290 /* -7D---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
291 /* -7E---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
292 /* -7F---X- */ DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
293 /* -80---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
294 /* -81---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, , V), \
295 /* -82---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
296 /* -83---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DA, W, V), \
297 /* -84---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
298 /* -85---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
299 /* -86---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
300 /* -87---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
301 /* -88---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
302 /* -89---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, , V), \
303 /* -8A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
304 /* -8B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IA, W, V), \
305 /* -8C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
306 /* -8D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
307 /* -8E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
308 /* -8F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
309 /* -90---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
310 /* -91---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, , V), \
311 /* -92---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
312 /* -93---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, DB, W, V), \
313 /* -94---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
314 /* -95---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
315 /* -96---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
316 /* -97---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
317 /* -98---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
318 /* -99---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, , V), \
319 /* -9A---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
320 /* -9B---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCKv5(EMITTER, LDM, IB, W, V), \
321 /* -9C---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
322 /* -9D---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
323 /* -9E---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
324 /* -9F---X- */ DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
325 /* -AX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
326 /* -BX---X- */ DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
327 /* -C0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
328 /* -C1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
329 /* -C2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
330 /* -C3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
331 /* -C4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
332 /* -C5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
333 /* -C6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
334 /* -C7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
335 /* -C8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
336 /* -C9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
337 /* -CA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
338 /* -CB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
339 /* -CC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
340 /* -CD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
341 /* -CE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
342 /* -CF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
343 /* -D0---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
344 /* -D1---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
345 /* -D2---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
346 /* -D3---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
347 /* -D4---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
348 /* -D5---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
349 /* -D6---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
350 /* -D7---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
351 /* -D8---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
352 /* -D9---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
353 /* -DA---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
354 /* -DB---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
355 /* -DC---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
356 /* -DD---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
357 /* -DE---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
358 /* -DF---X- */ DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
359 /* -EX---X- */ DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \
360 /* -RX---X- */ DECLARE_ARM_SWI_BLOCK(EMITTER)
361
362#define DECLARE_ARM_F_EMITTER_BLOCK(EMITTER, V) \
363 /* F0X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
364 /* F1X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
365 /* F2X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
366 /* F3X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
367 /* F4X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
368 /* F5X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
369 /* F6X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
370 /* F7X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
371 /* F8X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
372 /* F9X---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
373 /* FAX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
374 /* FBX---X- */ DO_256(MIN_V(DECLARE_INSTRUCTION_ARM(EMITTER, BLX), DECLARE_INSTRUCTION_ARM(EMITTER, ILL), V >= 5)), \
375 /* FCX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
376 /* FDX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
377 /* FEX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)), \
378 /* FFX---X- */ DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, ILL)),
379
380#endif