src/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _barrelShift(struct ARMCore* cpu, uint32_t opcode) {
14 // TODO
15}
16
17static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
18 int rotate = (opcode & 0x00000F00) >> 7;
19 int immediate = opcode & 0x000000FF;
20 if (!rotate) {
21 cpu->shifterOperand = immediate;
22 cpu->shifterCarryOut = cpu->cpsr.c;
23 } else {
24 cpu->shifterOperand = ARM_ROR(immediate, rotate);
25 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
26 }
27}
28
29static const ARMInstruction _armTable[0x1000];
30
31static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
32 uint32_t opcode = memory->load32(memory, address);
33 *opcodeOut = opcode;
34 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
35}
36
37void ARMStep(struct ARMCore* cpu) {
38 // TODO
39 uint32_t opcode;
40 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
41 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
42
43 int condition = opcode >> 28;
44 if (condition == 0xE) {
45 instruction(cpu, opcode);
46 return;
47 } else {
48 switch (condition) {
49 case 0x0:
50 if (!ARM_COND_EQ) {
51 return;
52 }
53 break;
54 case 0x1:
55 if (!ARM_COND_NE) {
56 return;
57 }
58 break;
59 case 0x2:
60 if (!ARM_COND_CS) {
61 return;
62 }
63 break;
64 case 0x3:
65 if (!ARM_COND_CC) {
66 return;
67 }
68 break;
69 case 0x4:
70 if (!ARM_COND_MI) {
71 return;
72 }
73 break;
74 case 0x5:
75 if (!ARM_COND_PL) {
76 return;
77 }
78 break;
79 case 0x6:
80 if (!ARM_COND_VS) {
81 return;
82 }
83 break;
84 case 0x7:
85 if (!ARM_COND_VC) {
86 return;
87 }
88 break;
89 case 0x8:
90 if (!ARM_COND_HI) {
91 return;
92 }
93 break;
94 case 0x9:
95 if (!ARM_COND_LS) {
96 return;
97 }
98 break;
99 case 0xA:
100 if (!ARM_COND_GE) {
101 return;
102 }
103 break;
104 case 0xB:
105 if (!ARM_COND_LT) {
106 return;
107 }
108 break;
109 case 0xC:
110 if (!ARM_COND_GT) {
111 return;
112 }
113 break;
114 case 0xD:
115 if (!ARM_COND_GE) {
116 return;
117 }
118 break;
119 default:
120 break;
121 }
122 }
123 instruction(cpu, opcode);
124}
125
126// Instruction definitions
127// Beware pre-processor antics
128
129#define ARM_WRITE_PC \
130 cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM
131
132#define ARM_ADDITION_S(M, N, D) \
133 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
134 cpu->cpsr = cpu->spsr; \
135 _ARMReadCPSR(cpu); \
136 } else { \
137 cpu->cpsr.n = ARM_SIGN(D); \
138 cpu->cpsr.z = !(D); \
139 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
140 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
141 }
142
143#define ARM_SUBTRACTION_S(M, N, D) \
144 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
145 cpu->cpsr = cpu->spsr; \
146 _ARMReadCPSR(cpu); \
147 } else { \
148 cpu->cpsr.n = ARM_SIGN(D); \
149 cpu->cpsr.z = !(D); \
150 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
151 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
152 }
153
154#define ARM_NEUTRAL_S(M, N, D) \
155 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
156 cpu->cpsr = cpu->spsr; \
157 _ARMReadCPSR(cpu); \
158 } else { \
159 cpu->cpsr.n = ARM_SIGN(D); \
160 cpu->cpsr.z = !(D); \
161 cpu->cpsr.c = cpu->shifterCarryOut; \
162 }
163
164#define ADDR_MODE_2_ADDRESS (address)
165#define ADDR_MODE_2_RN (cpu->gprs[rn])
166#define ADDR_MODE_2_RM (cpu->gprs[rm])
167#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
168#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
169#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
170#define ADDR_MODE_2_LSL(I) (cpu->gprs[rm] << I)
171#define ADDR_MODE_2_LSR(I) (I ? ((uint32_t) cpu->gprs[rm]) >> I : 0)
172#define ADDR_MODE_2_ASR(I) (I ? ((int32_t) cpu->gprs[rm]) >> I : ((int32_t) cpu->gprs[rm]) >> 31)
173#define ADDR_MODE_2_ROR(I) (I ? ARM_ROR(cpu->gprs[rm], I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
174
175#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
176#define ADDR_MODE_3_RN ADDR_MODE_2_RN
177#define ADDR_MODE_3_RM ADDR_MODE_2_RM
178#define ADDR_MODE_3_IMMEDIATE ADDR_MODE_2_IMMEDIATE
179#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
180#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
181
182#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
183 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
184 BODY; \
185 }
186
187#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY, POST_BODY) \
188 DEFINE_INSTRUCTION_ARM(NAME, \
189 int rd = (opcode >> 12) & 0xF; \
190 int rn = (opcode >> 16) & 0xF; \
191 SHIFTER(cpu, opcode); \
192 BODY; \
193 S_BODY; \
194 POST_BODY; \
195 if (rd == ARM_PC) { \
196 ARM_WRITE_PC; \
197 })
198
199#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY, POST_BODY) \
200 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, , _barrelShift, BODY, POST_BODY) \
201 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S, S_BODY, _barrelShift, BODY, POST_BODY) \
202 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
203 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
204
205#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
206 DEFINE_INSTRUCTION_ARM(NAME, \
207 uint32_t address; \
208 int rn = (opcode >> 16) & 0xF; \
209 int rd = (opcode >> 12) & 0xF; \
210 int rm = opcode & 0xF; \
211 address = ADDRESS; \
212 BODY; \
213 WRITEBACK;)
214
215#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
216 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
217 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
218 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
219 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
220 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
221 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
222
223
224#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
225 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
226 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
227 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
228 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
229 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
230 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
231 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
232 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
233 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
234 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
235
236#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
237 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
238 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
239 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
240 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
241 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
242 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
243 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
244 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
245 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
246 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
247 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
248 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
249
250// TODO
251#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
252 DEFINE_INSTRUCTION_ARM(NAME, \
253 BODY;)
254
255#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
256 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
257 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DAW, , , BODY) \
258 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , , BODY) \
259 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DBW, , , BODY) \
260 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , , BODY) \
261 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IAW, , , BODY) \
262 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , , BODY) \
263 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IBW, , , BODY) \
264 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, S_PRE, S_POST, BODY) \
265 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DAW, S_PRE, S_POST, BODY) \
266 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, S_PRE, S_POST, BODY) \
267 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DBW, S_PRE, S_POST, BODY) \
268 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, S_PRE, S_POST, BODY) \
269 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IAW, S_PRE, S_POST, BODY) \
270 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, S_PRE, S_POST, BODY) \
271 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IBW, S_PRE, S_POST, BODY)
272
273// Begin ALU definitions
274
275DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
276 cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
277
278DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
279 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
280 cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
281
282DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
283 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
284
285DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
286 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
287
288DEFINE_ALU_INSTRUCTION_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
289 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
290
291DEFINE_ALU_INSTRUCTION_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
292 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
293
294DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
295 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
296
297DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
298 cpu->gprs[rd] = cpu->shifterOperand;, )
299
300DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
301 cpu->gprs[rd] = ~cpu->shifterOperand;, )
302
303DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
304 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
305
306DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
307 int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
308
309DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
310 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
311 int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
312
313DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
314 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
315 int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
316
317DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
318 int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
319
320DEFINE_ALU_INSTRUCTION_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
321 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
322
323DEFINE_ALU_INSTRUCTION_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
324 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
325
326// End ALU definitions
327
328// Begin multiply definitions
329
330DEFINE_INSTRUCTION_ARM(MLA,)
331DEFINE_INSTRUCTION_ARM(MLAS,)
332DEFINE_INSTRUCTION_ARM(MUL,)
333DEFINE_INSTRUCTION_ARM(MULS,)
334DEFINE_INSTRUCTION_ARM(SMLAL,)
335DEFINE_INSTRUCTION_ARM(SMLALS,)
336DEFINE_INSTRUCTION_ARM(SMULL,)
337DEFINE_INSTRUCTION_ARM(SMULLS,)
338DEFINE_INSTRUCTION_ARM(UMLAL,)
339DEFINE_INSTRUCTION_ARM(UMLALS,)
340DEFINE_INSTRUCTION_ARM(UMULL,)
341DEFINE_INSTRUCTION_ARM(UMULLS,)
342
343// End multiply definitions
344
345// Begin load/store definitions
346
347DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
348DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
349DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRBT,)
350DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
351DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
352DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
353DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRT,)
354DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
355DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
356DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRBT,)
357DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
358DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRT,)
359
360DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,)
361DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,)
362
363DEFINE_INSTRUCTION_ARM(SWP,)
364DEFINE_INSTRUCTION_ARM(SWPB,)
365
366// End load/store definitions
367
368// Begin branch definitions
369
370DEFINE_INSTRUCTION_ARM(B, \
371 int32_t offset = opcode << 8; \
372 offset >>= 6; \
373 cpu->gprs[ARM_PC] += offset; \
374 ARM_WRITE_PC;)
375
376DEFINE_INSTRUCTION_ARM(BL,)
377DEFINE_INSTRUCTION_ARM(BX,)
378
379// End branch definitions
380
381// TODO
382DEFINE_INSTRUCTION_ARM(ILL,) // Illegal opcode
383
384DEFINE_INSTRUCTION_ARM(MSR, \
385 int c = opcode & 0x00010000; \
386 int f = opcode & 0x00080000; \
387 int32_t operand; \
388 if (opcode & 0x02000000) { \
389 int rotate = (opcode & 0x00000F00) >> 8; \
390 operand = ARM_ROR(opcode & 0x000000FF, rotate); \
391 } else { \
392 operand = cpu->gprs[opcode & 0x0000000F]; \
393 } \
394 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \
395 if (opcode & 0x00400000) { \
396 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \
397 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \
398 } else { \
399 if (mask & PSR_USER_MASK) { \
400 cpu->cpsr.n = operand & 0x80000000; \
401 cpu->cpsr.z = operand & 0x40000000; \
402 cpu->cpsr.c = operand & 0x20000000; \
403 cpu->cpsr.v = operand & 0x10000000; \
404 } \
405 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \
406 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \
407 cpu->cpsr.priv = cpu->privilegeMode; \
408 cpu->cpsr.i = operand & 0x00000080; \
409 cpu->cpsr.f = operand & 0x00000040; \
410 } \
411 })
412
413DEFINE_INSTRUCTION_ARM(MRS,)
414DEFINE_INSTRUCTION_ARM(MSRI,)
415DEFINE_INSTRUCTION_ARM(MRSI,)
416DEFINE_INSTRUCTION_ARM(SWI,)
417
418#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
419 EMITTER ## NAME
420
421#define DO_8(DIRECTIVE) \
422 DIRECTIVE, \
423 DIRECTIVE, \
424 DIRECTIVE, \
425 DIRECTIVE, \
426 DIRECTIVE, \
427 DIRECTIVE, \
428 DIRECTIVE, \
429 DIRECTIVE
430
431#define DO_256(DIRECTIVE) \
432 DO_8(DO_8(DIRECTIVE)), \
433 DO_8(DO_8(DIRECTIVE)), \
434 DO_8(DO_8(DIRECTIVE)), \
435 DO_8(DO_8(DIRECTIVE))
436
437#define DO_INTERLACE(LEFT, RIGHT) \
438 LEFT, \
439 RIGHT
440
441#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
442 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
443 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
444
445#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
446 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU)), \
447 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
448 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
449 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
450 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
451 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
452 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
453 DECLARE_INSTRUCTION_ARM(EMITTER, ALU), \
454 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
455
456#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
457 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
458 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
459
460#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
461 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
462 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
463 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
464 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
465 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
466 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
467 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
468 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
469 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
470 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
471 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
472 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
473 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
474 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
475 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
476 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
477
478#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
479 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
480 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
481
482#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
483 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
484
485// TODO: Support coprocessors
486#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
487 DO_8(0), \
488 DO_8(0)
489
490#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
491 DO_8(DO_8(DO_INTERLACE(0, 0))), \
492 DO_8(DO_8(DO_INTERLACE(0, 0)))
493
494#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
495 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
496
497#define DECLARE_EMITTER_BLOCK(EMITTER) \
498 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
499 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
500 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
501 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
502 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
503 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
504 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
505 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
506 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
507 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
508 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
509 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
510 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
511 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
512 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
513 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
514 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWP, STRHP, ILL, ILL), \
515 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
516 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
517 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
518 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
519 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
520 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
521 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
522 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
523 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
524 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
525 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
526 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
527 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
528 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
529 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
530 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
531 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
532 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
533 DECLARE_ARM_ALU_BLOCK(EMITTER, MRS, SWPB, STRHIP, ILL, ILL), \
534 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
535 DECLARE_ARM_ALU_BLOCK(EMITTER, MSR, ILL, STRHIPW, ILL, ILL), \
536 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
537 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
538 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
539 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
540 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
541 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
542 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
543 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
544 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
545 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
546 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
547 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
548 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
549 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
550 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
551 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
552 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
553 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
554 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
555 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
556 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
557 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
558 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
559 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
560 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
561 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
562 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
563 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
564 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
565 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MRS), \
566 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
567 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
568 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
569 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
570 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
571 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
572 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
573 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
574 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
575 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
576 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
577 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
578 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
579 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
580 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
581 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
582 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
583 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
584 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
585 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
586 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
587 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
588 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
589 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
590 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
591 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
592 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
593 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
594 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
595 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
596 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
597 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
598 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
599 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
600 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
601 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
602 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
603 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
604 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
605 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
606 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
607 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
608 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
609 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
610 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
611 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
612 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
613 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
614 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
615 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
616 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
617 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
618 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
619 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
620 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
621 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
622 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
623 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
624 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
625 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
626 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
627 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
628 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
629 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
630 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
631 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
632 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
633 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
634 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
635 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
636 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
637 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
638 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
639 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
640 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
641 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
642 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
643 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
644 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
645 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
646 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
647 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
648 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
649 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
650 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
651 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
652 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
653 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
654 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
655 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
656 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
657 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
658 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
659 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
660 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
661 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
662 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
663 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
664 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
665 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
666 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
667 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
668 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
669 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
670 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
671 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
672 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
673 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
674 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
675 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
676 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
677 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
678 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
679 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
680 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
681 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
682 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
683 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
684 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
685 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
686 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
687 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
688 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
689 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
690 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
691 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
692 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
693 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
694 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
695 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
696 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
697 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
698 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
699 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
700 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
701 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
702 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
703 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
704 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
705 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
706 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
707 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
708 DECLARE_ARM_SWI_BLOCK(EMITTER)
709
710static const ARMInstruction _armTable[0x1000] = {
711 DECLARE_EMITTER_BLOCK(_ARMInstruction)
712};