src/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include "util/common.h"
10
11#include "core/core.h"
12#include "gb/gb.h"
13
14extern const uint32_t GB_SAVESTATE_MAGIC;
15extern const uint32_t GB_SAVESTATE_VERSION;
16
17mLOG_DECLARE_CATEGORY(GB_STATE);
18
19/* Savestate format:
20 * 0x00000 - 0x00003: Version Magic (0x01000001)
21 * 0x00004 - 0x00007: ROM CRC32
22 * 0x00008: Game Boy model
23 * 0x00009 - 0x0000F: Reserved (leave zero)
24 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
25 * 0x00020 - 0x00047: CPU state:
26 * | 0x00020: A register
27 * | 0x00021: F register
28 * | 0x00022: B register
29 * | 0x00023: C register
30 * | 0x00024: D register
31 * | 0x00025: E register
32 * | 0x00026: H register
33 * | 0x00027: L register
34 * | 0x00028 - 0x00029: SP register
35 * | 0x0002A - 0x0002B: PC register
36 * | 0x0002C - 0x0002F: Cycles since last event
37 * | 0x00030 - 0x00033: Cycles until next event
38 * | 0x00034 - 0x00035: Reserved (current instruction)
39 * | 0x00036 - 0x00037: Index address
40 * | 0x00038: Bus value
41 * | 0x00039: Execution state
42 * | 0x0003A - 0x0003B: IRQ vector
43 * | 0x0003C - 0x0003F: EI pending cycles
44 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
45 * | 0x00044 - 0x00047: Flags
46 * | bit 0: Is condition met?
47 * | bit 1: Is condition IRQ pending?
48 * | bit 2: Double speed
49 * | bits 3 - 31: Reserved
50 * 0x00048 - 0x0005B: Audio channel 1/framer state
51 * | 0x00048 - 0x0004B: Envelepe timing
52 * | bits 0 - 6: Remaining length
53 * | bits 7 - 9: Next step
54 * | bits 10 - 20: Shadow frequency register
55 * | bits 21 - 31: Reserved
56 * | 0x0004C - 0x0004F: Next frame
57 * | 0x00050 - 0x00053: Next channel 3 fade
58 * | 0x00054 - 0x00057: Reserved
59 * | 0x00058 - 0x0005B: Next event
60 * 0x0005C - 0x0006B: Audio channel 2 state
61 * | 0x0005C - 0x0005F: Envelepe timing
62 * | bits 0 - 2: Remaining length
63 * | bits 3 - 5: Next step
64 * | bits 6 - 31: Reserved
65 * | 0x00060 - 0x00067: Reserved
66 * | 0x00068 - 0x0006B: Next event
67 * 0x0006C - 0x00093: Audio channel 3 state
68 * | 0x0006C - 0x0008B: Wave banks
69 * | 0x0008C - 0x0008D: Remaining length
70 * | 0x0008E - 0x0008F: Reserved
71 * | 0x00090 - 0x00093: Next event
72 * 0x00094 - 0x000A3: Audio channel 4 state
73 * | 0x00094 - 0x00097: Linear feedback shift register state
74 * | 0x00098 - 0x0009B: Envelepe timing
75 * | bits 0 - 2: Remaining length
76 * | bits 3 - 5: Next step
77 * | bits 6 - 31: Reserved
78 * | 0x00098 - 0x0009F: Reserved
79 * | 0x000A0 - 0x000A3: Next event
80 * 0x000A4 - 0x000B7: Audio miscellaneous state
81 * | TODO: Fix this, they're in big-endian order, but field is little-endian
82 * | 0x000A4: Channel 1 envelope state
83 * | bits 0 - 3: Current volume
84 * | bits 4 - 5: Is dead?
85 * | bit 6: Is high?
86 * | 0x000A5: Channel 2 envelope state
87 * | bits 0 - 3: Current volume
88 * | bits 4 - 5: Is dead?
89 * | bit 6: Is high?
90* | bits 7: Reserved
91 * | 0x000A6: Channel 4 envelope state
92 * | bits 0 - 3: Current volume
93 * | bits 4 - 5: Is dead?
94 * | bit 6: Is high?
95* | bits 7: Reserved
96 * | 0x000A7: Miscellaneous audio flags
97 * | bits 0 - 3: Current frame
98 * | bit 4: Is channel 1 sweep enabled?
99 * | bit 5: Has channel 1 sweep occurred?
100 * | bit 6: Is channel 3's memory readable?
101 * | bit 7: Reserved
102 * | 0x000A8 - 0x000AB: Next event
103 * | 0x000AC - 0x000AF: Event diff
104 * | 0x000B0 - 0x000B3: Next sample
105 * 0x000B4 - 0x000153: Video state
106 * | 0x000B4 - 0x000B5: Current x
107 * | 0x000B6 - 0x000B7: Current y (ly)
108 * | 0x000B8 - 0x000BB: Next event
109 * | 0x000BC - 0x000BF: Event diff
110 * | 0x000C0 - 0x000C3: Next mode
111 * | 0x000C4 - 0x000C7: Dot cycle counter
112 * | 0x000C8 - 0x000CB: Frame counter
113 * | 0x000CC: Current VRAM bank
114 * | 0x000CD: Palette flags
115 * | bit 0: BCP increment
116 * | bit 1: OCP increment
117 * | bits 2 - 3: Mode
118 * | bits 4 - 7: Reserved
119 * | 0x000CE - 0x000CF: Reserved
120 * | 0x000D0 - 0x000D1: BCP index
121 * | 0x000D1 - 0x000D3: OCP index
122 * | 0x000D4 - 0x00153: Palette entries
123 * 0x00154 - 0x000167: Timer state
124 * | 0x00154 - 0x00157: Next event
125 * | 0x00158 - 0x0015B: Event diff
126 * | 0x0015C - 0x0015F: Next DIV
127 * | 0x00160 - 0x00163: Inernal DIV
128 * | 0x00164: TIMA period
129 * | 0x00165: Flags
130 * | bit 0: Is IRQ pending?
131 * | 0x00166 - 0x00167: Reserved
132 * 0x000168 - 0x000197: Memory state
133 * | 0x00168 - 0x00169: Current ROM bank
134 * | 0x0016A: Current WRAM bank
135 * | 0x0016B: Current SRAM bank
136 * | 0x0016C - 0x0016F: Next DMA
137 * | 0x00170 - 0x00171: Next DMA source
138 * | 0x00172 - 0x00173: Next DMA destination
139 * | 0x00174 - 0x00177: Next HDMA
140 * | 0x00178 - 0x00179: Next HDMA source
141 * | 0x0017A - 0x0017B: Next HDMA destination
142 * | 0x0017C - 0x0017D: HDMA remaining
143 * | 0x0017E: DMA remaining
144 * | 0x0017F - 0x00183: RTC registers
145 * | 0x00184 - 0x00193: MBC state (TODO)
146 * | 0x00194 - 0x00195: Flags
147 * | bit 0: SRAM accessable
148 * | bit 1: RTC accessible
149 * | bit 2: RTC latched
150 * | bit 3: IME
151 * | bit 4: Is HDMA active?
152 * | bits 5 - 7: Active RTC register
153 * | 0x00196 - 0x00197: Reserved (leave zero)
154 * 0x00198 - 0x0019F: Savestate creation time (usec since 1970)
155 * 0x001A0 - 0x0025F: Reserved (leave zero)
156 * 0x00260 - 0x002FF: OAM
157 * 0x00300 - 0x0037F: I/O memory
158 * 0x00380 - 0x003FE: HRAM
159 * 0x003FF: Interrupts enabled
160 * 0x00400 - 0x043FF: VRAM
161 * 0x04400 - 0x0C3FF: WRAM
162 * Total size: 0xC400 (50,176) bytes
163*/
164
165DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
166DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
167DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
168DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
169DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
170DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
171DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
172DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
173DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
174DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
175DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
176DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
177DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
178
179DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
180DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
181DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
182DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
183
184struct GBSerializedPSGState {
185 struct {
186 GBSerializedAudioEnvelope envelope;
187 int32_t nextFrame;
188 int32_t nextCh3Fade;
189 int32_t reserved;
190 int32_t nextEvent;
191 } ch1;
192 struct {
193 GBSerializedAudioEnvelope envelope;
194 int32_t reserved[2];
195 int32_t nextEvent;
196 } ch2;
197 struct {
198 uint32_t wavebanks[8];
199 int16_t length;
200 int16_t reserved;
201 int32_t nextEvent;
202 } ch3;
203 struct {
204 int32_t lfsr;
205 GBSerializedAudioEnvelope envelope;
206 int32_t reserved;
207 int32_t nextEvent;
208 } ch4;
209};
210
211DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
212DECL_BIT(GBSerializedCpuFlags, Condition, 0);
213DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
214DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
215
216DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
217DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
218
219DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
220DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
221DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
222DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
223
224DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
225DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
226DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
227
228DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
229DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
230DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
231DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
232DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
233DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
234DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
235
236#pragma pack(push, 1)
237struct GBSerializedState {
238 uint32_t versionMagic;
239 uint32_t romCrc32;
240 uint8_t model;
241 uint8_t reservedHeader[7];
242
243 char title[16];
244
245 struct {
246 uint8_t a;
247 uint8_t f;
248 uint8_t b;
249 uint8_t c;
250 uint8_t d;
251 uint8_t e;
252 uint8_t h;
253 uint8_t l;
254 uint16_t sp;
255 uint16_t pc;
256
257 int32_t cycles;
258 int32_t nextEvent;
259
260 uint16_t reservedInstruction;
261 uint16_t index;
262 uint8_t bus;
263 uint8_t executionState;
264
265 uint16_t irqVector;
266
267 int32_t eiPending;
268 int32_t reservedDiPending;
269 GBSerializedCpuFlags flags;
270 } cpu;
271
272 struct {
273 struct GBSerializedPSGState psg;
274 GBSerializedAudioFlags flags;
275 int32_t reserved[2];
276 int32_t nextSample;
277 } audio;
278
279 struct {
280 int16_t x;
281 int16_t ly;
282 int32_t nextEvent;
283 int32_t eventDiff;
284 int32_t nextMode;
285 int32_t dotCounter;
286 int32_t frameCounter;
287
288 uint8_t vramCurrentBank;
289 GBSerializedVideoFlags flags;
290 uint16_t reserved;
291
292 uint16_t bcpIndex;
293 uint16_t ocpIndex;
294
295 uint16_t palette[64];
296 } video;
297
298 struct {
299 int32_t nextEvent;
300 int32_t eventDiff;
301
302 int32_t nextDiv;
303 uint32_t internalDiv;
304 uint8_t timaPeriod;
305 GBSerializedTimerFlags flags;
306 uint16_t reserved;
307 } timer;
308
309 struct {
310 uint16_t currentBank;
311 uint8_t wramCurrentBank;
312 uint8_t sramCurrentBank;
313
314 int32_t dmaNext;
315 uint16_t dmaSource;
316 uint16_t dmaDest;
317
318 int32_t hdmaNext;
319 uint16_t hdmaSource;
320 uint16_t hdmaDest;
321
322 uint16_t hdmaRemaining;
323 uint8_t dmaRemaining;
324 uint8_t rtcRegs[5];
325
326 union {
327 struct {
328 uint32_t mode;
329 } mbc1;
330 struct {
331 uint64_t lastLatch;
332 } rtc;
333 struct {
334 int8_t machineState;
335 GBMBC7Field field;
336 int8_t address;
337 uint8_t srBits;
338 uint32_t sr;
339 GBSerializedMBC7Flags flags;
340 } mbc7;
341 struct {
342 uint8_t reserved[16];
343 } padding;
344 };
345
346 GBSerializedMemoryFlags flags;
347 uint16_t reserved;
348 } memory;
349
350 uint64_t creationUsec;
351
352 uint32_t reserved[48];
353
354 uint8_t oam[GB_SIZE_OAM];
355
356 uint8_t io[GB_SIZE_IO];
357 uint8_t hram[GB_SIZE_HRAM];
358 uint8_t ie;
359
360 uint8_t vram[GB_SIZE_VRAM];
361 uint8_t wram[GB_SIZE_WORKING_RAM];
362};
363#pragma pack(pop)
364
365bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
366void GBSerialize(struct GB* gb, struct GBSerializedState* state);
367
368#endif