1#ifndef ARM_H
  2#define ARM_H
  3
  4#include "common.h"
  5
  6enum {
  7	ARM_SP = 13,
  8	ARM_LR = 14,
  9	ARM_PC = 15
 10};
 11
 12enum ExecutionMode {
 13	MODE_ARM = 0,
 14	MODE_THUMB = 1
 15};
 16
 17enum PrivilegeMode {
 18	MODE_USER = 0x10,
 19	MODE_FIQ = 0x11,
 20	MODE_IRQ = 0x12,
 21	MODE_SUPERVISOR = 0x13,
 22	MODE_ABORT = 0x17,
 23	MODE_UNDEFINED = 0x1B,
 24	MODE_SYSTEM = 0x1F
 25};
 26
 27enum WordSize {
 28	WORD_SIZE_ARM = 4,
 29	WORD_SIZE_THUMB = 2
 30};
 31
 32enum ExecutionVector {
 33	BASE_RESET = 0x00000000,
 34	BASE_UNDEF = 0x00000004,
 35	BASE_SWI = 0x00000008,
 36	BASE_PABT = 0x0000000C,
 37	BASE_DABT = 0x00000010,
 38	BASE_IRQ = 0x00000018,
 39	BASE_FIQ = 0x0000001C
 40};
 41
 42enum RegisterBank {
 43	BANK_NONE = 0,
 44	BANK_FIQ = 1,
 45	BANK_IRQ = 2,
 46	BANK_SUPERVISOR = 3,
 47	BANK_ABORT = 4,
 48	BANK_UNDEFINED = 5
 49};
 50
 51struct ARMCore;
 52
 53union PSR {
 54	struct {
 55#ifdef __POWERPC__
 56		unsigned n : 1;
 57		unsigned z : 1;
 58		unsigned c : 1;
 59		unsigned v : 1;
 60		unsigned : 20;
 61		unsigned i : 1;
 62		unsigned f : 1;
 63		enum ExecutionMode t : 1;
 64		enum PrivilegeMode priv : 5;
 65#else
 66		enum PrivilegeMode priv : 5;
 67		enum ExecutionMode t : 1;
 68		unsigned f : 1;
 69		unsigned i : 1;
 70		unsigned : 20;
 71		unsigned v : 1;
 72		unsigned c : 1;
 73		unsigned z : 1;
 74		unsigned n : 1;
 75#endif
 76	};
 77
 78	int32_t packed;
 79};
 80
 81struct ARMMemory {
 82	int32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
 83	int16_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 84	uint16_t (*loadU16)(struct ARMCore*, uint32_t address, int* cycleCounter);
 85	int8_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 86	uint8_t (*loadU8)(struct ARMCore*, uint32_t address, int* cycleCounter);
 87
 88	void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
 89	void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
 90	void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
 91
 92	uint32_t* activeRegion;
 93	uint32_t activeMask;
 94	uint32_t activePrefetchCycles32;
 95	uint32_t activePrefetchCycles16;
 96	uint32_t activeNonseqCycles32;
 97	uint32_t activeNonseqCycles16;
 98	void (*setActiveRegion)(struct ARMCore*, uint32_t address);
 99	int (*waitMultiple)(struct ARMCore*, uint32_t startAddress, int count);
100};
101
102struct ARMInterruptHandler {
103	void (*reset)(struct ARMCore* cpu);
104	void (*processEvents)(struct ARMCore* cpu);
105	void (*swi16)(struct ARMCore* cpu, int immediate);
106	void (*swi32)(struct ARMCore* cpu, int immediate);
107	void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
108	void (*readCPSR)(struct ARMCore* cpu);
109
110	void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
111};
112
113struct ARMComponent {
114	uint32_t id;
115	void (*init)(struct ARMCore* cpu, struct ARMComponent* component);
116	void (*deinit)(struct ARMComponent* component);
117};
118
119struct ARMCore {
120	int32_t gprs[16];
121	union PSR cpsr;
122	union PSR spsr;
123
124	int32_t cycles;
125	int32_t nextEvent;
126	int halted;
127
128	int32_t bankedRegisters[6][7];
129	int32_t bankedSPSRs[6];
130
131	int32_t shifterOperand;
132	int32_t shifterCarryOut;
133
134	uint32_t currentPC;
135	enum ExecutionMode executionMode;
136	enum PrivilegeMode privilegeMode;
137
138	struct ARMMemory memory;
139	struct ARMInterruptHandler irqh;
140
141	struct ARMComponent* master;
142
143	int numComponents;
144	struct ARMComponent** components;
145};
146
147void ARMInit(struct ARMCore* cpu);
148void ARMDeinit(struct ARMCore* cpu);
149void ARMSetComponents(struct ARMCore* cpu, struct ARMComponent* master, int extra, struct ARMComponent** extras);
150
151void ARMReset(struct ARMCore* cpu);
152void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
153void ARMRaiseIRQ(struct ARMCore*);
154void ARMRaiseSWI(struct ARMCore*);
155
156void ARMRun(struct ARMCore* cpu);
157
158#endif