src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int32_t shiftVal = cpu->gprs[rm];
23 if (rm == ARM_PC) {
24 shiftVal += 4;
25 }
26 int shift = cpu->gprs[rs] & 0xFF;
27 if (!shift) {
28 cpu->shifterOperand = shiftVal;
29 cpu->shifterCarryOut = cpu->cpsr.c;
30 } else if (shift < 32) {
31 cpu->shifterOperand = shiftVal << shift;
32 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
33 } else if (shift == 32) {
34 cpu->shifterOperand = 0;
35 cpu->shifterCarryOut = shiftVal & 1;
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = 0;
39 }
40 } else {
41 int immediate = (opcode & 0x00000F80) >> 7;
42 if (!immediate) {
43 cpu->shifterOperand = cpu->gprs[rm];
44 cpu->shifterCarryOut = cpu->cpsr.c;
45 } else {
46 cpu->shifterOperand = cpu->gprs[rm] << immediate;
47 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
48 }
49 }
50}
51
52static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
53 int rm = opcode & 0x0000000F;
54 if (opcode & 0x00000010) {
55 int rs = (opcode >> 8) & 0x0000000F;
56 ++cpu->cycles;
57 uint32_t shiftVal = cpu->gprs[rm];
58 if (rm == ARM_PC) {
59 shiftVal += 4;
60 }
61 int shift = cpu->gprs[rs] & 0xFF;
62 if (!shift) {
63 cpu->shifterOperand = shiftVal;
64 cpu->shifterCarryOut = cpu->cpsr.c;
65 } else if (shift < 32) {
66 cpu->shifterOperand = shiftVal >> shift;
67 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
68 } else if (shift == 32) {
69 cpu->shifterOperand = 0;
70 cpu->shifterCarryOut = shiftVal >> 31;
71 } else {
72 cpu->shifterOperand = 0;
73 cpu->shifterCarryOut = 0;
74 }
75 } else {
76 int immediate = (opcode & 0x00000F80) >> 7;
77 if (immediate) {
78 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
79 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
83 }
84 }
85}
86
87static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
88 int rm = opcode & 0x0000000F;
89 if (opcode & 0x00000010) {
90 int rs = (opcode >> 8) & 0x0000000F;
91 ++cpu->cycles;
92 int shiftVal = cpu->gprs[rm];
93 if (rm == ARM_PC) {
94 shiftVal += 4;
95 }
96 int shift = cpu->gprs[rs] & 0xFF;
97 if (!shift) {
98 cpu->shifterOperand = shiftVal;
99 cpu->shifterCarryOut = cpu->cpsr.c;
100 } else if (shift < 32) {
101 cpu->shifterOperand = shiftVal >> shift;
102 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
103 } else if (cpu->gprs[rm] >> 31) {
104 cpu->shifterOperand = 0xFFFFFFFF;
105 cpu->shifterCarryOut = 1;
106 } else {
107 cpu->shifterOperand = 0;
108 cpu->shifterCarryOut = 0;
109 }
110 } else {
111 int immediate = (opcode & 0x00000F80) >> 7;
112 if (immediate) {
113 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
114 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
115 } else {
116 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
117 cpu->shifterOperand = cpu->shifterCarryOut;
118 }
119 }
120}
121
122static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
123 int rm = opcode & 0x0000000F;
124 if (opcode & 0x00000010) {
125 int rs = (opcode >> 8) & 0x0000000F;
126 ++cpu->cycles;
127 int shiftVal = cpu->gprs[rm];
128 if (rm == ARM_PC) {
129 shiftVal += 4;
130 }
131 int shift = cpu->gprs[rs] & 0xFF;
132 int rotate = shift & 0x1F;
133 if (!shift) {
134 cpu->shifterOperand = shiftVal;
135 cpu->shifterCarryOut = cpu->cpsr.c;
136 } else if (rotate) {
137 cpu->shifterOperand = ROR(shiftVal, rotate);
138 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
139 } else {
140 cpu->shifterOperand = shiftVal;
141 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
142 }
143 } else {
144 int immediate = (opcode & 0x00000F80) >> 7;
145 if (immediate) {
146 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
147 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
148 } else {
149 // RRX
150 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
151 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
152 }
153 }
154}
155
156static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
157 int rotate = (opcode & 0x00000F00) >> 7;
158 int immediate = opcode & 0x000000FF;
159 if (!rotate) {
160 cpu->shifterOperand = immediate;
161 cpu->shifterCarryOut = cpu->cpsr.c;
162 } else {
163 cpu->shifterOperand = ROR(immediate, rotate);
164 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
165 }
166}
167
168// Instruction definitions
169// Beware pre-processor antics
170
171ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
172 cpu->cpsr.flags = 0;
173 cpu->cpsr.n = ARM_SIGN(d);
174 cpu->cpsr.z = !d;
175 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
176 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
177}
178
179ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
180 cpu->cpsr.flags = 0;
181 cpu->cpsr.n = ARM_SIGN(d);
182 cpu->cpsr.z = !d;
183 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
184 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
185}
186
187ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
188 cpu->cpsr.n = ARM_SIGN(d);
189 cpu->cpsr.z = !d; \
190 cpu->cpsr.c = cpu->shifterCarryOut; \
191}
192
193#define ARM_ADDITION_S(M, N, D) \
194 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
195 cpu->cpsr = cpu->spsr; \
196 _ARMReadCPSR(cpu); \
197 } else { \
198 _additionS(cpu, M, N, D); \
199 }
200
201#define ARM_SUBTRACTION_S(M, N, D) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 _subtractionS(cpu, M, N, D); \
207 }
208
209#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 cpu->cpsr.n = ARM_SIGN(D); \
215 cpu->cpsr.z = !(D); \
216 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
217 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
218 }
219
220#define ARM_NEUTRAL_S(M, N, D) \
221 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
222 cpu->cpsr = cpu->spsr; \
223 _ARMReadCPSR(cpu); \
224 } else { \
225 _neutralS(cpu, D); \
226 }
227
228#define ARM_NEUTRAL_HI_S(DLO, DHI) \
229 cpu->cpsr.n = ARM_SIGN(DHI); \
230 cpu->cpsr.z = !((DHI) | (DLO));
231
232#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
233#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
234#define ADDR_MODE_2_ADDRESS (address)
235#define ADDR_MODE_2_RN (cpu->gprs[rn])
236#define ADDR_MODE_2_RM (cpu->gprs[rm])
237#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
238#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
239#define ADDR_MODE_2_WRITEBACK(ADDR) \
240 cpu->gprs[rn] = ADDR; \
241 if (UNLIKELY(rn == ARM_PC)) { \
242 currentCycles += ARMWritePC(cpu); \
243 }
244
245#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
246#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
247#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
248#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
249
250#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
251#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
252#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
253#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
254
255#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
256#define ADDR_MODE_3_RN ADDR_MODE_2_RN
257#define ADDR_MODE_3_RM ADDR_MODE_2_RM
258#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
259#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
260#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
261
262#define ADDR_MODE_4_WRITEBACK_LDM \
263 if (!((1 << rn) & rs)) { \
264 cpu->gprs[rn] = address; \
265 }
266
267#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
268
269#define ARM_LOAD_POST_BODY \
270 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
271 if (rd == ARM_PC) { \
272 currentCycles += ARMWritePC(cpu); \
273 }
274
275#define ARM_STORE_POST_BODY \
276 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
277
278#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
279 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
280 int currentCycles = ARM_PREFETCH_CYCLES; \
281 BODY; \
282 cpu->cycles += currentCycles; \
283 }
284
285#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
286 DEFINE_INSTRUCTION_ARM(NAME, \
287 int rd = (opcode >> 12) & 0xF; \
288 int rn = (opcode >> 16) & 0xF; \
289 UNUSED(rn); \
290 SHIFTER(cpu, opcode); \
291 BODY; \
292 S_BODY; \
293 if (rd == ARM_PC) { \
294 if (cpu->executionMode == MODE_ARM) { \
295 currentCycles += ARMWritePC(cpu); \
296 } else { \
297 currentCycles += ThumbWritePC(cpu); \
298 } \
299 })
300
301#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
302 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
303 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
304 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
312
313#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
315 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
316 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
319
320#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
321 DEFINE_INSTRUCTION_ARM(NAME, \
322 int rd = (opcode >> 16) & 0xF; \
323 int rs = (opcode >> 8) & 0xF; \
324 int rm = opcode & 0xF; \
325 if (rd == ARM_PC) { \
326 return; \
327 } \
328 ARM_WAIT_MUL(cpu->gprs[rs]); \
329 BODY; \
330 S_BODY; \
331 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
332
333#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
334 DEFINE_INSTRUCTION_ARM(NAME, \
335 int rd = (opcode >> 12) & 0xF; \
336 int rdHi = (opcode >> 16) & 0xF; \
337 int rs = (opcode >> 8) & 0xF; \
338 int rm = opcode & 0xF; \
339 if (rdHi == ARM_PC || rd == ARM_PC) { \
340 return; \
341 } \
342 currentCycles += cpu->memory.stall(cpu, WAIT); \
343 BODY; \
344 S_BODY; \
345 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
346
347#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
348 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
349 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
350
351#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
352 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
353 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
354
355#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
356 DEFINE_INSTRUCTION_ARM(NAME, \
357 uint32_t address; \
358 int rn = (opcode >> 16) & 0xF; \
359 int rd = (opcode >> 12) & 0xF; \
360 int rm = opcode & 0xF; \
361 UNUSED(rm); \
362 address = ADDRESS; \
363 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
364 BODY; \
365 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
366
367#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
368 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
369 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
370 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
371 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
372 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
374
375#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
379 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
380 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
386
387#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
391 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
392 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
400
401#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
404
405#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
406 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
407 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
408 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
409 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
410 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
411 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
412
413#define ARM_MS_PRE_store \
414 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
415 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
416
417#define ARM_MS_PRE_load \
418 enum PrivilegeMode privilegeMode; \
419 if (!(rs & 0x8000)) { \
420 privilegeMode = cpu->privilegeMode; \
421 ARMSetPrivilegeMode(cpu, MODE_SYSTEM); \
422 }
423
424#define ARM_MS_POST_store ARMSetPrivilegeMode(cpu, privilegeMode);
425
426#define ARM_MS_POST_load \
427 if (!(rs & 0x8000)) { \
428 ARMSetPrivilegeMode(cpu, privilegeMode); \
429 } else if (_ARMModeHasSPSR(cpu->cpsr.priv)) { \
430 cpu->cpsr = cpu->spsr; \
431 _ARMReadCPSR(cpu); \
432 }
433
434#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
435 DEFINE_INSTRUCTION_ARM(NAME, \
436 int rn = (opcode >> 16) & 0xF; \
437 int rs = opcode & 0x0000FFFF; \
438 uint32_t address = cpu->gprs[rn]; \
439 S_PRE; \
440 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
441 WRITEBACK; \
442 S_POST; \
443 POST_BODY;)
444
445
446#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
447 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
448 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
449 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
450 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
451 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY)
463
464// Begin ALU definitions
465
466DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
467 int32_t n = cpu->gprs[rn];
468 cpu->gprs[rd] = n + cpu->shifterOperand;)
469
470DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
471 int32_t n = cpu->gprs[rn];
472 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
473
474DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
475 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
476
477DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
478 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
479
480DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
481 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
482
483DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
484 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
487 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
490 cpu->gprs[rd] = cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
493 cpu->gprs[rd] = ~cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
496 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
499 int32_t n = cpu->gprs[rn];
500 cpu->gprs[rd] = cpu->shifterOperand - n;)
501
502DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
503 int32_t n = cpu->gprs[rn];
504 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
505
506DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
507 int32_t n = cpu->gprs[rn];
508 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
509
510DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
511 int32_t n = cpu->gprs[rn];
512 cpu->gprs[rd] = n - cpu->shifterOperand;)
513
514DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
515 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
516
517DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
518 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
519
520// End ALU definitions
521
522// Begin multiply definitions
523
524DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
525DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
526
527DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
528 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
529 int32_t dm = cpu->gprs[rd];
530 int32_t dn = d;
531 cpu->gprs[rd] = dm + dn;
532 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
533 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
534
535DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
536 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
537 cpu->gprs[rd] = d;
538 cpu->gprs[rdHi] = d >> 32;,
539 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
540
541DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
542 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
543 int32_t dm = cpu->gprs[rd];
544 int32_t dn = d;
545 cpu->gprs[rd] = dm + dn;
546 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
547 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
548
549DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
550 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
551 cpu->gprs[rd] = d;
552 cpu->gprs[rdHi] = d >> 32;,
553 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
554
555// End multiply definitions
556
557// Begin load/store definitions
558
559DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
560DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
561DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
562DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
563DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
564DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
565DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
566DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
567
568DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
569 enum PrivilegeMode priv = cpu->privilegeMode;
570 ARMSetPrivilegeMode(cpu, MODE_USER);
571 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
572 ARMSetPrivilegeMode(cpu, priv);
573 cpu->gprs[rd] = r;
574 ARM_LOAD_POST_BODY;)
575
576DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
577 enum PrivilegeMode priv = cpu->privilegeMode;
578 ARMSetPrivilegeMode(cpu, MODE_USER);
579 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
580 ARMSetPrivilegeMode(cpu, priv);
581 cpu->gprs[rd] = r;
582 ARM_LOAD_POST_BODY;)
583
584DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
585 enum PrivilegeMode priv = cpu->privilegeMode;
586 int32_t r = cpu->gprs[rd];
587 ARMSetPrivilegeMode(cpu, MODE_USER);
588 cpu->memory.store8(cpu, address, r, ¤tCycles);
589 ARMSetPrivilegeMode(cpu, priv);
590 ARM_STORE_POST_BODY;)
591
592DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
593 enum PrivilegeMode priv = cpu->privilegeMode;
594 int32_t r = cpu->gprs[rd];
595 ARMSetPrivilegeMode(cpu, MODE_USER);
596 cpu->memory.store32(cpu, address, r, ¤tCycles);
597 ARMSetPrivilegeMode(cpu, priv);
598 ARM_STORE_POST_BODY;)
599
600DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
601 load,
602 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
603 if ((rs & 0x8000) || !rs) {
604 if (cpu->executionMode == MODE_THUMB) {
605 currentCycles += ThumbWritePC(cpu);
606 } else {
607 currentCycles += ARMWritePC(cpu);
608 }
609 })
610
611DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
612 store,
613 ARM_STORE_POST_BODY;)
614
615DEFINE_INSTRUCTION_ARM(SWP,
616 int rm = opcode & 0xF;
617 int rd = (opcode >> 12) & 0xF;
618 int rn = (opcode >> 16) & 0xF;
619 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
620 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
621 cpu->gprs[rd] = d;)
622
623DEFINE_INSTRUCTION_ARM(SWPB,
624 int rm = opcode & 0xF;
625 int rd = (opcode >> 12) & 0xF;
626 int rn = (opcode >> 16) & 0xF;
627 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
628 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
629 cpu->gprs[rd] = d;)
630
631// End load/store definitions
632
633// Begin branch definitions
634
635DEFINE_INSTRUCTION_ARM(B,
636 int32_t offset = opcode << 8;
637 offset >>= 6;
638 cpu->gprs[ARM_PC] += offset;
639 currentCycles += ARMWritePC(cpu);)
640
641DEFINE_INSTRUCTION_ARM(BL,
642 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
643 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
644 cpu->gprs[ARM_PC] += immediate >> 6;
645 currentCycles += ARMWritePC(cpu);)
646
647DEFINE_INSTRUCTION_ARM(BX,
648 int rm = opcode & 0x0000000F;
649 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
650 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
651 if (cpu->executionMode == MODE_THUMB) {
652 currentCycles += ThumbWritePC(cpu);
653 } else {
654 currentCycles += ARMWritePC(cpu);
655 })
656
657// End branch definitions
658
659// Begin coprocessor definitions
660
661DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
662DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
663DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
664DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
665DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
666
667// Begin miscellaneous definitions
668
669DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
670DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
671
672DEFINE_INSTRUCTION_ARM(MSR,
673 int c = opcode & 0x00010000;
674 int f = opcode & 0x00080000;
675 int32_t operand = cpu->gprs[opcode & 0x0000000F];
676 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
677 if (mask & PSR_USER_MASK) {
678 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
679 }
680 if (mask & PSR_STATE_MASK) {
681 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
682 }
683 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
684 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
685 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
686 }
687 _ARMReadCPSR(cpu);
688 if (cpu->executionMode == MODE_THUMB) {
689 cpu->prefetch[0] = 0x46C0; // nop
690 cpu->prefetch[1] &= 0xFFFF;
691 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
692 } else {
693 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
694 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
695 })
696
697DEFINE_INSTRUCTION_ARM(MSRR,
698 int c = opcode & 0x00010000;
699 int f = opcode & 0x00080000;
700 int32_t operand = cpu->gprs[opcode & 0x0000000F];
701 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
702 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
703 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
704
705DEFINE_INSTRUCTION_ARM(MRS, \
706 int rd = (opcode >> 12) & 0xF; \
707 cpu->gprs[rd] = cpu->cpsr.packed;)
708
709DEFINE_INSTRUCTION_ARM(MRSR, \
710 int rd = (opcode >> 12) & 0xF; \
711 cpu->gprs[rd] = cpu->spsr.packed;)
712
713DEFINE_INSTRUCTION_ARM(MSRI,
714 int c = opcode & 0x00010000;
715 int f = opcode & 0x00080000;
716 int rotate = (opcode & 0x00000F00) >> 7;
717 int32_t operand = ROR(opcode & 0x000000FF, rotate);
718 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
719 if (mask & PSR_USER_MASK) {
720 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
721 }
722 if (mask & PSR_STATE_MASK) {
723 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
724 }
725 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
726 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
727 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
728 }
729 _ARMReadCPSR(cpu);
730 if (cpu->executionMode == MODE_THUMB) {
731 cpu->prefetch[0] = 0x46C0; // nop
732 cpu->prefetch[1] &= 0xFFFF;
733 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
734 } else {
735 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
736 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
737 })
738
739DEFINE_INSTRUCTION_ARM(MSRRI,
740 int c = opcode & 0x00010000;
741 int f = opcode & 0x00080000;
742 int rotate = (opcode & 0x00000F00) >> 7;
743 int32_t operand = ROR(opcode & 0x000000FF, rotate);
744 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
745 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
746 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
747
748DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
749
750const ARMInstruction _armTable[0x1000] = {
751 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
752};