src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "ds.h"
7
8#include "arm/decoder.h"
9#include "arm/debugger/debugger.h"
10#include "arm/isa-inlines.h"
11#include "ds/bios.h"
12
13#include "util/crc32.h"
14#include "util/memory.h"
15#include "util/math.h"
16#include "util/vfs.h"
17
18mLOG_DEFINE_CATEGORY(DS, "DS");
19
20const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
21const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
22const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
23
24static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
25static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
26
27enum {
28 DS7_SP_BASE = 0x380FD80,
29 DS7_SP_BASE_IRQ = 0x380FF80,
30 DS7_SP_BASE_SVC = 0x380FFC0,
31
32 DS9_SP_BASE = 0x3002F7C,
33 DS9_SP_BASE_IRQ = 0x3003F80,
34 DS9_SP_BASE_SVC = 0x3003FC0,
35};
36
37static void DSInit(void* cpu, struct mCPUComponent* component);
38
39static void DS7Reset(struct ARMCore* cpu);
40static void DS7TestIRQ(struct ARMCore* cpu);
41static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
42
43static void DS9Reset(struct ARMCore* cpu);
44static void DS9TestIRQ(struct ARMCore* cpu);
45static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
46static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
47
48static void DSProcessEvents(struct ARMCore* cpu);
49static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
50static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
51static void DSBreakpoint(struct ARMCore* cpu, int immediate);
52
53void DSCreate(struct DS* ds) {
54 ds->d.id = DS_COMPONENT_MAGIC;
55 ds->d.init = DSInit;
56 ds->d.deinit = NULL;
57 ds->arm7 = NULL;
58 ds->arm9 = NULL;
59}
60
61static void DSInit(void* cpu, struct mCPUComponent* component) {
62 struct DS* ds = (struct DS*) component;
63 struct ARMCore* core = cpu;
64 if (!ds->arm7) {
65 // The ARM7 must get initialized first
66 ds->arm7 = core;
67 ds->debugger = 0;
68 ds->sync = 0;
69 return;
70 }
71 ds->arm9 = cpu;
72
73 ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
74
75 DS7InterruptHandlerInit(&ds->arm7->irqh);
76 DS9InterruptHandlerInit(&ds->arm9->irqh);
77 DSMemoryInit(ds);
78
79 ds->video.p = ds;
80
81 ds->springIRQ7 = 0;
82 ds->springIRQ9 = 0;
83 ds->keySource = NULL;
84 ds->rtcSource = NULL;
85 ds->rumble = NULL;
86
87 ds->romVf = NULL;
88
89 ds->keyCallback = NULL;
90}
91
92void DSUnloadROM(struct DS* ds) {
93 if (ds->romVf) {
94 ds->romVf->close(ds->romVf);
95 ds->romVf = NULL;
96 }
97}
98
99void DSDestroy(struct DS* ds) {
100 DSUnloadROM(ds);
101 DSMemoryDeinit(ds);
102}
103
104void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
105 irqh->reset = DS7Reset;
106 irqh->processEvents = DSProcessEvents;
107 irqh->swi16 = DS7Swi16;
108 irqh->swi32 = DS7Swi32;
109 irqh->hitIllegal = DSIllegal;
110 irqh->readCPSR = DS7TestIRQ;
111 irqh->writeCP15 = NULL;
112 irqh->hitStub = DSHitStub;
113 irqh->bkpt16 = DSBreakpoint;
114 irqh->bkpt32 = DSBreakpoint;
115}
116
117void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
118 irqh->reset = DS9Reset;
119 irqh->processEvents = DSProcessEvents;
120 irqh->swi16 = NULL;
121 irqh->swi32 = NULL;
122 irqh->hitIllegal = DSIllegal;
123 irqh->readCPSR = DS9TestIRQ;
124 irqh->writeCP15 = DS9WriteCP15;
125 irqh->hitStub = DSHitStub;
126 irqh->bkpt16 = DSBreakpoint;
127 irqh->bkpt32 = DSBreakpoint;
128}
129
130void DS7Reset(struct ARMCore* cpu) {
131 ARMSetPrivilegeMode(cpu, MODE_IRQ);
132 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
133 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
134 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
135 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
136 cpu->gprs[ARM_SP] = DS7_SP_BASE;
137
138 struct DS* ds = (struct DS*) cpu->master;
139 DSMemoryReset(ds);
140 DS7IOInit(ds);
141
142 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
143 if (header) {
144 // TODO: Error check
145 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
146 uint32_t base = header->arm7Base - DS_BASE_RAM;
147 uint32_t* basePointer = &ds->memory.ram[base >> 2];
148 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
149 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
150 }
151 cpu->gprs[12] = header->arm7Entry;
152 cpu->gprs[ARM_LR] = header->arm7Entry;
153 cpu->gprs[ARM_PC] = header->arm7Entry;
154 int currentCycles = 0;
155 ARM_WRITE_PC;
156
157 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
158 }
159}
160
161void DS9Reset(struct ARMCore* cpu) {
162 ARMSetPrivilegeMode(cpu, MODE_IRQ);
163 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
164 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
165 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
166 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
167 cpu->gprs[ARM_SP] = DS9_SP_BASE;
168
169 struct DS* ds = (struct DS*) cpu->master;
170 DS9IOInit(ds);
171
172 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
173 if (header) {
174 // TODO: Error check
175 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
176 uint32_t base = header->arm9Base - DS_BASE_RAM;
177 uint32_t* basePointer = &ds->memory.ram[base >> 2];
178 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
179 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
180 }
181 cpu->gprs[12] = header->arm9Entry;
182 cpu->gprs[ARM_LR] = header->arm9Entry;
183 cpu->gprs[ARM_PC] = header->arm9Entry;
184 int currentCycles = 0;
185 ARM_WRITE_PC;
186
187 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
188 }
189}
190
191static void DSProcessEvents(struct ARMCore* cpu) {
192 struct DS* ds = (struct DS*) cpu->master;
193
194 if (ds->springIRQ7) {
195 ARMRaiseIRQ(cpu);
196 ds->springIRQ7 = 0;
197 }
198
199 do {
200 int32_t cycles = cpu->nextEvent;
201 int32_t nextEvent = INT_MAX;
202#ifndef NDEBUG
203 if (cycles < 0) {
204 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
205 }
206#endif
207
208 cpu->cycles -= cycles;
209 cpu->nextEvent = nextEvent;
210
211 if (cpu->halted) {
212 cpu->cycles = cpu->nextEvent;
213 }
214 } while (cpu->cycles >= cpu->nextEvent);
215}
216
217void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
218 ds->debugger = (struct ARMDebugger*) debugger->platform;
219 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
220 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
221 ARMHotplugAttach(ds->arm7, CPU_COMPONENT_DEBUGGER);
222 ARMHotplugAttach(ds->arm9, CPU_COMPONENT_DEBUGGER);
223}
224
225void DSDetachDebugger(struct DS* ds) {
226 ds->debugger = NULL;
227 ARMHotplugDetach(ds->arm7, CPU_COMPONENT_DEBUGGER);
228 ARMHotplugDetach(ds->arm9, CPU_COMPONENT_DEBUGGER);
229 ds->arm7->components[CPU_COMPONENT_DEBUGGER] = NULL;
230 ds->arm9->components[CPU_COMPONENT_DEBUGGER] = NULL;
231}
232
233bool DSLoadROM(struct DS* ds, struct VFile* vf) {
234 DSUnloadROM(ds);
235 ds->romVf = vf;
236 // TODO: error check
237 return true;
238}
239
240bool DSIsROM(struct VFile* vf) {
241 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
242 return false;
243 }
244 uint8_t signature[sizeof(DS_ROM_MAGIC)];
245 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
246 return false;
247 }
248 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
249}
250
251bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
252 size_t size = vf->size(vf);
253 void* data = NULL;
254 uint32_t crc;
255 if (size == DS7_SIZE_BIOS) {
256 data = vf->map(vf, size, MAP_READ);
257 } else if (size == 0x1000) {
258 data = vf->map(vf, size, MAP_READ);
259 }
260 if (!data) {
261 return false;
262 }
263 crc = doCrc32(data, size);
264 if (crc == DS7_BIOS_CHECKSUM) {
265 ds->bios7Vf = vf;
266 ds->memory.bios7 = data;
267 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
268 } else if (crc == DS9_BIOS_CHECKSUM) {
269 ds->bios9Vf = vf;
270 ds->memory.bios9 = data;
271 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
272 } else {
273 mLOG(DS, WARN, "BIOS checksum incorrect");
274 vf->unmap(vf, data, size);
275 return false;
276 }
277 return true;
278}
279
280void DSGetGameCode(struct DS* ds, char* out) {
281 memset(out, 0, 8);
282 if (!ds->romVf) {
283 return;
284 }
285
286 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
287 memcpy(out, "NTR-", 4);
288 memcpy(&out[4], &cart->id, 4);
289 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
290}
291
292void DSGetGameTitle(struct DS* ds, char* out) {
293 memset(out, 0, 12);
294 if (!ds->romVf) {
295 return;
296 }
297
298 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
299 memcpy(out, &cart->title, 4);
300 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
301}
302
303void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
304 struct DS* ds = (struct DS*) cpu->master;
305 if (ds->debugger) {
306 struct mDebuggerEntryInfo info = {
307 .address = _ARMPCAddress(cpu),
308 .opcode = opcode
309 };
310 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
311 }
312 // TODO: More sensible category?
313 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
314}
315
316void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
317 struct DS* ds = (struct DS*) cpu->master;
318 if (ds->debugger) {
319 struct mDebuggerEntryInfo info = {
320 .address = _ARMPCAddress(cpu),
321 .opcode = opcode
322 };
323 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
324 } else {
325 ARMRaiseUndefined(cpu);
326 }
327}
328
329void DSBreakpoint(struct ARMCore* cpu, int immediate) {
330 struct DS* ds = (struct DS*) cpu->master;
331 if (immediate >= CPU_COMPONENT_MAX) {
332 return;
333 }
334 switch (immediate) {
335 case CPU_COMPONENT_DEBUGGER:
336 if (ds->debugger) {
337 struct mDebuggerEntryInfo info = {
338 .address = _ARMPCAddress(cpu)
339 };
340 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
341 }
342 break;
343 default:
344 break;
345 }
346}
347
348void DS7TestIRQ(struct ARMCore* cpu) {
349 struct DS* ds = (struct DS*) cpu->master;
350 if (0) {
351 ds->springIRQ7 = 1;
352 cpu->nextEvent = cpu->cycles;
353 }
354}
355
356void DS9TestIRQ(struct ARMCore* cpu) {
357 struct DS* ds = (struct DS*) cpu->master;
358 if (0) {
359 ds->springIRQ9 = 1;
360 cpu->nextEvent = cpu->cycles;
361 }
362}
363
364static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
365 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
366}
367
368static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
369 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
370 switch (opcode2) {
371 case 0:
372 cpu->cp15.r2.d = value;
373 break;
374 case 1:
375 cpu->cp15.r2.i = value;
376 break;
377 default:
378 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
379 break;
380 }
381}
382
383static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
384 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
385 switch (opcode2) {
386 case 0:
387 cpu->cp15.r3.d = value;
388 break;
389 default:
390 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
391 break;
392 }
393}
394
395static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
396 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
397}
398
399static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
400 cpu->cp15.r6.region[crm] = value;
401 uint32_t base = ARMProtectionGetBase(value) << 12;
402 uint32_t size = 2 << ARMProtectionGetSize(value);
403 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
404}
405
406static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
407 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
408}
409
410static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
411 uint32_t base = ARMTCMControlGetBase(value) << 12;
412 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
413 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
414 switch (opcode2) {
415 case 0:
416 cpu->cp15.r9.d = value;
417 break;
418 case 1:
419 cpu->cp15.r9.i = value;
420 break;
421 default:
422 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
423 break;
424 }
425}
426
427void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
428 switch (crn) {
429 default:
430 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
431 break;
432 case 0:
433 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
434 ARMRaiseUndefined(cpu);
435 break;
436 case 1:
437 _writeSysControl(cpu, crm, opcode2, value);
438 break;
439 case 2:
440 _writeCacheControl(cpu, crm, opcode2, value);
441 break;
442 case 3:
443 _writeWriteBufferControl(cpu, crm, opcode2, value);
444 break;
445 case 5:
446 _writeAccessControl(cpu, crm, opcode2, value);
447 break;
448 case 6:
449 _writeRegionConfiguration(cpu, crm, opcode2, value);
450 break;
451 case 7:
452 _writeCache(cpu, crm, opcode2, value);
453 break;
454 case 9:
455 _writeTCMControl(cpu, crm, opcode2, value);
456 break;
457 }}