src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-gpio.h"
4#include "gba-io.h"
5#include "hle-bios.h"
6
7#include <limits.h>
8#include <string.h>
9#include <sys/mman.h>
10
11static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
12static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
16static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
17static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
18static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
19static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
20static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
21
22void GBAMemoryInit(struct GBAMemory* memory) {
23 memory->d.load32 = GBALoad32;
24 memory->d.load16 = GBALoad16;
25 memory->d.loadU16 = GBALoadU16;
26 memory->d.load8 = GBALoad8;
27 memory->d.loadU8 = GBALoadU8;
28 memory->d.store32 = GBAStore32;
29 memory->d.store16 = GBAStore16;
30 memory->d.store8 = GBAStore8;
31
32 memory->bios = (uint32_t*) hleBios;
33 memory->fullBios = 0;
34 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
35 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
36 memory->rom = 0;
37 memory->gpio.p = memory->p;
38 memset(memory->io, 0, sizeof(memory->io));
39 memset(memory->dma, 0, sizeof(memory->dma));
40
41 if (!memory->wram || !memory->iwram) {
42 GBAMemoryDeinit(memory);
43 GBALog(memory->p, GBA_LOG_ERROR, "Could not map memory");
44 return;
45 }
46
47 int i;
48 for (i = 0; i < 16; ++i) {
49 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
50 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
51 memory->waitstatesPrefetch16[i] = GBA_BASE_WAITSTATES_SEQ[i];
52 memory->waitstates32[i] = GBA_BASE_WAITSTATES_32[i];
53 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
54 memory->waitstatesPrefetch32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
55 }
56 for (; i < 256; ++i) {
57 memory->waitstates16[i] = 0;
58 memory->waitstatesSeq16[i] = 0;
59 memory->waitstatesPrefetch16[i] = 0;
60 memory->waitstates32[i] = 0;
61 memory->waitstatesSeq32[i] = 0;
62 memory->waitstatesPrefetch32[i] = 0;
63 }
64
65 memory->activeRegion = 0;
66 memory->d.activeRegion = 0;
67 memory->d.activeMask = 0;
68 memory->d.setActiveRegion = GBASetActiveRegion;
69 memory->d.activePrefetchCycles32 = 0;
70 memory->d.activePrefetchCycles16 = 0;
71 memory->biosPrefetch = 0;
72 memory->d.waitMultiple = GBAWaitMultiple;
73}
74
75void GBAMemoryDeinit(struct GBAMemory* memory) {
76 munmap(memory->wram, SIZE_WORKING_RAM);
77 munmap(memory->iwram, SIZE_WORKING_IRAM);
78 GBASavedataDeinit(&memory->savedata);
79}
80
81static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
82 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
83
84 if (gbaMemory->activeRegion == REGION_BIOS) {
85 gbaMemory->biosPrefetch = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
86 }
87 gbaMemory->activeRegion = address >> BASE_OFFSET;
88 memory->activePrefetchCycles32 = gbaMemory->waitstatesPrefetch32[gbaMemory->activeRegion];
89 memory->activePrefetchCycles16 = gbaMemory->waitstatesPrefetch16[gbaMemory->activeRegion];
90 memory->activeNonseqCycles32 = gbaMemory->waitstates32[gbaMemory->activeRegion];
91 memory->activeNonseqCycles16 = gbaMemory->waitstates16[gbaMemory->activeRegion];
92 switch (address & ~OFFSET_MASK) {
93 case BASE_BIOS:
94 memory->activeRegion = gbaMemory->bios;
95 memory->activeMask = SIZE_BIOS - 1;
96 break;
97 case BASE_WORKING_RAM:
98 memory->activeRegion = gbaMemory->wram;
99 memory->activeMask = SIZE_WORKING_RAM - 1;
100 break;
101 case BASE_WORKING_IRAM:
102 memory->activeRegion = gbaMemory->iwram;
103 memory->activeMask = SIZE_WORKING_IRAM - 1;
104 break;
105 case BASE_CART0:
106 case BASE_CART0_EX:
107 case BASE_CART1:
108 case BASE_CART1_EX:
109 case BASE_CART2:
110 case BASE_CART2_EX:
111 memory->activeRegion = gbaMemory->rom;
112 memory->activeMask = SIZE_CART0 - 1;
113 break;
114 default:
115 memory->activeRegion = 0;
116 memory->activeMask = 0;
117 break;
118 }
119}
120
121int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
122 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
123 uint32_t value = 0;
124 int wait = 0;
125
126 switch (address & ~OFFSET_MASK) {
127 case BASE_BIOS:
128 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
129 if (address < SIZE_BIOS) {
130 LOAD_32(value, address, gbaMemory->bios);
131 } else {
132 value = 0;
133 }
134 } else {
135 value = gbaMemory->biosPrefetch;
136 }
137 break;
138 case BASE_WORKING_RAM:
139 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
140 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
141 break;
142 case BASE_WORKING_IRAM:
143 LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
144 break;
145 case BASE_IO:
146 value = GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
147 break;
148 case BASE_PALETTE_RAM:
149 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
150 break;
151 case BASE_VRAM:
152 LOAD_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
153 break;
154 case BASE_OAM:
155 LOAD_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
156 break;
157 case BASE_CART0:
158 case BASE_CART0_EX:
159 case BASE_CART1:
160 case BASE_CART1_EX:
161 case BASE_CART2:
162 case BASE_CART2_EX:
163 wait = gbaMemory->waitstates32[address >> BASE_OFFSET];
164 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
165 LOAD_32(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
166 }
167 break;
168 case BASE_CART_SRAM:
169 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load32: 0x%08X", address);
170 break;
171 default:
172 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
173 if (gbaMemory->p->cpu.executionMode == MODE_ARM) {
174 value = memory->load32(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_ARM * 2, 0);
175 } else {
176 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + WORD_SIZE_THUMB * 2, 0);
177 value |= value << 16;
178 }
179 break;
180 }
181
182
183 if (cycleCounter) {
184 *cycleCounter += 2 + wait;
185 }
186 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
187 int rotate = (address & 3) << 3;
188 return (value >> rotate) | (value << (32 - rotate));
189}
190
191uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
192 return GBALoad16(memory, address, cycleCounter);
193}
194
195int16_t GBALoad16(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
196 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
197 int16_t value = 0;
198 int wait = 0;
199
200 switch (address & ~OFFSET_MASK) {
201 case BASE_BIOS:
202 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
203 if (address < SIZE_BIOS) {
204 LOAD_16(value, address, gbaMemory->bios);
205 } else {
206 value = 0;
207 }
208 } else {
209 value = gbaMemory->biosPrefetch;
210 }
211 break;
212 case BASE_WORKING_RAM:
213 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
214 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
215 break;
216 case BASE_WORKING_IRAM:
217 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
218 break;
219 case BASE_IO:
220 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
221 break;
222 case BASE_PALETTE_RAM:
223 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
224 break;
225 case BASE_VRAM:
226 LOAD_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
227 break;
228 case BASE_OAM:
229 LOAD_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
230 break;
231 case BASE_CART0:
232 case BASE_CART0_EX:
233 case BASE_CART1:
234 case BASE_CART1_EX:
235 case BASE_CART2:
236 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
237 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
238 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
239 }
240 break;
241 case BASE_CART2_EX:
242 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
243 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
244 value = GBASavedataReadEEPROM(&gbaMemory->savedata);
245 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
246 LOAD_16(value, address & (SIZE_CART0 - 1), gbaMemory->rom);
247 }
248 break;
249 case BASE_CART_SRAM:
250 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load16: 0x%08X", address);
251 break;
252 default:
253 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
254 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0);
255 break;
256 }
257
258 if (cycleCounter) {
259 *cycleCounter += 2 + wait;
260 }
261 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
262 int rotate = (address & 1) << 3;
263 return (value >> rotate) | ((value << rotate) & 0xFF00);
264}
265
266uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
267 return GBALoad8(memory, address, cycleCounter);
268}
269
270int8_t GBALoad8(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {
271 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
272 int8_t value = 0;
273 int wait = 0;
274
275 switch (address & ~OFFSET_MASK) {
276 case BASE_BIOS:
277 if (gbaMemory->p->cpu.currentPC >> BASE_OFFSET == REGION_BIOS) {
278 if (address < SIZE_BIOS) {
279 value = ((int8_t*) gbaMemory->bios)[address];
280 } else {
281 value = 0;
282 }
283 } else {
284 value = gbaMemory->biosPrefetch;
285 }
286 break;
287 case BASE_WORKING_RAM:
288 value = ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
289 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
290 break;
291 case BASE_WORKING_IRAM:
292 value = ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
293 break;
294 case BASE_IO:
295 value = (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
296 break;
297 case BASE_PALETTE_RAM:
298 value = ((int8_t*) gbaMemory->p->video.renderer->palette)[address & (SIZE_PALETTE_RAM - 1)];
299 break;
300 case BASE_VRAM:
301 value = ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x0001FFFF];
302 break;
303 case BASE_OAM:
304 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
305 break;
306 case BASE_CART0:
307 case BASE_CART0_EX:
308 case BASE_CART1:
309 case BASE_CART1_EX:
310 case BASE_CART2:
311 case BASE_CART2_EX:
312 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
313 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
314 value = ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
315 }
316 break;
317 case BASE_CART_SRAM:
318 wait = gbaMemory->waitstates16[address >> BASE_OFFSET];
319 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
320 GBASavedataInitSRAM(&gbaMemory->savedata);
321 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
322 value = gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
323 } else if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
324 value = GBASavedataReadFlash(&gbaMemory->savedata, address);
325 }
326 break;
327 default:
328 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
329 value = memory->load16(memory, gbaMemory->p->cpu.currentPC + (gbaMemory->p->cpu.executionMode == MODE_ARM ? WORD_SIZE_ARM : WORD_SIZE_THUMB) * 2, 0) >> ((address & 1) << 3);
330 break;
331 }
332
333 if (cycleCounter) {
334 *cycleCounter += 2 + wait;
335 }
336 return value;
337}
338
339void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value, int* cycleCounter) {
340 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
341 int wait = 0;
342
343 switch (address & ~OFFSET_MASK) {
344 case BASE_WORKING_RAM:
345 STORE_32(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
346 wait = gbaMemory->waitstates32[REGION_WORKING_RAM];
347 break;
348 case BASE_WORKING_IRAM:
349 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
350 break;
351 case BASE_IO:
352 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
353 break;
354 case BASE_PALETTE_RAM:
355 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
356 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
357 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
358 break;
359 case BASE_VRAM:
360 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
361 STORE_32(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
362 }
363 break;
364 case BASE_OAM:
365 STORE_32(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
366 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
367 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
368 break;
369 case BASE_CART0:
370 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
371 break;
372 case BASE_CART_SRAM:
373 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
374 break;
375 default:
376 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
377 break;
378 }
379
380 if (cycleCounter) {
381 *cycleCounter += 1 + wait;
382 }
383}
384
385void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value, int* cycleCounter) {
386 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
387 int wait = 0;
388
389 switch (address & ~OFFSET_MASK) {
390 case BASE_WORKING_RAM:
391 STORE_16(value, address & (SIZE_WORKING_RAM - 1), gbaMemory->wram);
392 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
393 break;
394 case BASE_WORKING_IRAM:
395 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), gbaMemory->iwram);
396 break;
397 case BASE_IO:
398 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
399 break;
400 case BASE_PALETTE_RAM:
401 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gbaMemory->p->video.palette);
402 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
403 break;
404 case BASE_VRAM:
405 if ((address & OFFSET_MASK) < SIZE_VRAM) {
406 STORE_16(value, address & 0x0001FFFF, gbaMemory->p->video.renderer->vram);
407 }
408 break;
409 case BASE_OAM:
410 STORE_16(value, address & (SIZE_OAM - 1), gbaMemory->p->video.oam.raw);
411 gbaMemory->p->video.renderer->writeOAM(gbaMemory->p->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
412 break;
413 case BASE_CART0:
414 if (IS_GPIO_REGISTER(address & 0xFFFFFF)) {
415 uint32_t reg = address & 0xFFFFFF;
416 GBAGPIOWrite(&gbaMemory->gpio, reg, value);
417 } else {
418 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
419 }
420 break;
421 case BASE_CART2_EX:
422 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
423 GBASavedataInitEEPROM(&gbaMemory->savedata);
424 }
425 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
426 break;
427 case BASE_CART_SRAM:
428 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
429 break;
430 default:
431 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
432 break;
433 }
434
435 if (cycleCounter) {
436 *cycleCounter += 1 + wait;
437 }
438}
439
440void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value, int* cycleCounter) {
441 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
442 int wait = 0;
443
444 switch (address & ~OFFSET_MASK) {
445 case BASE_WORKING_RAM:
446 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
447 wait = gbaMemory->waitstates16[REGION_WORKING_RAM];
448 break;
449 case BASE_WORKING_IRAM:
450 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
451 break;
452 case BASE_IO:
453 GBAIOWrite8(gbaMemory->p, address & (SIZE_IO - 1), value);
454 break;
455 case BASE_PALETTE_RAM:
456 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
457 break;
458 case BASE_VRAM:
459 if (address >= 0x06018000) {
460 // TODO: check BG mode
461 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
462 break;
463 }
464 ((int8_t*) gbaMemory->p->video.renderer->vram)[address & 0x1FFFE] = value;
465 ((int8_t*) gbaMemory->p->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
466 break;
467 case BASE_OAM:
468 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
469 break;
470 case BASE_CART0:
471 GBALog(gbaMemory->p, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
472 break;
473 case BASE_CART_SRAM:
474 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
475 if (address == SAVEDATA_FLASH_BASE) {
476 GBASavedataInitFlash(&gbaMemory->savedata);
477 } else {
478 GBASavedataInitSRAM(&gbaMemory->savedata);
479 }
480 }
481 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
482 GBASavedataWriteFlash(&gbaMemory->savedata, address, value);
483 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
484 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
485 }
486 wait = gbaMemory->waitstates16[REGION_CART_SRAM];
487 break;
488 default:
489 GBALog(gbaMemory->p, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
490 break;
491 }
492
493 if (cycleCounter) {
494 *cycleCounter += 1 + wait;
495 }
496}
497
498static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count) {
499 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
500 int wait = 1 + gbaMemory->waitstates32[startAddress >> BASE_OFFSET];
501 wait += (1 + gbaMemory->waitstatesSeq32[startAddress >> BASE_OFFSET]) * (count - 1);
502 return wait;
503}
504
505void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
506 int sram = parameters & 0x0003;
507 int ws0 = (parameters & 0x000C) >> 2;
508 int ws0seq = (parameters & 0x0010) >> 4;
509 int ws1 = (parameters & 0x0060) >> 5;
510 int ws1seq = (parameters & 0x0080) >> 7;
511 int ws2 = (parameters & 0x0300) >> 8;
512 int ws2seq = (parameters & 0x0400) >> 10;
513 int prefetch = parameters & 0x4000;
514
515 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
516 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
517 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
518 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
519
520 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
521 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
522 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
523
524 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
525 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
526 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
527
528 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
529 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
530 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
531
532 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
533 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
534 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
535
536 if (!prefetch) {
537 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
538 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
539 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
540
541 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
542 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
543 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
544 } else {
545 memory->waitstatesPrefetch16[REGION_CART0] = memory->waitstatesPrefetch16[REGION_CART0_EX] = 0;
546 memory->waitstatesPrefetch16[REGION_CART1] = memory->waitstatesPrefetch16[REGION_CART1_EX] = 0;
547 memory->waitstatesPrefetch16[REGION_CART2] = memory->waitstatesPrefetch16[REGION_CART2_EX] = 0;
548
549 memory->waitstatesPrefetch32[REGION_CART0] = memory->waitstatesPrefetch32[REGION_CART0_EX] = 0;
550 memory->waitstatesPrefetch32[REGION_CART1] = memory->waitstatesPrefetch32[REGION_CART1_EX] = 0;
551 memory->waitstatesPrefetch32[REGION_CART2] = memory->waitstatesPrefetch32[REGION_CART2_EX] = 0;
552 }
553
554 memory->d.activePrefetchCycles32 = memory->waitstatesPrefetch32[memory->activeRegion];
555 memory->d.activePrefetchCycles16 = memory->waitstatesPrefetch16[memory->activeRegion];
556 memory->d.activeNonseqCycles32 = memory->waitstates32[memory->activeRegion];
557 memory->d.activeNonseqCycles16 = memory->waitstates16[memory->activeRegion];
558}
559
560int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
561 struct GBADMA* dma;
562 int32_t test = INT_MAX;
563
564 dma = &memory->dma[0];
565 dma->nextIRQ -= cycles;
566 if (dma->enable && dma->doIrq && dma->nextIRQ) {
567 if (dma->nextIRQ <= 0) {
568 dma->nextIRQ = INT_MAX;
569 GBARaiseIRQ(memory->p, IRQ_DMA0);
570 } else if (dma->nextIRQ < test) {
571 test = dma->nextIRQ;
572 }
573 }
574
575 dma = &memory->dma[1];
576 dma->nextIRQ -= cycles;
577 if (dma->enable && dma->doIrq && dma->nextIRQ) {
578 if (dma->nextIRQ <= 0) {
579 dma->nextIRQ = INT_MAX;
580 GBARaiseIRQ(memory->p, IRQ_DMA1);
581 } else if (dma->nextIRQ < test) {
582 test = dma->nextIRQ;
583 }
584 }
585
586 dma = &memory->dma[2];
587 dma->nextIRQ -= cycles;
588 if (dma->enable && dma->doIrq && dma->nextIRQ) {
589 if (dma->nextIRQ <= 0) {
590 dma->nextIRQ = INT_MAX;
591 GBARaiseIRQ(memory->p, IRQ_DMA2);
592 } else if (dma->nextIRQ < test) {
593 test = dma->nextIRQ;
594 }
595 }
596
597 dma = &memory->dma[3];
598 dma->nextIRQ -= cycles;
599 if (dma->enable && dma->doIrq && dma->nextIRQ) {
600 if (dma->nextIRQ <= 0) {
601 dma->nextIRQ = INT_MAX;
602 GBARaiseIRQ(memory->p, IRQ_DMA3);
603 } else if (dma->nextIRQ < test) {
604 test = dma->nextIRQ;
605 }
606 }
607
608 return test;
609}
610
611void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
612 memory->dma[dma].source = address & 0xFFFFFFFE;
613}
614
615void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
616 memory->dma[dma].dest = address & 0xFFFFFFFE;
617}
618
619void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
620 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
621}
622
623uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
624 struct GBADMA* currentDma = &memory->dma[dma];
625 int wasEnabled = currentDma->enable;
626 currentDma->packed = control;
627 currentDma->nextIRQ = 0;
628
629 if (currentDma->drq) {
630 GBALog(memory->p, GBA_LOG_STUB, "DRQ not implemented");
631 }
632
633 if (!wasEnabled && currentDma->enable) {
634 currentDma->nextSource = currentDma->source;
635 currentDma->nextDest = currentDma->dest;
636 currentDma->nextCount = currentDma->count;
637 GBAMemoryScheduleDMA(memory, dma, currentDma);
638 }
639 // If the DMA has already occurred, this value might have changed since the function started
640 return currentDma->packed;
641};
642
643void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
644 switch (info->timing) {
645 case DMA_TIMING_NOW:
646 GBAMemoryServiceDMA(memory, number, info);
647 break;
648 case DMA_TIMING_HBLANK:
649 // Handled implicitly
650 break;
651 case DMA_TIMING_VBLANK:
652 // Handled implicitly
653 break;
654 case DMA_TIMING_CUSTOM:
655 switch (number) {
656 case 0:
657 GBALog(memory->p, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
658 break;
659 case 1:
660 case 2:
661 GBAAudioScheduleFifoDma(&memory->p->audio, number, info);
662 break;
663 case 3:
664 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
665 break;
666 }
667 }
668}
669
670void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
671 struct GBADMA* dma;
672 int i;
673 for (i = 0; i < 4; ++i) {
674 dma = &memory->dma[i];
675 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
676 GBAMemoryServiceDMA(memory, i, dma);
677 }
678 }
679}
680
681void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
682 struct GBADMA* dma;
683 int i;
684 for (i = 0; i < 4; ++i) {
685 dma = &memory->dma[i];
686 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
687 GBAMemoryServiceDMA(memory, i, dma);
688 }
689 }
690}
691
692void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
693 if (!info->enable) {
694 // There was a DMA scheduled that got canceled
695 return;
696 }
697
698 uint32_t width = info->width ? 4 : 2;
699 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
700 int destOffset = DMA_OFFSET[info->dstControl] * width;
701 int32_t wordsRemaining = info->nextCount;
702 uint32_t source = info->nextSource;
703 uint32_t dest = info->nextDest;
704 uint32_t sourceRegion = source >> BASE_OFFSET;
705 uint32_t destRegion = dest >> BASE_OFFSET;
706
707 if (width == 4) {
708 int32_t word;
709 source &= 0xFFFFFFFC;
710 dest &= 0xFFFFFFFC;
711 while (wordsRemaining--) {
712 word = memory->d.load32(&memory->d, source, 0);
713 memory->d.store32(&memory->d, dest, word, 0);
714 source += sourceOffset;
715 dest += destOffset;
716 }
717 } else {
718 uint16_t word;
719 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
720 while (wordsRemaining--) {
721 word = GBASavedataReadEEPROM(&memory->savedata);
722 memory->d.store16(&memory->d, dest, word, 0);
723 source += sourceOffset;
724 dest += destOffset;
725 }
726 } else if (destRegion == REGION_CART2_EX) {
727 if (memory->savedata.type == SAVEDATA_NONE) {
728 GBASavedataInitEEPROM(&memory->savedata);
729 }
730 while (wordsRemaining) {
731 word = memory->d.load16(&memory->d, source, 0);
732 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
733 source += sourceOffset;
734 dest += destOffset;
735 --wordsRemaining;
736 }
737 } else {
738 while (wordsRemaining--) {
739 word = memory->d.load16(&memory->d, source, 0);
740 memory->d.store16(&memory->d, dest, word, 0);
741 source += sourceOffset;
742 dest += destOffset;
743 }
744 }
745 }
746
747 if (info->doIrq) {
748 info->nextIRQ = memory->p->cpu.cycles + 2;
749 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
750 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
751 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
752 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
753 }
754
755 info->nextSource = source;
756 info->nextDest = dest;
757 info->nextCount = wordsRemaining;
758
759 if (!info->repeat) {
760 info->enable = 0;
761
762 // Clear the enable bit in memory
763 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
764 } else {
765 info->nextCount = info->count;
766 if (info->dstControl == DMA_INCREMENT_RELOAD) {
767 info->nextDest = info->dest;
768 }
769 GBAMemoryScheduleDMA(memory, number, info);
770 }
771}