1/* Copyright (c) 2013-2014 Jeffrey Pfau
 2 *
 3 * This Source Code Form is subject to the terms of the Mozilla Public
 4 * License, v. 2.0. If a copy of the MPL was not distributed with this
 5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
 6#ifndef ISA_INLINES_H
 7#define ISA_INLINES_H
 8
 9#include "macros.h"
10
11#include "arm.h"
12
13#define ARM_COND_EQ (cpu->cpsr.z)
14#define ARM_COND_NE (!cpu->cpsr.z)
15#define ARM_COND_CS (cpu->cpsr.c)
16#define ARM_COND_CC (!cpu->cpsr.c)
17#define ARM_COND_MI (cpu->cpsr.n)
18#define ARM_COND_PL (!cpu->cpsr.n)
19#define ARM_COND_VS (cpu->cpsr.v)
20#define ARM_COND_VC (!cpu->cpsr.v)
21#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
22#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
23#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
24#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
25#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
26#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
27#define ARM_COND_AL 1
28
29#define ARM_SIGN(I) ((I) >> 31)
30#define ARM_ROR(I, ROTATE) ((((uint32_t) (I)) >> ROTATE) | ((uint32_t) (I) << ((-ROTATE) & 31)))
31
32
33#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
34#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
35#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
36#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
37
38#define ARM_WAIT_MUL(R) \
39	if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
40		currentCycles += 1; \
41	} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
42		currentCycles += 2; \
43	} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
44		currentCycles += 3; \
45	} else { \
46		currentCycles += 4; \
47	}
48
49#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
50#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
51
52#define ARM_WRITE_PC \
53	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM); \
54	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
55	LOAD_32(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
56	cpu->gprs[ARM_PC] += WORD_SIZE_ARM; \
57	currentCycles += 2 + cpu->memory.activeUncachedCycles32 + cpu->memory.activeSeqCycles32;
58
59#define THUMB_WRITE_PC \
60	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB); \
61	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]); \
62	LOAD_16(cpu->prefetch, cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
63	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB; \
64	currentCycles += 2 + cpu->memory.activeUncachedCycles16 + cpu->memory.activeSeqCycles16;
65
66static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
67	return mode != MODE_SYSTEM && mode != MODE_USER;
68}
69
70static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
71	if (executionMode == cpu->executionMode) {
72		return;
73	}
74
75	cpu->executionMode = executionMode;
76	switch (executionMode) {
77	case MODE_ARM:
78		cpu->cpsr.t = 0;
79		break;
80	case MODE_THUMB:
81		cpu->cpsr.t = 1;
82	}
83	cpu->nextEvent = 0;
84}
85
86static inline void _ARMReadCPSR(struct ARMCore* cpu) {
87	_ARMSetMode(cpu, cpu->cpsr.t);
88	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
89	cpu->irqh.readCPSR(cpu);
90}
91
92#endif