1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_VRAM = 0x4000,
 48	GB_SIZE_VRAM_BANK0 = 0x2000,
 49	GB_SIZE_EXTERNAL_RAM = 0x2000,
 50	GB_SIZE_WORKING_RAM = 0x8000,
 51	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 52	GB_SIZE_OAM = 0xA0,
 53	GB_SIZE_IO = 0x80,
 54	GB_SIZE_HRAM = 0x7F,
 55};
 56
 57enum GBMemoryBankControllerType {
 58	GB_MBC_NONE = 0,
 59	GB_MBC1 = 1,
 60	GB_MBC2 = 2,
 61	GB_MBC3 = 3,
 62	GB_MBC5 = 5,
 63	GB_MBC6 = 6,
 64	GB_MBC7 = 7,
 65	GB_MMM01 = 0x10,
 66	GB_HuC1 = 0x11,
 67	GB_HuC3 = 0x12,
 68};
 69
 70struct GBMemory;
 71typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 72
 73struct GBMemory {
 74	uint8_t* rom;
 75	uint8_t* romBank;
 76	enum GBMemoryBankControllerType mbcType;
 77	GBMemoryBankController mbc;
 78	int currentBank;
 79
 80	uint8_t* wram;
 81	uint8_t* wramBank;
 82	int wramCurrentBank;
 83
 84	bool sramAccess;
 85	uint8_t* sram;
 86	uint8_t* sramBank;
 87	int sramCurrentBank;
 88
 89	uint8_t io[GB_SIZE_IO];
 90	bool ime;
 91	uint8_t ie;
 92
 93	uint8_t hram[GB_SIZE_HRAM];
 94
 95	int32_t dmaNext;
 96	uint16_t dmaSource;
 97	uint16_t dmaDest;
 98	int dmaRemaining;
 99
100	int32_t hdmaNext;
101	uint16_t hdmaSource;
102	uint16_t hdmaDest;
103	int hdmaRemaining;
104	bool isHdma;
105
106	size_t romSize;
107
108	bool rtcAccess;
109	int activeRtcReg;
110	int rtcLatched;
111	uint8_t rtcRegs[5];
112	struct mRTCSource* rtc;
113};
114
115void GBMemoryInit(struct GB* gb);
116void GBMemoryDeinit(struct GB* gb);
117
118void GBMemoryReset(struct GB* gb);
119void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
120
121uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
122void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
123
124int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
125void GBMemoryDMA(struct GB* gb, uint16_t base);
126void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
127
128uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
129void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
130
131uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
132uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
133
134void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
135void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
136
137#endif