src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38
39static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
40static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
42static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
43
44static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
45
46static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
47static void _GBPocketCamCapture(struct GBMemory*);
48
49void GBMBCSwitchBank(struct GB* gb, int bank) {
50 size_t bankStart = bank * GB_SIZE_CART_BANK0;
51 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
52 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
53 bankStart &= (gb->memory.romSize - 1);
54 bank = bankStart / GB_SIZE_CART_BANK0;
55 }
56 gb->memory.romBank = &gb->memory.rom[bankStart];
57 gb->memory.currentBank = bank;
58 if (gb->cpu->pc < GB_BASE_VRAM) {
59 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
60 }
61}
62
63void GBMBCSwitchBank0(struct GB* gb, int bank) {
64 size_t bankStart = bank * GB_SIZE_CART_BANK0;
65 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
66 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
67 bankStart &= (gb->memory.romSize - 1);
68 }
69 gb->memory.romBase = &gb->memory.rom[bankStart];
70 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
71 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
72 }
73}
74
75void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
76 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
77 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
78 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
79 bankStart &= (gb->memory.romSize - 1);
80 bank = bankStart / GB_SIZE_CART_HALFBANK;
81 if (!bank) {
82 ++bank;
83 }
84 }
85 if (!half) {
86 gb->memory.romBank = &gb->memory.rom[bankStart];
87 gb->memory.currentBank = bank;
88 } else {
89 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
90 gb->memory.mbcState.mbc6.currentBank1 = bank;
91 }
92 if (gb->cpu->pc < GB_BASE_VRAM) {
93 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
94 }
95}
96
97static bool _isMulticart(const uint8_t* mem) {
98 bool success = true;
99 struct VFile* vf;
100
101 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
102 success = success && GBIsROM(vf);
103 vf->close(vf);
104
105 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
106 success = success && GBIsROM(vf);
107 vf->close(vf);
108
109 return success;
110}
111
112void GBMBCSwitchSramBank(struct GB* gb, int bank) {
113 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
114 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
115 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
116 bankStart &= (gb->sramSize - 1);
117 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
118 }
119 gb->memory.sramBank = &gb->memory.sram[bankStart];
120 gb->memory.sramCurrentBank = bank;
121}
122
123void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
124 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
125 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
126 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
127 bankStart &= (gb->sramSize - 1);
128 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
129 }
130 if (!half) {
131 gb->memory.sramBank = &gb->memory.sram[bankStart];
132 gb->memory.sramCurrentBank = bank;
133 } else {
134 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
135 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
136 }
137}
138
139void GBMBCInit(struct GB* gb) {
140 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
141 if (gb->memory.rom) {
142 if (gb->memory.romSize >= 0x8000) {
143 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
144 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
145 cart = cartFooter;
146 }
147 }
148 switch (cart->ramSize) {
149 case 0:
150 gb->sramSize = 0;
151 break;
152 case 1:
153 gb->sramSize = 0x800;
154 break;
155 default:
156 case 2:
157 gb->sramSize = 0x2000;
158 break;
159 case 3:
160 gb->sramSize = 0x8000;
161 break;
162 case 4:
163 gb->sramSize = 0x20000;
164 break;
165 case 5:
166 gb->sramSize = 0x10000;
167 break;
168 }
169
170 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
171 switch (cart->type) {
172 case 0:
173 case 8:
174 case 9:
175 gb->memory.mbcType = GB_MBC_NONE;
176 break;
177 case 1:
178 case 2:
179 case 3:
180 gb->memory.mbcType = GB_MBC1;
181 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
182 gb->memory.mbcState.mbc1.multicartStride = 4;
183 } else {
184 gb->memory.mbcState.mbc1.multicartStride = 5;
185 }
186 break;
187 case 5:
188 case 6:
189 gb->memory.mbcType = GB_MBC2;
190 break;
191 case 0x0B:
192 case 0x0C:
193 case 0x0D:
194 gb->memory.mbcType = GB_MMM01;
195 break;
196 case 0x0F:
197 case 0x10:
198 gb->memory.mbcType = GB_MBC3_RTC;
199 break;
200 case 0x11:
201 case 0x12:
202 case 0x13:
203 gb->memory.mbcType = GB_MBC3;
204 break;
205 default:
206 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
207 // Fall through
208 case 0x19:
209 case 0x1A:
210 case 0x1B:
211 gb->memory.mbcType = GB_MBC5;
212 break;
213 case 0x1C:
214 case 0x1D:
215 case 0x1E:
216 gb->memory.mbcType = GB_MBC5_RUMBLE;
217 break;
218 case 0x20:
219 gb->memory.mbcType = GB_MBC6;
220 break;
221 case 0x22:
222 gb->memory.mbcType = GB_MBC7;
223 break;
224 case 0xFC:
225 gb->memory.mbcType = GB_POCKETCAM;
226 break;
227 case 0xFD:
228 gb->memory.mbcType = GB_TAMA5;
229 break;
230 case 0xFE:
231 gb->memory.mbcType = GB_HuC3;
232 break;
233 case 0xFF:
234 gb->memory.mbcType = GB_HuC1;
235 break;
236 }
237 }
238 } else {
239 gb->memory.mbcType = GB_MBC_NONE;
240 }
241 gb->memory.mbcRead = NULL;
242 switch (gb->memory.mbcType) {
243 case GB_MBC_NONE:
244 gb->memory.mbcWrite = _GBMBCNone;
245 break;
246 case GB_MBC1:
247 gb->memory.mbcWrite = _GBMBC1;
248 break;
249 case GB_MBC2:
250 gb->memory.mbcWrite = _GBMBC2;
251 gb->memory.mbcRead = _GBMBC2Read;
252 gb->sramSize = 0x100;
253 break;
254 case GB_MBC3:
255 gb->memory.mbcWrite = _GBMBC3;
256 break;
257 default:
258 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
259 // Fall through
260 case GB_MBC5:
261 gb->memory.mbcWrite = _GBMBC5;
262 break;
263 case GB_MBC6:
264 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
265 gb->memory.mbcWrite = _GBMBC6;
266 gb->memory.mbcRead = _GBMBC6Read;
267 break;
268 case GB_MBC7:
269 gb->memory.mbcWrite = _GBMBC7;
270 gb->memory.mbcRead = _GBMBC7Read;
271 gb->sramSize = 0x100;
272 break;
273 case GB_MMM01:
274 gb->memory.mbcWrite = _GBMMM01;
275 break;
276 case GB_HuC1:
277 gb->memory.mbcWrite = _GBHuC1;
278 break;
279 case GB_HuC3:
280 gb->memory.mbcWrite = _GBHuC3;
281 break;
282 case GB_TAMA5:
283 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
284 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
285 gb->memory.mbcWrite = _GBTAMA5;
286 gb->memory.mbcRead = _GBTAMA5Read;
287 gb->sramSize = 0x20;
288 break;
289 case GB_MBC3_RTC:
290 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
291 gb->memory.mbcWrite = _GBMBC3;
292 break;
293 case GB_MBC5_RUMBLE:
294 gb->memory.mbcWrite = _GBMBC5;
295 break;
296 case GB_POCKETCAM:
297 gb->memory.mbcWrite = _GBPocketCam;
298 gb->memory.mbcRead = _GBPocketCamRead;
299 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
300 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
301 }
302 break;
303 }
304
305 gb->memory.currentBank = 1;
306 gb->memory.sramCurrentBank = 0;
307 gb->memory.sramAccess = false;
308 gb->memory.rtcAccess = false;
309 gb->memory.activeRtcReg = 0;
310 gb->memory.rtcLatched = false;
311 gb->memory.rtcLastLatch = 0;
312 if (gb->memory.rtc) {
313 if (gb->memory.rtc->sample) {
314 gb->memory.rtc->sample(gb->memory.rtc);
315 }
316 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
317 } else {
318 gb->memory.rtcLastLatch = time(0);
319 }
320 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
321
322 GBResizeSram(gb, gb->sramSize);
323
324 if (gb->memory.mbcType == GB_MBC3_RTC) {
325 GBMBCRTCRead(gb);
326 }
327}
328
329static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
330 time_t t;
331 if (rtc) {
332 if (rtc->sample) {
333 rtc->sample(rtc);
334 }
335 t = rtc->unixTime(rtc);
336 } else {
337 t = time(0);
338 }
339 time_t currentLatch = t;
340 t -= *rtcLastLatch;
341 *rtcLastLatch = currentLatch;
342
343 int64_t diff;
344 diff = rtcRegs[0] + t % 60;
345 if (diff < 0) {
346 diff += 60;
347 t -= 60;
348 }
349 rtcRegs[0] = diff % 60;
350 t /= 60;
351 t += diff / 60;
352
353 diff = rtcRegs[1] + t % 60;
354 if (diff < 0) {
355 diff += 60;
356 t -= 60;
357 }
358 rtcRegs[1] = diff % 60;
359 t /= 60;
360 t += diff / 60;
361
362 diff = rtcRegs[2] + t % 24;
363 if (diff < 0) {
364 diff += 24;
365 t -= 24;
366 }
367 rtcRegs[2] = diff % 24;
368 t /= 24;
369 t += diff / 24;
370
371 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
372 rtcRegs[3] = diff;
373 rtcRegs[4] &= 0xFE;
374 rtcRegs[4] |= (diff >> 8) & 1;
375 if (diff & 0x200) {
376 rtcRegs[4] |= 0x80;
377 }
378}
379
380void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
381 struct GBMemory* memory = &gb->memory;
382 int bank = value & 0x1F;
383 int stride = 1 << memory->mbcState.mbc1.multicartStride;
384 switch (address >> 13) {
385 case 0x0:
386 switch (value) {
387 case 0:
388 memory->sramAccess = false;
389 break;
390 case 0xA:
391 memory->sramAccess = true;
392 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
393 break;
394 default:
395 // TODO
396 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
397 break;
398 }
399 break;
400 case 0x1:
401 if (!bank) {
402 ++bank;
403 }
404 bank &= stride - 1;
405 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
406 break;
407 case 0x2:
408 bank &= 3;
409 if (memory->mbcState.mbc1.mode) {
410 GBMBCSwitchBank0(gb, bank << gb->memory.mbcState.mbc1.multicartStride);
411 GBMBCSwitchSramBank(gb, bank);
412 }
413 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
414 break;
415 case 0x3:
416 memory->mbcState.mbc1.mode = value & 1;
417 if (memory->mbcState.mbc1.mode) {
418 GBMBCSwitchBank0(gb, memory->currentBank & ~((1 << memory->mbcState.mbc1.multicartStride) - 1));
419 } else {
420 GBMBCSwitchBank0(gb, 0);
421 GBMBCSwitchSramBank(gb, 0);
422 }
423 break;
424 default:
425 // TODO
426 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
427 break;
428 }
429}
430
431void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
432 struct GBMemory* memory = &gb->memory;
433 int shift = (address & 1) * 4;
434 int bank = value & 0xF;
435 switch (address >> 13) {
436 case 0x0:
437 switch (value) {
438 case 0:
439 memory->sramAccess = false;
440 break;
441 case 0xA:
442 memory->sramAccess = true;
443 break;
444 default:
445 // TODO
446 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
447 break;
448 }
449 break;
450 case 0x1:
451 if (!bank) {
452 ++bank;
453 }
454 GBMBCSwitchBank(gb, bank);
455 break;
456 case 0x5:
457 if (!memory->sramAccess) {
458 return;
459 }
460 address &= 0x1FF;
461 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
462 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
463 break;
464 default:
465 // TODO
466 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
467 break;
468 }
469}
470
471static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
472 address &= 0x1FF;
473 int shift = (address & 1) * 4;
474 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
475}
476
477void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
478 struct GBMemory* memory = &gb->memory;
479 int bank = value & 0x7F;
480 switch (address >> 13) {
481 case 0x0:
482 switch (value) {
483 case 0:
484 memory->sramAccess = false;
485 break;
486 case 0xA:
487 memory->sramAccess = true;
488 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
489 break;
490 default:
491 // TODO
492 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
493 break;
494 }
495 break;
496 case 0x1:
497 if (!bank) {
498 ++bank;
499 }
500 GBMBCSwitchBank(gb, bank);
501 break;
502 case 0x2:
503 if (value < 4) {
504 GBMBCSwitchSramBank(gb, value);
505 memory->rtcAccess = false;
506 } else if (value >= 8 && value <= 0xC) {
507 memory->activeRtcReg = value - 8;
508 memory->rtcAccess = true;
509 }
510 break;
511 case 0x3:
512 if (memory->rtcLatched && value == 0) {
513 memory->rtcLatched = false;
514 } else if (!memory->rtcLatched && value == 1) {
515 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
516 memory->rtcLatched = true;
517 }
518 break;
519 }
520}
521
522void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
523 struct GBMemory* memory = &gb->memory;
524 int bank;
525 switch (address >> 12) {
526 case 0x0:
527 case 0x1:
528 switch (value) {
529 case 0:
530 memory->sramAccess = false;
531 break;
532 case 0xA:
533 memory->sramAccess = true;
534 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
535 break;
536 default:
537 // TODO
538 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
539 break;
540 }
541 break;
542 case 0x2:
543 bank = (memory->currentBank & 0x100) | value;
544 GBMBCSwitchBank(gb, bank);
545 break;
546 case 0x3:
547 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
548 GBMBCSwitchBank(gb, bank);
549 break;
550 case 0x4:
551 case 0x5:
552 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
553 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
554 value &= ~8;
555 }
556 GBMBCSwitchSramBank(gb, value & 0xF);
557 break;
558 default:
559 // TODO
560 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
561 break;
562 }
563}
564
565void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
566 struct GBMemory* memory = &gb->memory;
567 int bank = value;
568 switch (address >> 10) {
569 case 0:
570 switch (value) {
571 case 0:
572 memory->mbcState.mbc6.sramAccess = false;
573 break;
574 case 0xA:
575 memory->mbcState.mbc6.sramAccess = true;
576 break;
577 default:
578 // TODO
579 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
580 break;
581 }
582 break;
583 case 0x1:
584 GBMBCSwitchSramHalfBank(gb, 0, bank);
585 break;
586 case 0x2:
587 GBMBCSwitchSramHalfBank(gb, 1, bank);
588 break;
589 case 0x8:
590 case 0x9:
591 GBMBCSwitchHalfBank(gb, 0, bank);
592 break;
593 case 0xC:
594 case 0xD:
595 GBMBCSwitchHalfBank(gb, 1, bank);
596 break;
597 case 0x28:
598 case 0x29:
599 case 0x2A:
600 case 0x2B:
601 if (memory->mbcState.mbc6.sramAccess) {
602 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
603 }
604 break;
605 case 0x2C:
606 case 0x2D:
607 case 0x2E:
608 case 0x2F:
609 if (memory->mbcState.mbc6.sramAccess) {
610 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
611 }
612 break;
613 default:
614 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
615 break;
616 }
617}
618
619uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
620 if (!memory->mbcState.mbc6.sramAccess) {
621 return 0xFF;
622 }
623 switch (address >> 12) {
624 case 0xA:
625 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
626 case 0xB:
627 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
628 }
629 return 0xFF;
630}
631
632void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
633 int bank = value & 0x7F;
634 switch (address >> 13) {
635 case 0x0:
636 switch (value) {
637 default:
638 case 0:
639 gb->memory.mbcState.mbc7.access = 0;
640 break;
641 case 0xA:
642 gb->memory.mbcState.mbc7.access |= 1;
643 break;
644 }
645 break;
646 case 0x1:
647 GBMBCSwitchBank(gb, bank);
648 break;
649 case 0x2:
650 if (value == 0x40) {
651 gb->memory.mbcState.mbc7.access |= 2;
652 } else {
653 gb->memory.mbcState.mbc7.access &= ~2;
654 }
655 break;
656 case 0x5:
657 _GBMBC7Write(&gb->memory, address, value);
658 break;
659 default:
660 // TODO
661 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
662 break;
663 }
664}
665
666uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
667 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
668 if (mbc7->access != 3) {
669 return 0xFF;
670 }
671 switch (address & 0xF0) {
672 case 0x20:
673 if (memory->rotation && memory->rotation->readTiltX) {
674 int32_t x = -memory->rotation->readTiltX(memory->rotation);
675 x >>= 21;
676 x += 0x81D0;
677 return x;
678 }
679 return 0xFF;
680 case 0x30:
681 if (memory->rotation && memory->rotation->readTiltX) {
682 int32_t x = -memory->rotation->readTiltX(memory->rotation);
683 x >>= 21;
684 x += 0x81D0;
685 return x >> 8;
686 }
687 return 7;
688 case 0x40:
689 if (memory->rotation && memory->rotation->readTiltY) {
690 int32_t y = -memory->rotation->readTiltY(memory->rotation);
691 y >>= 21;
692 y += 0x81D0;
693 return y;
694 }
695 return 0xFF;
696 case 0x50:
697 if (memory->rotation && memory->rotation->readTiltY) {
698 int32_t y = -memory->rotation->readTiltY(memory->rotation);
699 y >>= 21;
700 y += 0x81D0;
701 return y >> 8;
702 }
703 return 7;
704 case 0x60:
705 return 0;
706 case 0x80:
707 return mbc7->eeprom;
708 default:
709 return 0xFF;
710 }
711}
712
713static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
714 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
715 if (mbc7->access != 3) {
716 return;
717 }
718 switch (address & 0xF0) {
719 case 0x00:
720 mbc7->latch = (value & 0x55) == 0x55;
721 return;
722 case 0x10:
723 mbc7->latch |= (value & 0xAA);
724 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
725 memory->rotation->sample(memory->rotation);
726 }
727 mbc7->latch = 0;
728 return;
729 default:
730 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
731 return;
732 case 0x80:
733 break;
734 }
735 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
736 value = GBMBC7FieldFillDO(value); // Hi-Z
737 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
738 mbc7->state = GBMBC7_STATE_IDLE;
739 }
740 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
741 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
742 mbc7->sr <<= 1;
743 mbc7->sr |= GBMBC7FieldGetDI(value);
744 ++mbc7->srBits;
745 }
746 switch (mbc7->state) {
747 case GBMBC7_STATE_IDLE:
748 if (GBMBC7FieldIsDI(value)) {
749 mbc7->state = GBMBC7_STATE_READ_COMMAND;
750 mbc7->srBits = 0;
751 mbc7->sr = 0;
752 }
753 break;
754 case GBMBC7_STATE_READ_COMMAND:
755 if (mbc7->srBits == 10) {
756 mbc7->state = 0x10 | (mbc7->sr >> 6);
757 if (mbc7->state & 0xC) {
758 mbc7->state &= ~0x3;
759 }
760 mbc7->srBits = 0;
761 mbc7->address = mbc7->sr & 0x7F;
762 }
763 break;
764 case GBMBC7_STATE_DO:
765 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
766 mbc7->sr <<= 1;
767 --mbc7->srBits;
768 if (!mbc7->srBits) {
769 mbc7->state = GBMBC7_STATE_IDLE;
770 }
771 break;
772 default:
773 break;
774 }
775 switch (mbc7->state) {
776 case GBMBC7_STATE_EEPROM_EWEN:
777 mbc7->writable = true;
778 mbc7->state = GBMBC7_STATE_IDLE;
779 break;
780 case GBMBC7_STATE_EEPROM_EWDS:
781 mbc7->writable = false;
782 mbc7->state = GBMBC7_STATE_IDLE;
783 break;
784 case GBMBC7_STATE_EEPROM_WRITE:
785 if (mbc7->srBits == 16) {
786 if (mbc7->writable) {
787 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
788 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
789 }
790 mbc7->state = GBMBC7_STATE_IDLE;
791 }
792 break;
793 case GBMBC7_STATE_EEPROM_ERASE:
794 if (mbc7->writable) {
795 memory->sram[mbc7->address * 2] = 0xFF;
796 memory->sram[mbc7->address * 2 + 1] = 0xFF;
797 }
798 mbc7->state = GBMBC7_STATE_IDLE;
799 break;
800 case GBMBC7_STATE_EEPROM_READ:
801 mbc7->srBits = 16;
802 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
803 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
804 mbc7->state = GBMBC7_STATE_DO;
805 value = GBMBC7FieldClearDO(value);
806 break;
807 case GBMBC7_STATE_EEPROM_WRAL:
808 if (mbc7->srBits == 16) {
809 if (mbc7->writable) {
810 int i;
811 for (i = 0; i < 128; ++i) {
812 memory->sram[i * 2] = mbc7->sr >> 8;
813 memory->sram[i * 2 + 1] = mbc7->sr;
814 }
815 }
816 mbc7->state = GBMBC7_STATE_IDLE;
817 }
818 break;
819 case GBMBC7_STATE_EEPROM_ERAL:
820 if (mbc7->writable) {
821 int i;
822 for (i = 0; i < 128; ++i) {
823 memory->sram[i * 2] = 0xFF;
824 memory->sram[i * 2 + 1] = 0xFF;
825 }
826 }
827 mbc7->state = GBMBC7_STATE_IDLE;
828 break;
829 default:
830 break;
831 }
832 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
833 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
834 }
835 mbc7->eeprom = value;
836}
837
838void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
839 struct GBMemory* memory = &gb->memory;
840 if (!memory->mbcState.mmm01.locked) {
841 switch (address >> 13) {
842 case 0x0:
843 memory->mbcState.mmm01.locked = true;
844 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
845 break;
846 case 0x1:
847 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
848 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
849 break;
850 case 0x2:
851 memory->mbcState.mmm01.currentBank0 &= ~0x180;
852 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
853 break;
854 default:
855 // TODO
856 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
857 break;
858 }
859 return;
860 }
861 switch (address >> 13) {
862 case 0x0:
863 switch (value) {
864 case 0xA:
865 memory->sramAccess = true;
866 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
867 break;
868 default:
869 memory->sramAccess = false;
870 break;
871 }
872 break;
873 case 0x1:
874 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
875 break;
876 case 0x2:
877 GBMBCSwitchSramBank(gb, value);
878 break;
879 default:
880 // TODO
881 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
882 break;
883 }
884}
885
886void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
887 struct GBMemory* memory = &gb->memory;
888 int bank = value & 0x3F;
889 switch (address >> 13) {
890 case 0x0:
891 switch (value) {
892 case 0xE:
893 memory->sramAccess = false;
894 break;
895 default:
896 memory->sramAccess = true;
897 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
898 break;
899 }
900 break;
901 case 0x1:
902 GBMBCSwitchBank(gb, bank);
903 break;
904 case 0x2:
905 GBMBCSwitchSramBank(gb, value);
906 break;
907 default:
908 // TODO
909 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
910 break;
911 }
912}
913
914void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
915 struct GBMemory* memory = &gb->memory;
916 int bank = value & 0x3F;
917 if (address & 0x1FFF) {
918 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
919 }
920
921 switch (address >> 13) {
922 case 0x0:
923 switch (value) {
924 case 0xA:
925 memory->sramAccess = true;
926 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
927 break;
928 default:
929 memory->sramAccess = false;
930 break;
931 }
932 break;
933 case 0x1:
934 GBMBCSwitchBank(gb, bank);
935 break;
936 case 0x2:
937 GBMBCSwitchSramBank(gb, bank);
938 break;
939 default:
940 // TODO
941 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
942 break;
943 }
944}
945
946void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
947 struct GBMemory* memory = &gb->memory;
948 int bank = value & 0x3F;
949 switch (address >> 13) {
950 case 0x0:
951 switch (value) {
952 case 0:
953 memory->sramAccess = false;
954 break;
955 case 0xA:
956 memory->sramAccess = true;
957 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
958 break;
959 default:
960 // TODO
961 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
962 break;
963 }
964 break;
965 case 0x1:
966 GBMBCSwitchBank(gb, bank);
967 break;
968 case 0x2:
969 if (value < 0x10) {
970 GBMBCSwitchSramBank(gb, value);
971 memory->mbcState.pocketCam.registersActive = false;
972 } else {
973 memory->mbcState.pocketCam.registersActive = true;
974 }
975 break;
976 case 0x5:
977 address &= 0x7F;
978 if (address == 0 && value & 1) {
979 value &= 6; // TODO: Timing
980 _GBPocketCamCapture(memory);
981 }
982 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
983 memory->mbcState.pocketCam.registers[address] = value;
984 }
985 break;
986 default:
987 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
988 break;
989 }
990}
991
992uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
993 if (memory->mbcState.pocketCam.registersActive) {
994 if ((address & 0x7F) == 0) {
995 return memory->mbcState.pocketCam.registers[0];
996 }
997 return 0;
998 }
999 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1000}
1001
1002void _GBPocketCamCapture(struct GBMemory* memory) {
1003 if (!memory->cam) {
1004 return;
1005 }
1006 const void* image = NULL;
1007 size_t stride;
1008 enum mColorFormat format;
1009 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1010 if (!image) {
1011 return;
1012 }
1013 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1014 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1015 size_t x, y;
1016 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1017 for (x = 0; x < GBCAM_WIDTH; ++x) {
1018 uint32_t gray;
1019 uint32_t color;
1020 switch (format) {
1021 case mCOLOR_XBGR8:
1022 case mCOLOR_XRGB8:
1023 case mCOLOR_ARGB8:
1024 case mCOLOR_ABGR8:
1025 color = ((const uint32_t*) image)[y * stride + x];
1026 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1027 break;
1028 case mCOLOR_BGRX8:
1029 case mCOLOR_RGBX8:
1030 case mCOLOR_RGBA8:
1031 case mCOLOR_BGRA8:
1032 color = ((const uint32_t*) image)[y * stride + x];
1033 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1034 break;
1035 case mCOLOR_BGR5:
1036 case mCOLOR_RGB5:
1037 case mCOLOR_ARGB5:
1038 case mCOLOR_ABGR5:
1039 color = ((const uint16_t*) image)[y * stride + x];
1040 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1041 break;
1042 case mCOLOR_BGR565:
1043 case mCOLOR_RGB565:
1044 color = ((const uint16_t*) image)[y * stride + x];
1045 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1046 break;
1047 case mCOLOR_BGRA5:
1048 case mCOLOR_RGBA5:
1049 color = ((const uint16_t*) image)[y * stride + x];
1050 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1051 break;
1052 default:
1053 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1054 return;
1055 }
1056 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1057 gray = (gray + 1) * exposure / 0x300;
1058 // TODO: Additional processing
1059 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1060 if (gray < pocketCam->registers[matrixEntry + 6]) {
1061 gray = 0x101;
1062 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1063 gray = 0x100;
1064 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1065 gray = 0x001;
1066 } else {
1067 gray = 0;
1068 }
1069 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1070 uint16_t existing;
1071 LOAD_16LE(existing, coord + 0x100, memory->sram);
1072 existing |= gray << (7 - (x & 7));
1073 STORE_16LE(existing, coord + 0x100, memory->sram);
1074 }
1075 }
1076}
1077
1078void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1079 struct GBMemory* memory = &gb->memory;
1080 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1081 switch (address >> 13) {
1082 case 0x5:
1083 if (address & 1) {
1084 tama5->reg = value;
1085 } else {
1086 value &= 0xF;
1087 if (tama5->reg < GBTAMA5_MAX) {
1088 tama5->registers[tama5->reg] = value;
1089 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1090 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1091 switch (tama5->reg) {
1092 case GBTAMA5_BANK_LO:
1093 case GBTAMA5_BANK_HI:
1094 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1095 break;
1096 case GBTAMA5_WRITE_LO:
1097 case GBTAMA5_WRITE_HI:
1098 case GBTAMA5_CS:
1099 break;
1100 case GBTAMA5_ADDR_LO:
1101 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1102 case 0x0: // RAM write
1103 memory->sram[address] = out;
1104 break;
1105 case 0x1: // RAM read
1106 break;
1107 default:
1108 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1109 }
1110 break;
1111 default:
1112 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1113 break;
1114 }
1115 } else {
1116 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1117 }
1118 }
1119 break;
1120 default:
1121 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1122 }
1123}
1124
1125uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1126 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1127 if ((address & 0x1FFF) > 1) {
1128 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1129 }
1130 if (address & 1) {
1131 return 0xFF;
1132 } else {
1133 uint8_t value = 0xF0;
1134 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1135 switch (tama5->reg) {
1136 case GBTAMA5_ACTIVE:
1137 return 0xF1;
1138 case GBTAMA5_READ_LO:
1139 case GBTAMA5_READ_HI:
1140 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1141 case 1:
1142 value = memory->sram[address];
1143 break;
1144 default:
1145 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1146 break;
1147 }
1148 if (tama5->reg == GBTAMA5_READ_HI) {
1149 value >>= 4;
1150 }
1151 value |= 0xF0;
1152 return value;
1153 default:
1154 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1155 return 0xF1;
1156 }
1157 }
1158}
1159
1160void GBMBCRTCRead(struct GB* gb) {
1161 struct GBMBCRTCSaveBuffer rtcBuffer;
1162 struct VFile* vf = gb->sramVf;
1163 if (!vf) {
1164 return;
1165 }
1166 vf->seek(vf, gb->sramSize, SEEK_SET);
1167 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1168 return;
1169 }
1170
1171 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1172 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1173 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1174 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1175 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1176 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1177}
1178
1179void GBMBCRTCWrite(struct GB* gb) {
1180 struct VFile* vf = gb->sramVf;
1181 if (!vf) {
1182 return;
1183 }
1184
1185 uint8_t rtcRegs[5];
1186 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1187 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1188 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1189
1190 struct GBMBCRTCSaveBuffer rtcBuffer;
1191 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1192 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1193 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1194 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1195 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1196 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1197 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1198 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1199 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1200 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1201 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1202
1203 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1204 // Writing past the end of the file can invalidate the file mapping
1205 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1206 gb->memory.sram = NULL;
1207 }
1208 vf->seek(vf, gb->sramSize, SEEK_SET);
1209 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1210 if (!gb->memory.sram) {
1211 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1212 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1213 }
1214}