1/* Copyright (c) 2013-2015 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GBA_MEMORY_H
  7#define GBA_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "arm/arm.h"
 12#include "core/timing.h"
 13
 14#include "gba/hardware.h"
 15#include "gba/savedata.h"
 16#include "gba/vfame.h"
 17
 18enum GBAMemoryRegion {
 19	REGION_BIOS = 0x0,
 20	REGION_WORKING_RAM = 0x2,
 21	REGION_WORKING_IRAM = 0x3,
 22	REGION_IO = 0x4,
 23	REGION_PALETTE_RAM = 0x5,
 24	REGION_VRAM = 0x6,
 25	REGION_OAM = 0x7,
 26	REGION_CART0 = 0x8,
 27	REGION_CART0_EX = 0x9,
 28	REGION_CART1 = 0xA,
 29	REGION_CART1_EX = 0xB,
 30	REGION_CART2 = 0xC,
 31	REGION_CART2_EX = 0xD,
 32	REGION_CART_SRAM = 0xE,
 33	REGION_CART_SRAM_MIRROR = 0xF
 34};
 35
 36enum GBAMemoryBase {
 37	BASE_BIOS = 0x00000000,
 38	BASE_WORKING_RAM = 0x02000000,
 39	BASE_WORKING_IRAM = 0x03000000,
 40	BASE_IO = 0x04000000,
 41	BASE_PALETTE_RAM = 0x05000000,
 42	BASE_VRAM = 0x06000000,
 43	BASE_OAM = 0x07000000,
 44	BASE_CART0 = 0x08000000,
 45	BASE_CART0_EX = 0x09000000,
 46	BASE_CART1 = 0x0A000000,
 47	BASE_CART1_EX = 0x0B000000,
 48	BASE_CART2 = 0x0C000000,
 49	BASE_CART2_EX = 0x0D000000,
 50	BASE_CART_SRAM = 0x0E000000,
 51	BASE_CART_SRAM_MIRROR = 0x0F000000
 52};
 53
 54enum {
 55	SIZE_BIOS = 0x00004000,
 56	SIZE_WORKING_RAM = 0x00040000,
 57	SIZE_WORKING_IRAM = 0x00008000,
 58	SIZE_IO = 0x00000400,
 59	SIZE_PALETTE_RAM = 0x00000400,
 60	SIZE_VRAM = 0x00018000,
 61	SIZE_OAM = 0x00000400,
 62	SIZE_CART0 = 0x02000000,
 63	SIZE_CART1 = 0x02000000,
 64	SIZE_CART2 = 0x02000000,
 65	SIZE_CART_SRAM = 0x00010000,
 66	SIZE_CART_FLASH512 = 0x00010000,
 67	SIZE_CART_FLASH1M = 0x00020000,
 68	SIZE_CART_EEPROM = 0x00002000
 69};
 70
 71enum {
 72	OFFSET_MASK = 0x00FFFFFF,
 73	BASE_OFFSET = 24
 74};
 75
 76enum DMAControl {
 77	DMA_INCREMENT = 0,
 78	DMA_DECREMENT = 1,
 79	DMA_FIXED = 2,
 80	DMA_INCREMENT_RELOAD = 3
 81};
 82
 83enum DMATiming {
 84	DMA_TIMING_NOW = 0,
 85	DMA_TIMING_VBLANK = 1,
 86	DMA_TIMING_HBLANK = 2,
 87	DMA_TIMING_CUSTOM = 3
 88};
 89
 90mLOG_DECLARE_CATEGORY(GBA_MEM);
 91
 92DECL_BITFIELD(GBADMARegister, uint16_t);
 93DECL_BITS(GBADMARegister, DestControl, 5, 2);
 94DECL_BITS(GBADMARegister, SrcControl, 7, 2);
 95DECL_BIT(GBADMARegister, Repeat, 9);
 96DECL_BIT(GBADMARegister, Width, 10);
 97DECL_BIT(GBADMARegister, DRQ, 11);
 98DECL_BITS(GBADMARegister, Timing, 12, 2);
 99DECL_BIT(GBADMARegister, DoIRQ, 14);
100DECL_BIT(GBADMARegister, Enable, 15);
101
102struct GBADMA {
103	GBADMARegister reg;
104
105	uint32_t source;
106	uint32_t dest;
107	int32_t count;
108	uint32_t nextSource;
109	uint32_t nextDest;
110	int32_t nextCount;
111	int32_t nextEvent;
112	uint32_t scheduledAt;
113	int32_t hasStarted;
114};
115
116struct GBAMemory {
117	uint32_t* bios;
118	uint32_t* wram;
119	uint32_t* iwram;
120	uint32_t* rom;
121	uint16_t io[SIZE_IO >> 1];
122
123	struct GBACartridgeHardware hw;
124	struct GBASavedata savedata;
125	struct GBAVFameCart vfame;
126	size_t romSize;
127	uint32_t romMask;
128	uint16_t romID;
129	int fullBios;
130
131	char waitstatesSeq32[256];
132	char waitstatesSeq16[256];
133	char waitstatesNonseq32[256];
134	char waitstatesNonseq16[256];
135	char waitstatesPrefetchSeq32[16];
136	char waitstatesPrefetchSeq16[16];
137	char waitstatesPrefetchNonseq32[16];
138	char waitstatesPrefetchNonseq16[16];
139	int activeRegion;
140	bool prefetch;
141	uint32_t lastPrefetchedPc;
142	uint32_t biosPrefetch;
143
144	struct GBADMA dma[4];
145	struct mTimingEvent dmaEvent;
146	int activeDMA;
147
148	bool mirroring;
149};
150
151void GBAMemoryInit(struct GBA* gba);
152void GBAMemoryDeinit(struct GBA* gba);
153
154void GBAMemoryReset(struct GBA* gba);
155
156uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
157uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
158uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
159
160uint32_t GBALoadBad(struct ARMCore* cpu);
161
162void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
163void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
164void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
165
166uint32_t GBAView32(struct ARMCore* cpu, uint32_t address);
167uint16_t GBAView16(struct ARMCore* cpu, uint32_t address);
168uint8_t GBAView8(struct ARMCore* cpu, uint32_t address);
169
170void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old);
171void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old);
172void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old);
173
174uint32_t GBALoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
175                         int* cycleCounter);
176uint32_t GBAStoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
177                          int* cycleCounter);
178
179void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters);
180
181uint32_t GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address);
182uint32_t GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address);
183void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count);
184uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control);
185
186void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info);
187void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles);
188void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles);
189void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles);
190
191struct GBASerializedState;
192void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state);
193void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state);
194
195#endif