src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
35static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
36
37static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
38
39static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
40static void _GBPocketCamCapture(struct GBMemory*);
41
42void GBMBCSwitchBank(struct GB* gb, int bank) {
43 size_t bankStart = bank * GB_SIZE_CART_BANK0;
44 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
45 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
46 bankStart &= (gb->memory.romSize - 1);
47 bank = bankStart / GB_SIZE_CART_BANK0;
48 if (!bank) {
49 ++bank;
50 }
51 }
52 gb->memory.romBank = &gb->memory.rom[bankStart];
53 gb->memory.currentBank = bank;
54 if (gb->cpu->pc < GB_BASE_VRAM) {
55 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
56 }
57}
58
59void GBMBCSwitchBank0(struct GB* gb, int bank) {
60 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
61 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
62 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
63 bankStart &= (gb->memory.romSize - 1);
64 }
65 gb->memory.romBase = &gb->memory.rom[bankStart];
66 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
67 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
68 }
69}
70
71static bool _isMulticart(const uint8_t* mem) {
72 bool success = true;
73 struct VFile* vf;
74
75 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
76 success = success && GBIsROM(vf);
77 vf->close(vf);
78
79 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
80 success = success && GBIsROM(vf);
81 vf->close(vf);
82
83 return success;
84}
85
86void GBMBCSwitchSramBank(struct GB* gb, int bank) {
87 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
88 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
89 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
90 bankStart &= (gb->sramSize - 1);
91 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
92 }
93 gb->memory.sramBank = &gb->memory.sram[bankStart];
94 gb->memory.sramCurrentBank = bank;
95}
96
97void GBMBCInit(struct GB* gb) {
98 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
99 if (gb->memory.rom) {
100 switch (cart->ramSize) {
101 case 0:
102 gb->sramSize = 0;
103 break;
104 case 1:
105 gb->sramSize = 0x800;
106 break;
107 default:
108 case 2:
109 gb->sramSize = 0x2000;
110 break;
111 case 3:
112 gb->sramSize = 0x8000;
113 break;
114 case 4:
115 gb->sramSize = 0x20000;
116 break;
117 case 5:
118 gb->sramSize = 0x10000;
119 break;
120 }
121
122 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
123 switch (cart->type) {
124 case 0:
125 case 8:
126 case 9:
127 gb->memory.mbcType = GB_MBC_NONE;
128 break;
129 case 1:
130 case 2:
131 case 3:
132 gb->memory.mbcType = GB_MBC1;
133 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
134 gb->memory.mbcState.mbc1.multicartStride = 4;
135 } else {
136 gb->memory.mbcState.mbc1.multicartStride = 5;
137 }
138 break;
139 case 5:
140 case 6:
141 gb->memory.mbcType = GB_MBC2;
142 break;
143 case 0x0F:
144 case 0x10:
145 gb->memory.mbcType = GB_MBC3_RTC;
146 break;
147 case 0x11:
148 case 0x12:
149 case 0x13:
150 gb->memory.mbcType = GB_MBC3;
151 break;
152 default:
153 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
154 // Fall through
155 case 0x19:
156 case 0x1A:
157 case 0x1B:
158 gb->memory.mbcType = GB_MBC5;
159 break;
160 case 0x1C:
161 case 0x1D:
162 case 0x1E:
163 gb->memory.mbcType = GB_MBC5_RUMBLE;
164 break;
165 case 0x20:
166 gb->memory.mbcType = GB_MBC6;
167 break;
168 case 0x22:
169 gb->memory.mbcType = GB_MBC7;
170 break;
171 case 0xFC:
172 gb->memory.mbcType = GB_POCKETCAM;
173 break;
174 case 0xFD:
175 gb->memory.mbcType = GB_TAMA5;
176 break;
177 case 0xFE:
178 gb->memory.mbcType = GB_HuC3;
179 break;
180 case 0xFF:
181 gb->memory.mbcType = GB_HuC1;
182 break;
183 }
184 }
185 } else {
186 gb->memory.mbcType = GB_MBC_NONE;
187 }
188 gb->memory.mbcRead = NULL;
189 switch (gb->memory.mbcType) {
190 case GB_MBC_NONE:
191 gb->memory.mbcWrite = _GBMBCNone;
192 break;
193 case GB_MBC1:
194 gb->memory.mbcWrite = _GBMBC1;
195 break;
196 case GB_MBC2:
197 gb->memory.mbcWrite = _GBMBC2;
198 gb->sramSize = 0x200;
199 break;
200 case GB_MBC3:
201 gb->memory.mbcWrite = _GBMBC3;
202 break;
203 default:
204 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
205 // Fall through
206 case GB_MBC5:
207 gb->memory.mbcWrite = _GBMBC5;
208 break;
209 case GB_MBC6:
210 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
211 gb->memory.mbcWrite = _GBMBC6;
212 break;
213 case GB_MBC7:
214 gb->memory.mbcWrite = _GBMBC7;
215 gb->memory.mbcRead = _GBMBC7Read;
216 gb->sramSize = 0x100;
217 break;
218 case GB_MMM01:
219 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
220 gb->memory.mbcWrite = _GBMBC1;
221 break;
222 case GB_HuC1:
223 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
224 gb->memory.mbcWrite = _GBMBC1;
225 break;
226 case GB_HuC3:
227 gb->memory.mbcWrite = _GBHuC3;
228 break;
229 case GB_TAMA5:
230 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
231 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
232 gb->memory.mbcWrite = _GBTAMA5;
233 gb->memory.mbcRead = _GBTAMA5Read;
234 gb->sramSize = 0x20;
235 break;
236 case GB_MBC3_RTC:
237 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
238 gb->memory.mbcWrite = _GBMBC3;
239 break;
240 case GB_MBC5_RUMBLE:
241 gb->memory.mbcWrite = _GBMBC5;
242 break;
243 case GB_POCKETCAM:
244 gb->memory.mbcWrite = _GBPocketCam;
245 gb->memory.mbcRead = _GBPocketCamRead;
246 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
247 gb->memory.cam->startRequestImage(gb->memory.cam);
248 }
249 break;
250 }
251
252 gb->memory.currentBank = 1;
253 gb->memory.sramCurrentBank = 0;
254 gb->memory.sramAccess = false;
255 gb->memory.rtcAccess = false;
256 gb->memory.activeRtcReg = 0;
257 gb->memory.rtcLatched = false;
258 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
259
260 GBResizeSram(gb, gb->sramSize);
261
262 if (gb->memory.mbcType == GB_MBC3_RTC) {
263 GBMBCRTCRead(gb);
264 }
265}
266
267static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
268 time_t t;
269 if (rtc) {
270 if (rtc->sample) {
271 rtc->sample(rtc);
272 }
273 t = rtc->unixTime(rtc);
274 } else {
275 t = time(0);
276 }
277 time_t currentLatch = t;
278 t -= *rtcLastLatch;
279 *rtcLastLatch = currentLatch;
280
281 int64_t diff;
282 diff = rtcRegs[0] + t % 60;
283 if (diff < 0) {
284 diff += 60;
285 t -= 60;
286 }
287 rtcRegs[0] = diff % 60;
288 t /= 60;
289 t += diff / 60;
290
291 diff = rtcRegs[1] + t % 60;
292 if (diff < 0) {
293 diff += 60;
294 t -= 60;
295 }
296 rtcRegs[1] = diff % 60;
297 t /= 60;
298 t += diff / 60;
299
300 diff = rtcRegs[2] + t % 24;
301 if (diff < 0) {
302 diff += 24;
303 t -= 24;
304 }
305 rtcRegs[2] = diff % 24;
306 t /= 24;
307 t += diff / 24;
308
309 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
310 rtcRegs[3] = diff;
311 rtcRegs[4] &= 0xFE;
312 rtcRegs[4] |= (diff >> 8) & 1;
313 if (diff & 0x200) {
314 rtcRegs[4] |= 0x80;
315 }
316}
317
318void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
319 struct GBMemory* memory = &gb->memory;
320 int bank = value & 0x1F;
321 int stride = 1 << memory->mbcState.mbc1.multicartStride;
322 switch (address >> 13) {
323 case 0x0:
324 switch (value) {
325 case 0:
326 memory->sramAccess = false;
327 break;
328 case 0xA:
329 memory->sramAccess = true;
330 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
331 break;
332 default:
333 // TODO
334 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
335 break;
336 }
337 break;
338 case 0x1:
339 if (!bank) {
340 ++bank;
341 }
342 bank &= stride - 1;
343 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
344 break;
345 case 0x2:
346 bank &= 3;
347 if (memory->mbcState.mbc1.mode) {
348 GBMBCSwitchBank0(gb, bank);
349 GBMBCSwitchSramBank(gb, bank);
350 }
351 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
352 break;
353 case 0x3:
354 memory->mbcState.mbc1.mode = value & 1;
355 if (memory->mbcState.mbc1.mode) {
356 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
357 } else {
358 GBMBCSwitchBank0(gb, 0);
359 GBMBCSwitchSramBank(gb, 0);
360 }
361 break;
362 default:
363 // TODO
364 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
365 break;
366 }
367}
368
369void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
370 struct GBMemory* memory = &gb->memory;
371 int bank = value & 0xF;
372 switch (address >> 13) {
373 case 0x0:
374 switch (value) {
375 case 0:
376 memory->sramAccess = false;
377 break;
378 case 0xA:
379 memory->sramAccess = true;
380 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
381 break;
382 default:
383 // TODO
384 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
385 break;
386 }
387 break;
388 case 0x1:
389 if (!bank) {
390 ++bank;
391 }
392 GBMBCSwitchBank(gb, bank);
393 break;
394 default:
395 // TODO
396 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
397 break;
398 }
399}
400
401void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
402 struct GBMemory* memory = &gb->memory;
403 int bank = value & 0x7F;
404 switch (address >> 13) {
405 case 0x0:
406 switch (value) {
407 case 0:
408 memory->sramAccess = false;
409 break;
410 case 0xA:
411 memory->sramAccess = true;
412 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
413 break;
414 default:
415 // TODO
416 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
417 break;
418 }
419 break;
420 case 0x1:
421 if (!bank) {
422 ++bank;
423 }
424 GBMBCSwitchBank(gb, bank);
425 break;
426 case 0x2:
427 if (value < 4) {
428 GBMBCSwitchSramBank(gb, value);
429 memory->rtcAccess = false;
430 } else if (value >= 8 && value <= 0xC) {
431 memory->activeRtcReg = value - 8;
432 memory->rtcAccess = true;
433 }
434 break;
435 case 0x3:
436 if (memory->rtcLatched && value == 0) {
437 memory->rtcLatched = false;
438 } else if (!memory->rtcLatched && value == 1) {
439 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
440 memory->rtcLatched = true;
441 }
442 break;
443 }
444}
445
446void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
447 struct GBMemory* memory = &gb->memory;
448 int bank;
449 switch (address >> 12) {
450 case 0x0:
451 case 0x1:
452 switch (value) {
453 case 0:
454 memory->sramAccess = false;
455 break;
456 case 0xA:
457 memory->sramAccess = true;
458 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
459 break;
460 default:
461 // TODO
462 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
463 break;
464 }
465 break;
466 case 0x2:
467 bank = (memory->currentBank & 0x100) | value;
468 GBMBCSwitchBank(gb, bank);
469 break;
470 case 0x3:
471 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
472 GBMBCSwitchBank(gb, bank);
473 break;
474 case 0x4:
475 case 0x5:
476 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
477 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
478 value &= ~8;
479 }
480 GBMBCSwitchSramBank(gb, value & 0xF);
481 break;
482 default:
483 // TODO
484 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
485 break;
486 }
487}
488
489void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
490 // TODO
491 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
492 UNUSED(gb);
493 UNUSED(address);
494 UNUSED(value);
495}
496
497void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
498 int bank = value & 0x7F;
499 switch (address >> 13) {
500 case 0x0:
501 switch (value) {
502 default:
503 case 0:
504 gb->memory.mbcState.mbc7.access = 0;
505 break;
506 case 0xA:
507 gb->memory.mbcState.mbc7.access |= 1;
508 break;
509 }
510 break;
511 case 0x1:
512 GBMBCSwitchBank(gb, bank);
513 break;
514 case 0x2:
515 if (value == 0x40) {
516 gb->memory.mbcState.mbc7.access |= 2;
517 } else {
518 gb->memory.mbcState.mbc7.access &= ~2;
519 }
520 break;
521 case 0x5:
522 _GBMBC7Write(&gb->memory, address, value);
523 default:
524 // TODO
525 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
526 break;
527 }
528}
529
530uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
531 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
532 if (mbc7->access != 3) {
533 return 0xFF;
534 }
535 switch (address & 0xF0) {
536 case 0x20:
537 if (memory->rotation && memory->rotation->readTiltX) {
538 int32_t x = -memory->rotation->readTiltX(memory->rotation);
539 x >>= 21;
540 x += 0x81D0;
541 return x;
542 }
543 return 0xFF;
544 case 0x30:
545 if (memory->rotation && memory->rotation->readTiltX) {
546 int32_t x = -memory->rotation->readTiltX(memory->rotation);
547 x >>= 21;
548 x += 0x81D0;
549 return x >> 8;
550 }
551 return 7;
552 case 0x40:
553 if (memory->rotation && memory->rotation->readTiltY) {
554 int32_t y = -memory->rotation->readTiltY(memory->rotation);
555 y >>= 21;
556 y += 0x81D0;
557 return y;
558 }
559 return 0xFF;
560 case 0x50:
561 if (memory->rotation && memory->rotation->readTiltY) {
562 int32_t y = -memory->rotation->readTiltY(memory->rotation);
563 y >>= 21;
564 y += 0x81D0;
565 return y >> 8;
566 }
567 return 7;
568 case 0x60:
569 return 0;
570 case 0x80:
571 return mbc7->eeprom;
572 default:
573 return 0xFF;
574 }
575}
576
577static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
578 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
579 if (mbc7->access != 3) {
580 return;
581 }
582 switch (address & 0xF0) {
583 case 0x00:
584 mbc7->latch = (value & 0x55) == 0x55;
585 return;
586 case 0x10:
587 mbc7->latch |= (value & 0xAA);
588 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
589 memory->rotation->sample(memory->rotation);
590 }
591 mbc7->latch = 0;
592 return;
593 default:
594 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
595 return;
596 case 0x80:
597 break;
598 }
599 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
600 value = GBMBC7FieldFillDO(value); // Hi-Z
601 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
602 mbc7->state = GBMBC7_STATE_IDLE;
603 }
604 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
605 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
606 mbc7->sr <<= 1;
607 mbc7->sr |= GBMBC7FieldGetDI(value);
608 ++mbc7->srBits;
609 }
610 switch (mbc7->state) {
611 case GBMBC7_STATE_IDLE:
612 if (GBMBC7FieldIsDI(value)) {
613 mbc7->state = GBMBC7_STATE_READ_COMMAND;
614 mbc7->srBits = 0;
615 mbc7->sr = 0;
616 }
617 break;
618 case GBMBC7_STATE_READ_COMMAND:
619 if (mbc7->srBits == 10) {
620 mbc7->state = 0x10 | (mbc7->sr >> 6);
621 if (mbc7->state & 0xC) {
622 mbc7->state &= ~0x3;
623 }
624 mbc7->srBits = 0;
625 mbc7->address = mbc7->sr & 0x7F;
626 }
627 break;
628 case GBMBC7_STATE_DO:
629 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
630 mbc7->sr <<= 1;
631 --mbc7->srBits;
632 if (!mbc7->srBits) {
633 mbc7->state = GBMBC7_STATE_IDLE;
634 }
635 break;
636 default:
637 break;
638 }
639 switch (mbc7->state) {
640 case GBMBC7_STATE_EEPROM_EWEN:
641 mbc7->writable = true;
642 mbc7->state = GBMBC7_STATE_IDLE;
643 break;
644 case GBMBC7_STATE_EEPROM_EWDS:
645 mbc7->writable = false;
646 mbc7->state = GBMBC7_STATE_IDLE;
647 break;
648 case GBMBC7_STATE_EEPROM_WRITE:
649 if (mbc7->srBits == 16) {
650 if (mbc7->writable) {
651 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
652 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
653 }
654 mbc7->state = GBMBC7_STATE_IDLE;
655 }
656 break;
657 case GBMBC7_STATE_EEPROM_ERASE:
658 if (mbc7->writable) {
659 memory->sram[mbc7->address * 2] = 0xFF;
660 memory->sram[mbc7->address * 2 + 1] = 0xFF;
661 }
662 mbc7->state = GBMBC7_STATE_IDLE;
663 break;
664 case GBMBC7_STATE_EEPROM_READ:
665 mbc7->srBits = 16;
666 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
667 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
668 mbc7->state = GBMBC7_STATE_DO;
669 value = GBMBC7FieldClearDO(value);
670 break;
671 case GBMBC7_STATE_EEPROM_WRAL:
672 if (mbc7->srBits == 16) {
673 if (mbc7->writable) {
674 int i;
675 for (i = 0; i < 128; ++i) {
676 memory->sram[i * 2] = mbc7->sr >> 8;
677 memory->sram[i * 2 + 1] = mbc7->sr;
678 }
679 }
680 mbc7->state = GBMBC7_STATE_IDLE;
681 }
682 break;
683 case GBMBC7_STATE_EEPROM_ERAL:
684 if (mbc7->writable) {
685 int i;
686 for (i = 0; i < 128; ++i) {
687 memory->sram[i * 2] = 0xFF;
688 memory->sram[i * 2 + 1] = 0xFF;
689 }
690 }
691 mbc7->state = GBMBC7_STATE_IDLE;
692 break;
693 default:
694 break;
695 }
696 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
697 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
698 }
699 mbc7->eeprom = value;
700}
701
702void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
703 struct GBMemory* memory = &gb->memory;
704 int bank = value & 0x3F;
705 if (address & 0x1FFF) {
706 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
707 }
708
709 switch (address >> 13) {
710 case 0x0:
711 switch (value) {
712 case 0xA:
713 memory->sramAccess = true;
714 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
715 break;
716 default:
717 memory->sramAccess = false;
718 break;
719 }
720 break;
721 case 0x1:
722 GBMBCSwitchBank(gb, bank);
723 break;
724 case 0x2:
725 GBMBCSwitchSramBank(gb, bank);
726 break;
727 default:
728 // TODO
729 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
730 break;
731 }
732}
733
734void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
735 struct GBMemory* memory = &gb->memory;
736 int bank = value & 0x3F;
737 switch (address >> 13) {
738 case 0x0:
739 switch (value) {
740 case 0:
741 memory->sramAccess = false;
742 break;
743 case 0xA:
744 memory->sramAccess = true;
745 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
746 break;
747 default:
748 // TODO
749 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
750 break;
751 }
752 break;
753 case 0x1:
754 GBMBCSwitchBank(gb, bank);
755 break;
756 case 0x2:
757 if (value < 0x10) {
758 GBMBCSwitchSramBank(gb, value);
759 memory->mbcState.pocketCam.registersActive = false;
760 } else {
761 memory->mbcState.pocketCam.registersActive = true;
762 }
763 break;
764 case 0x5:
765 address &= 0x7F;
766 if (address == 0 && value & 1) {
767 value &= 6; // TODO: Timing
768 _GBPocketCamCapture(memory);
769 }
770 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
771 memory->mbcState.pocketCam.registers[address] = value;
772 }
773 break;
774 default:
775 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
776 break;
777 }
778}
779
780uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
781 if (memory->mbcState.pocketCam.registersActive) {
782 if ((address & 0x7F) == 0) {
783 return memory->mbcState.pocketCam.registers[0];
784 }
785 return 0;
786 }
787 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
788}
789
790void _GBPocketCamCapture(struct GBMemory* memory) {
791 if (!memory->cam) {
792 return;
793 }
794 const uint32_t* image = NULL;
795 size_t stride;
796 memory->cam->requestImage(memory->cam, GBCAM_WIDTH, GBCAM_HEIGHT, &image, &stride);
797 if (!image) {
798 return;
799 }
800 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
801 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
802 size_t x, y;
803 for (y = 0; y < GBCAM_HEIGHT; ++y) {
804 for (x = 0; x < GBCAM_WIDTH; ++x) {
805 uint32_t color = image[y * stride + x];
806 uint32_t gray = ((color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF));
807 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
808 gray = (gray + 1) * exposure / 0x300;
809 // TODO: Additional processing
810 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
811 if (gray < pocketCam->registers[matrixEntry + 6]) {
812 gray = 0x101;
813 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
814 gray = 0x100;
815 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
816 gray = 0x001;
817 } else {
818 gray = 0;
819 }
820 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
821 uint16_t existing;
822 LOAD_16LE(existing, coord + 0x100, memory->sram);
823 existing |= gray << (7 - (x & 7));
824 STORE_16LE(existing, coord + 0x100, memory->sram);
825 }
826 }
827}
828
829void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
830 struct GBMemory* memory = &gb->memory;
831 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
832 switch (address >> 13) {
833 case 0x5:
834 if (address & 1) {
835 tama5->reg = value;
836 } else {
837 value &= 0xF;
838 if (tama5->reg < GBTAMA5_MAX) {
839 tama5->registers[tama5->reg] = value;
840 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
841 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
842 switch (tama5->reg) {
843 case GBTAMA5_BANK_LO:
844 case GBTAMA5_BANK_HI:
845 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
846 break;
847 case GBTAMA5_WRITE_LO:
848 case GBTAMA5_WRITE_HI:
849 case GBTAMA5_CS:
850 break;
851 case GBTAMA5_ADDR_LO:
852 switch (tama5->registers[GBTAMA5_CS] >> 1) {
853 case 0x0: // RAM write
854 memory->sram[address] = out;
855 break;
856 case 0x1: // RAM read
857 break;
858 default:
859 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
860 }
861 break;
862 default:
863 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
864 break;
865 }
866 } else {
867 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
868 }
869 }
870 break;
871 default:
872 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
873 }
874}
875
876uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
877 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
878 if ((address & 0x1FFF) > 1) {
879 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
880 }
881 if (address & 1) {
882 return 0xFF;
883 } else {
884 uint8_t value = 0xF0;
885 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
886 switch (tama5->reg) {
887 case GBTAMA5_ACTIVE:
888 return 0xF1;
889 case GBTAMA5_READ_LO:
890 case GBTAMA5_READ_HI:
891 switch (tama5->registers[GBTAMA5_CS] >> 1) {
892 case 1:
893 value = memory->sram[address];
894 break;
895 default:
896 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
897 break;
898 }
899 if (tama5->reg == GBTAMA5_READ_HI) {
900 value >>= 4;
901 }
902 value |= 0xF0;
903 return value;
904 default:
905 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
906 return 0xF1;
907 }
908 }
909}
910
911void GBMBCRTCRead(struct GB* gb) {
912 struct GBMBCRTCSaveBuffer rtcBuffer;
913 struct VFile* vf = gb->sramVf;
914 if (!vf) {
915 return;
916 }
917 ssize_t end = vf->seek(vf, -sizeof(rtcBuffer), SEEK_END);
918 switch (end & 0x1FFF) {
919 case 0:
920 break;
921 case 0x1FFC:
922 vf->seek(vf, -sizeof(rtcBuffer) - 4, SEEK_END);
923 break;
924 default:
925 return;
926 }
927 vf->read(vf, &rtcBuffer, sizeof(rtcBuffer));
928
929 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
930 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
931 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
932 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
933 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
934 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
935}
936
937void GBMBCRTCWrite(struct GB* gb) {
938 struct VFile* vf = gb->sramVf;
939 if (!vf) {
940 return;
941 }
942
943 uint8_t rtcRegs[5];
944 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
945 time_t rtcLastLatch = gb->memory.rtcLastLatch;
946 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
947
948 struct GBMBCRTCSaveBuffer rtcBuffer;
949 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
950 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
951 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
952 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
953 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
954 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
955 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
956 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
957 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
958 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
959 STORE_64LE(rtcLastLatch, 0, &rtcBuffer.unixTime);
960
961 if (vf->size(vf) == gb->sramSize) {
962 // Writing past the end of the file can invalidate the file mapping
963 vf->unmap(vf, gb->memory.sram, gb->sramSize);
964 gb->memory.sram = NULL;
965 }
966 vf->seek(vf, gb->sramSize, SEEK_SET);
967 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
968 if (!gb->memory.sram) {
969 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
970 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
971 }
972}