src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39
40static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
41static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
43static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
44
45static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
46
47static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
48static void _GBPocketCamCapture(struct GBMemory*);
49
50void GBMBCSwitchBank(struct GB* gb, int bank) {
51 size_t bankStart = bank * GB_SIZE_CART_BANK0;
52 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
53 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
54 bankStart &= (gb->memory.romSize - 1);
55 bank = bankStart / GB_SIZE_CART_BANK0;
56 }
57 gb->memory.romBank = &gb->memory.rom[bankStart];
58 gb->memory.currentBank = bank;
59 if (gb->cpu->pc < GB_BASE_VRAM) {
60 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
61 }
62}
63
64void GBMBCSwitchBank0(struct GB* gb, int bank) {
65 size_t bankStart = bank * GB_SIZE_CART_BANK0;
66 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
67 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
68 bankStart &= (gb->memory.romSize - 1);
69 }
70 gb->memory.romBase = &gb->memory.rom[bankStart];
71 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
72 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
73 }
74}
75
76void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
77 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
78 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
79 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
80 bankStart &= (gb->memory.romSize - 1);
81 bank = bankStart / GB_SIZE_CART_HALFBANK;
82 if (!bank) {
83 ++bank;
84 }
85 }
86 if (!half) {
87 gb->memory.romBank = &gb->memory.rom[bankStart];
88 gb->memory.currentBank = bank;
89 } else {
90 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
91 gb->memory.mbcState.mbc6.currentBank1 = bank;
92 }
93 if (gb->cpu->pc < GB_BASE_VRAM) {
94 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
95 }
96}
97
98static bool _isMulticart(const uint8_t* mem) {
99 bool success;
100 struct VFile* vf;
101
102 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
103 success = GBIsROM(vf);
104 vf->close(vf);
105
106 if (!success) {
107 return false;
108 }
109
110 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
111 success = GBIsROM(vf);
112 vf->close(vf);
113
114 if (!success) {
115 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
116 success = GBIsROM(vf);
117 vf->close(vf);
118 }
119
120 return success;
121}
122
123static bool _isWisdomTree(const uint8_t* mem, size_t size) {
124 size_t i;
125 for (i = 0x134; i < 0x14C; i += 4) {
126 if (*(uint32_t*) &mem[i] != 0) {
127 return false;
128 }
129 }
130 for (i = 0xF0; i < 0x100; i += 4) {
131 if (*(uint32_t*) &mem[i] != 0) {
132 return false;
133 }
134 }
135 if (mem[0x14D] != 0xE7) {
136 return false;
137 }
138 for (i = 0x300; i < size - 11; ++i) {
139 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
140 return true;
141 }
142 }
143 return false;
144}
145
146void GBMBCSwitchSramBank(struct GB* gb, int bank) {
147 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
148 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
149 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
150 bankStart &= (gb->sramSize - 1);
151 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
152 }
153 gb->memory.sramBank = &gb->memory.sram[bankStart];
154 gb->memory.sramCurrentBank = bank;
155}
156
157void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
158 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
159 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
160 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
161 bankStart &= (gb->sramSize - 1);
162 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
163 }
164 if (!half) {
165 gb->memory.sramBank = &gb->memory.sram[bankStart];
166 gb->memory.sramCurrentBank = bank;
167 } else {
168 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
169 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
170 }
171}
172
173void GBMBCInit(struct GB* gb) {
174 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
175 if (gb->memory.rom) {
176 if (gb->memory.romSize >= 0x8000) {
177 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
178 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
179 cart = cartFooter;
180 }
181 }
182 switch (cart->ramSize) {
183 case 0:
184 gb->sramSize = 0;
185 break;
186 case 1:
187 gb->sramSize = 0x800;
188 break;
189 default:
190 case 2:
191 gb->sramSize = 0x2000;
192 break;
193 case 3:
194 gb->sramSize = 0x8000;
195 break;
196 case 4:
197 gb->sramSize = 0x20000;
198 break;
199 case 5:
200 gb->sramSize = 0x10000;
201 break;
202 }
203
204 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
205 switch (cart->type) {
206 case 0:
207 if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) {
208 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
209 break;
210 }
211 // Fall through
212 case 8:
213 case 9:
214 gb->memory.mbcType = GB_MBC_NONE;
215 break;
216 case 1:
217 case 2:
218 case 3:
219 gb->memory.mbcType = GB_MBC1;
220 break;
221 case 5:
222 case 6:
223 gb->memory.mbcType = GB_MBC2;
224 break;
225 case 0x0B:
226 case 0x0C:
227 case 0x0D:
228 gb->memory.mbcType = GB_MMM01;
229 break;
230 case 0x0F:
231 case 0x10:
232 gb->memory.mbcType = GB_MBC3_RTC;
233 break;
234 case 0x11:
235 case 0x12:
236 case 0x13:
237 gb->memory.mbcType = GB_MBC3;
238 break;
239 default:
240 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
241 // Fall through
242 case 0x19:
243 case 0x1A:
244 case 0x1B:
245 gb->memory.mbcType = GB_MBC5;
246 break;
247 case 0x1C:
248 case 0x1D:
249 case 0x1E:
250 gb->memory.mbcType = GB_MBC5_RUMBLE;
251 break;
252 case 0x20:
253 gb->memory.mbcType = GB_MBC6;
254 break;
255 case 0x22:
256 gb->memory.mbcType = GB_MBC7;
257 break;
258 case 0xFC:
259 gb->memory.mbcType = GB_POCKETCAM;
260 break;
261 case 0xFD:
262 gb->memory.mbcType = GB_TAMA5;
263 break;
264 case 0xFE:
265 gb->memory.mbcType = GB_HuC3;
266 break;
267 case 0xFF:
268 gb->memory.mbcType = GB_HuC1;
269 break;
270 }
271 }
272 } else {
273 gb->memory.mbcType = GB_MBC_NONE;
274 }
275 gb->memory.mbcRead = NULL;
276 switch (gb->memory.mbcType) {
277 case GB_MBC_NONE:
278 gb->memory.mbcWrite = _GBMBCNone;
279 break;
280 case GB_MBC1:
281 gb->memory.mbcWrite = _GBMBC1;
282 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
283 gb->memory.mbcState.mbc1.multicartStride = 4;
284 } else {
285 gb->memory.mbcState.mbc1.multicartStride = 5;
286 }
287 break;
288 case GB_MBC2:
289 gb->memory.mbcWrite = _GBMBC2;
290 gb->memory.mbcRead = _GBMBC2Read;
291 gb->sramSize = 0x100;
292 break;
293 case GB_MBC3:
294 gb->memory.mbcWrite = _GBMBC3;
295 break;
296 default:
297 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
298 // Fall through
299 case GB_MBC5:
300 gb->memory.mbcWrite = _GBMBC5;
301 break;
302 case GB_MBC6:
303 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
304 gb->memory.mbcWrite = _GBMBC6;
305 gb->memory.mbcRead = _GBMBC6Read;
306 break;
307 case GB_MBC7:
308 gb->memory.mbcWrite = _GBMBC7;
309 gb->memory.mbcRead = _GBMBC7Read;
310 gb->sramSize = 0x100;
311 break;
312 case GB_MMM01:
313 gb->memory.mbcWrite = _GBMMM01;
314 break;
315 case GB_HuC1:
316 gb->memory.mbcWrite = _GBHuC1;
317 break;
318 case GB_HuC3:
319 gb->memory.mbcWrite = _GBHuC3;
320 break;
321 case GB_TAMA5:
322 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
323 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
324 gb->memory.mbcWrite = _GBTAMA5;
325 gb->memory.mbcRead = _GBTAMA5Read;
326 gb->sramSize = 0x20;
327 break;
328 case GB_MBC3_RTC:
329 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
330 gb->memory.mbcWrite = _GBMBC3;
331 break;
332 case GB_MBC5_RUMBLE:
333 gb->memory.mbcWrite = _GBMBC5;
334 break;
335 case GB_POCKETCAM:
336 gb->memory.mbcWrite = _GBPocketCam;
337 gb->memory.mbcRead = _GBPocketCamRead;
338 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
339 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
340 }
341 break;
342 case GB_UNL_WISDOM_TREE:
343 gb->memory.mbcWrite = _GBWisdomTree;
344 break;
345 }
346
347 gb->memory.currentBank = 1;
348 gb->memory.sramCurrentBank = 0;
349 gb->memory.sramAccess = false;
350 gb->memory.rtcAccess = false;
351 gb->memory.activeRtcReg = 0;
352 gb->memory.rtcLatched = false;
353 gb->memory.rtcLastLatch = 0;
354 if (gb->memory.rtc) {
355 if (gb->memory.rtc->sample) {
356 gb->memory.rtc->sample(gb->memory.rtc);
357 }
358 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
359 } else {
360 gb->memory.rtcLastLatch = time(0);
361 }
362 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
363
364 GBResizeSram(gb, gb->sramSize);
365
366 if (gb->memory.mbcType == GB_MBC3_RTC) {
367 GBMBCRTCRead(gb);
368 }
369}
370
371static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
372 time_t t;
373 if (rtc) {
374 if (rtc->sample) {
375 rtc->sample(rtc);
376 }
377 t = rtc->unixTime(rtc);
378 } else {
379 t = time(0);
380 }
381 time_t currentLatch = t;
382 t -= *rtcLastLatch;
383 *rtcLastLatch = currentLatch;
384
385 int64_t diff;
386 diff = rtcRegs[0] + t % 60;
387 if (diff < 0) {
388 diff += 60;
389 t -= 60;
390 }
391 rtcRegs[0] = diff % 60;
392 t /= 60;
393 t += diff / 60;
394
395 diff = rtcRegs[1] + t % 60;
396 if (diff < 0) {
397 diff += 60;
398 t -= 60;
399 }
400 rtcRegs[1] = diff % 60;
401 t /= 60;
402 t += diff / 60;
403
404 diff = rtcRegs[2] + t % 24;
405 if (diff < 0) {
406 diff += 24;
407 t -= 24;
408 }
409 rtcRegs[2] = diff % 24;
410 t /= 24;
411 t += diff / 24;
412
413 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
414 rtcRegs[3] = diff;
415 rtcRegs[4] &= 0xFE;
416 rtcRegs[4] |= (diff >> 8) & 1;
417 if (diff & 0x200) {
418 rtcRegs[4] |= 0x80;
419 }
420}
421
422void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
423 struct GBMemory* memory = &gb->memory;
424 int bank = value & 0x1F;
425 int stride = 1 << memory->mbcState.mbc1.multicartStride;
426 switch (address >> 13) {
427 case 0x0:
428 switch (value) {
429 case 0:
430 memory->sramAccess = false;
431 break;
432 case 0xA:
433 memory->sramAccess = true;
434 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
435 break;
436 default:
437 // TODO
438 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
439 break;
440 }
441 break;
442 case 0x1:
443 if (!bank) {
444 ++bank;
445 }
446 bank &= stride - 1;
447 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
448 break;
449 case 0x2:
450 bank &= 3;
451 if (memory->mbcState.mbc1.mode) {
452 GBMBCSwitchBank0(gb, bank << gb->memory.mbcState.mbc1.multicartStride);
453 GBMBCSwitchSramBank(gb, bank);
454 }
455 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
456 break;
457 case 0x3:
458 memory->mbcState.mbc1.mode = value & 1;
459 if (memory->mbcState.mbc1.mode) {
460 GBMBCSwitchBank0(gb, memory->currentBank & ~((1 << memory->mbcState.mbc1.multicartStride) - 1));
461 } else {
462 GBMBCSwitchBank0(gb, 0);
463 GBMBCSwitchSramBank(gb, 0);
464 }
465 break;
466 default:
467 // TODO
468 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
469 break;
470 }
471}
472
473void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
474 struct GBMemory* memory = &gb->memory;
475 int shift = (address & 1) * 4;
476 int bank = value & 0xF;
477 switch (address >> 13) {
478 case 0x0:
479 switch (value) {
480 case 0:
481 memory->sramAccess = false;
482 break;
483 case 0xA:
484 memory->sramAccess = true;
485 break;
486 default:
487 // TODO
488 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
489 break;
490 }
491 break;
492 case 0x1:
493 if (!bank) {
494 ++bank;
495 }
496 GBMBCSwitchBank(gb, bank);
497 break;
498 case 0x5:
499 if (!memory->sramAccess) {
500 return;
501 }
502 address &= 0x1FF;
503 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
504 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
505 break;
506 default:
507 // TODO
508 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
509 break;
510 }
511}
512
513static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
514 address &= 0x1FF;
515 int shift = (address & 1) * 4;
516 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
517}
518
519void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
520 struct GBMemory* memory = &gb->memory;
521 int bank = value;
522 switch (address >> 13) {
523 case 0x0:
524 switch (value) {
525 case 0:
526 memory->sramAccess = false;
527 break;
528 case 0xA:
529 memory->sramAccess = true;
530 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
531 break;
532 default:
533 // TODO
534 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
535 break;
536 }
537 break;
538 case 0x1:
539 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
540 bank &= 0x7F;
541 }
542 if (!bank) {
543 ++bank;
544 }
545 GBMBCSwitchBank(gb, bank);
546 break;
547 case 0x2:
548 if (value < 8) {
549 GBMBCSwitchSramBank(gb, value);
550 memory->rtcAccess = false;
551 } else if (value <= 0xC) {
552 memory->activeRtcReg = value - 8;
553 memory->rtcAccess = true;
554 }
555 break;
556 case 0x3:
557 if (memory->rtcLatched && value == 0) {
558 memory->rtcLatched = false;
559 } else if (!memory->rtcLatched && value == 1) {
560 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
561 memory->rtcLatched = true;
562 }
563 break;
564 }
565}
566
567void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
568 struct GBMemory* memory = &gb->memory;
569 int bank;
570 switch (address >> 12) {
571 case 0x0:
572 case 0x1:
573 switch (value) {
574 case 0:
575 memory->sramAccess = false;
576 break;
577 case 0xA:
578 memory->sramAccess = true;
579 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
580 break;
581 default:
582 // TODO
583 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
584 break;
585 }
586 break;
587 case 0x2:
588 bank = (memory->currentBank & 0x100) | value;
589 GBMBCSwitchBank(gb, bank);
590 break;
591 case 0x3:
592 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
593 GBMBCSwitchBank(gb, bank);
594 break;
595 case 0x4:
596 case 0x5:
597 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
598 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
599 value &= ~8;
600 }
601 GBMBCSwitchSramBank(gb, value & 0xF);
602 break;
603 default:
604 // TODO
605 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
606 break;
607 }
608}
609
610void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
611 struct GBMemory* memory = &gb->memory;
612 int bank = value;
613 switch (address >> 10) {
614 case 0:
615 switch (value) {
616 case 0:
617 memory->mbcState.mbc6.sramAccess = false;
618 break;
619 case 0xA:
620 memory->mbcState.mbc6.sramAccess = true;
621 break;
622 default:
623 // TODO
624 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
625 break;
626 }
627 break;
628 case 0x1:
629 GBMBCSwitchSramHalfBank(gb, 0, bank);
630 break;
631 case 0x2:
632 GBMBCSwitchSramHalfBank(gb, 1, bank);
633 break;
634 case 0x8:
635 case 0x9:
636 GBMBCSwitchHalfBank(gb, 0, bank);
637 break;
638 case 0xC:
639 case 0xD:
640 GBMBCSwitchHalfBank(gb, 1, bank);
641 break;
642 case 0x28:
643 case 0x29:
644 case 0x2A:
645 case 0x2B:
646 if (memory->mbcState.mbc6.sramAccess) {
647 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
648 }
649 break;
650 case 0x2C:
651 case 0x2D:
652 case 0x2E:
653 case 0x2F:
654 if (memory->mbcState.mbc6.sramAccess) {
655 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
656 }
657 break;
658 default:
659 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
660 break;
661 }
662}
663
664uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
665 if (!memory->mbcState.mbc6.sramAccess) {
666 return 0xFF;
667 }
668 switch (address >> 12) {
669 case 0xA:
670 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
671 case 0xB:
672 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
673 }
674 return 0xFF;
675}
676
677void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
678 int bank = value & 0x7F;
679 switch (address >> 13) {
680 case 0x0:
681 switch (value) {
682 default:
683 case 0:
684 gb->memory.mbcState.mbc7.access = 0;
685 break;
686 case 0xA:
687 gb->memory.mbcState.mbc7.access |= 1;
688 break;
689 }
690 break;
691 case 0x1:
692 GBMBCSwitchBank(gb, bank);
693 break;
694 case 0x2:
695 if (value == 0x40) {
696 gb->memory.mbcState.mbc7.access |= 2;
697 } else {
698 gb->memory.mbcState.mbc7.access &= ~2;
699 }
700 break;
701 case 0x5:
702 _GBMBC7Write(&gb->memory, address, value);
703 break;
704 default:
705 // TODO
706 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
707 break;
708 }
709}
710
711uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
712 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
713 if (mbc7->access != 3) {
714 return 0xFF;
715 }
716 switch (address & 0xF0) {
717 case 0x20:
718 if (memory->rotation && memory->rotation->readTiltX) {
719 int32_t x = -memory->rotation->readTiltX(memory->rotation);
720 x >>= 21;
721 x += 0x81D0;
722 return x;
723 }
724 return 0xFF;
725 case 0x30:
726 if (memory->rotation && memory->rotation->readTiltX) {
727 int32_t x = -memory->rotation->readTiltX(memory->rotation);
728 x >>= 21;
729 x += 0x81D0;
730 return x >> 8;
731 }
732 return 7;
733 case 0x40:
734 if (memory->rotation && memory->rotation->readTiltY) {
735 int32_t y = -memory->rotation->readTiltY(memory->rotation);
736 y >>= 21;
737 y += 0x81D0;
738 return y;
739 }
740 return 0xFF;
741 case 0x50:
742 if (memory->rotation && memory->rotation->readTiltY) {
743 int32_t y = -memory->rotation->readTiltY(memory->rotation);
744 y >>= 21;
745 y += 0x81D0;
746 return y >> 8;
747 }
748 return 7;
749 case 0x60:
750 return 0;
751 case 0x80:
752 return mbc7->eeprom;
753 default:
754 return 0xFF;
755 }
756}
757
758static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
759 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
760 if (mbc7->access != 3) {
761 return;
762 }
763 switch (address & 0xF0) {
764 case 0x00:
765 mbc7->latch = (value & 0x55) == 0x55;
766 return;
767 case 0x10:
768 mbc7->latch |= (value & 0xAA);
769 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
770 memory->rotation->sample(memory->rotation);
771 }
772 mbc7->latch = 0;
773 return;
774 default:
775 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
776 return;
777 case 0x80:
778 break;
779 }
780 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
781 value = GBMBC7FieldFillDO(value); // Hi-Z
782 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
783 mbc7->state = GBMBC7_STATE_IDLE;
784 }
785 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
786 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
787 mbc7->sr <<= 1;
788 mbc7->sr |= GBMBC7FieldGetDI(value);
789 ++mbc7->srBits;
790 }
791 switch (mbc7->state) {
792 case GBMBC7_STATE_IDLE:
793 if (GBMBC7FieldIsDI(value)) {
794 mbc7->state = GBMBC7_STATE_READ_COMMAND;
795 mbc7->srBits = 0;
796 mbc7->sr = 0;
797 }
798 break;
799 case GBMBC7_STATE_READ_COMMAND:
800 if (mbc7->srBits == 10) {
801 mbc7->state = 0x10 | (mbc7->sr >> 6);
802 if (mbc7->state & 0xC) {
803 mbc7->state &= ~0x3;
804 }
805 mbc7->srBits = 0;
806 mbc7->address = mbc7->sr & 0x7F;
807 }
808 break;
809 case GBMBC7_STATE_DO:
810 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
811 mbc7->sr <<= 1;
812 --mbc7->srBits;
813 if (!mbc7->srBits) {
814 mbc7->state = GBMBC7_STATE_IDLE;
815 }
816 break;
817 default:
818 break;
819 }
820 switch (mbc7->state) {
821 case GBMBC7_STATE_EEPROM_EWEN:
822 mbc7->writable = true;
823 mbc7->state = GBMBC7_STATE_IDLE;
824 break;
825 case GBMBC7_STATE_EEPROM_EWDS:
826 mbc7->writable = false;
827 mbc7->state = GBMBC7_STATE_IDLE;
828 break;
829 case GBMBC7_STATE_EEPROM_WRITE:
830 if (mbc7->srBits == 16) {
831 if (mbc7->writable) {
832 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
833 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
834 }
835 mbc7->state = GBMBC7_STATE_IDLE;
836 }
837 break;
838 case GBMBC7_STATE_EEPROM_ERASE:
839 if (mbc7->writable) {
840 memory->sram[mbc7->address * 2] = 0xFF;
841 memory->sram[mbc7->address * 2 + 1] = 0xFF;
842 }
843 mbc7->state = GBMBC7_STATE_IDLE;
844 break;
845 case GBMBC7_STATE_EEPROM_READ:
846 mbc7->srBits = 16;
847 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
848 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
849 mbc7->state = GBMBC7_STATE_DO;
850 value = GBMBC7FieldClearDO(value);
851 break;
852 case GBMBC7_STATE_EEPROM_WRAL:
853 if (mbc7->srBits == 16) {
854 if (mbc7->writable) {
855 int i;
856 for (i = 0; i < 128; ++i) {
857 memory->sram[i * 2] = mbc7->sr >> 8;
858 memory->sram[i * 2 + 1] = mbc7->sr;
859 }
860 }
861 mbc7->state = GBMBC7_STATE_IDLE;
862 }
863 break;
864 case GBMBC7_STATE_EEPROM_ERAL:
865 if (mbc7->writable) {
866 int i;
867 for (i = 0; i < 128; ++i) {
868 memory->sram[i * 2] = 0xFF;
869 memory->sram[i * 2 + 1] = 0xFF;
870 }
871 }
872 mbc7->state = GBMBC7_STATE_IDLE;
873 break;
874 default:
875 break;
876 }
877 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
878 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
879 }
880 mbc7->eeprom = value;
881}
882
883void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
884 struct GBMemory* memory = &gb->memory;
885 if (!memory->mbcState.mmm01.locked) {
886 switch (address >> 13) {
887 case 0x0:
888 memory->mbcState.mmm01.locked = true;
889 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
890 break;
891 case 0x1:
892 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
893 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
894 break;
895 case 0x2:
896 memory->mbcState.mmm01.currentBank0 &= ~0x180;
897 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
898 break;
899 default:
900 // TODO
901 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
902 break;
903 }
904 return;
905 }
906 switch (address >> 13) {
907 case 0x0:
908 switch (value) {
909 case 0xA:
910 memory->sramAccess = true;
911 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
912 break;
913 default:
914 memory->sramAccess = false;
915 break;
916 }
917 break;
918 case 0x1:
919 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
920 break;
921 case 0x2:
922 GBMBCSwitchSramBank(gb, value);
923 break;
924 default:
925 // TODO
926 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
927 break;
928 }
929}
930
931void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
932 struct GBMemory* memory = &gb->memory;
933 int bank = value & 0x3F;
934 switch (address >> 13) {
935 case 0x0:
936 switch (value) {
937 case 0xE:
938 memory->sramAccess = false;
939 break;
940 default:
941 memory->sramAccess = true;
942 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
943 break;
944 }
945 break;
946 case 0x1:
947 GBMBCSwitchBank(gb, bank);
948 break;
949 case 0x2:
950 GBMBCSwitchSramBank(gb, value);
951 break;
952 default:
953 // TODO
954 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
955 break;
956 }
957}
958
959void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
960 struct GBMemory* memory = &gb->memory;
961 int bank = value & 0x3F;
962 if (address & 0x1FFF) {
963 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
964 }
965
966 switch (address >> 13) {
967 case 0x0:
968 switch (value) {
969 case 0xA:
970 memory->sramAccess = true;
971 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
972 break;
973 default:
974 memory->sramAccess = false;
975 break;
976 }
977 break;
978 case 0x1:
979 GBMBCSwitchBank(gb, bank);
980 break;
981 case 0x2:
982 GBMBCSwitchSramBank(gb, bank);
983 break;
984 default:
985 // TODO
986 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
987 break;
988 }
989}
990
991void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
992 struct GBMemory* memory = &gb->memory;
993 int bank = value & 0x3F;
994 switch (address >> 13) {
995 case 0x0:
996 switch (value) {
997 case 0:
998 memory->sramAccess = false;
999 break;
1000 case 0xA:
1001 memory->sramAccess = true;
1002 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1003 break;
1004 default:
1005 // TODO
1006 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1007 break;
1008 }
1009 break;
1010 case 0x1:
1011 GBMBCSwitchBank(gb, bank);
1012 break;
1013 case 0x2:
1014 if (value < 0x10) {
1015 GBMBCSwitchSramBank(gb, value);
1016 memory->mbcState.pocketCam.registersActive = false;
1017 } else {
1018 memory->mbcState.pocketCam.registersActive = true;
1019 }
1020 break;
1021 case 0x5:
1022 address &= 0x7F;
1023 if (address == 0 && value & 1) {
1024 value &= 6; // TODO: Timing
1025 _GBPocketCamCapture(memory);
1026 }
1027 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1028 memory->mbcState.pocketCam.registers[address] = value;
1029 }
1030 break;
1031 default:
1032 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1033 break;
1034 }
1035}
1036
1037uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1038 if (memory->mbcState.pocketCam.registersActive) {
1039 if ((address & 0x7F) == 0) {
1040 return memory->mbcState.pocketCam.registers[0];
1041 }
1042 return 0;
1043 }
1044 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1045}
1046
1047void _GBPocketCamCapture(struct GBMemory* memory) {
1048 if (!memory->cam) {
1049 return;
1050 }
1051 const void* image = NULL;
1052 size_t stride;
1053 enum mColorFormat format;
1054 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1055 if (!image) {
1056 return;
1057 }
1058 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1059 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1060 size_t x, y;
1061 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1062 for (x = 0; x < GBCAM_WIDTH; ++x) {
1063 uint32_t gray;
1064 uint32_t color;
1065 switch (format) {
1066 case mCOLOR_XBGR8:
1067 case mCOLOR_XRGB8:
1068 case mCOLOR_ARGB8:
1069 case mCOLOR_ABGR8:
1070 color = ((const uint32_t*) image)[y * stride + x];
1071 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1072 break;
1073 case mCOLOR_BGRX8:
1074 case mCOLOR_RGBX8:
1075 case mCOLOR_RGBA8:
1076 case mCOLOR_BGRA8:
1077 color = ((const uint32_t*) image)[y * stride + x];
1078 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1079 break;
1080 case mCOLOR_BGR5:
1081 case mCOLOR_RGB5:
1082 case mCOLOR_ARGB5:
1083 case mCOLOR_ABGR5:
1084 color = ((const uint16_t*) image)[y * stride + x];
1085 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1086 break;
1087 case mCOLOR_BGR565:
1088 case mCOLOR_RGB565:
1089 color = ((const uint16_t*) image)[y * stride + x];
1090 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1091 break;
1092 case mCOLOR_BGRA5:
1093 case mCOLOR_RGBA5:
1094 color = ((const uint16_t*) image)[y * stride + x];
1095 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1096 break;
1097 default:
1098 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1099 return;
1100 }
1101 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1102 gray = (gray + 1) * exposure / 0x300;
1103 // TODO: Additional processing
1104 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1105 if (gray < pocketCam->registers[matrixEntry + 6]) {
1106 gray = 0x101;
1107 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1108 gray = 0x100;
1109 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1110 gray = 0x001;
1111 } else {
1112 gray = 0;
1113 }
1114 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1115 uint16_t existing;
1116 LOAD_16LE(existing, coord + 0x100, memory->sram);
1117 existing |= gray << (7 - (x & 7));
1118 STORE_16LE(existing, coord + 0x100, memory->sram);
1119 }
1120 }
1121}
1122
1123void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1124 struct GBMemory* memory = &gb->memory;
1125 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1126 switch (address >> 13) {
1127 case 0x5:
1128 if (address & 1) {
1129 tama5->reg = value;
1130 } else {
1131 value &= 0xF;
1132 if (tama5->reg < GBTAMA5_MAX) {
1133 tama5->registers[tama5->reg] = value;
1134 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1135 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1136 switch (tama5->reg) {
1137 case GBTAMA5_BANK_LO:
1138 case GBTAMA5_BANK_HI:
1139 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1140 break;
1141 case GBTAMA5_WRITE_LO:
1142 case GBTAMA5_WRITE_HI:
1143 case GBTAMA5_CS:
1144 break;
1145 case GBTAMA5_ADDR_LO:
1146 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1147 case 0x0: // RAM write
1148 memory->sram[address] = out;
1149 break;
1150 case 0x1: // RAM read
1151 break;
1152 default:
1153 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1154 }
1155 break;
1156 default:
1157 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1158 break;
1159 }
1160 } else {
1161 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1162 }
1163 }
1164 break;
1165 default:
1166 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1167 }
1168}
1169
1170uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1171 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1172 if ((address & 0x1FFF) > 1) {
1173 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1174 }
1175 if (address & 1) {
1176 return 0xFF;
1177 } else {
1178 uint8_t value = 0xF0;
1179 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1180 switch (tama5->reg) {
1181 case GBTAMA5_ACTIVE:
1182 return 0xF1;
1183 case GBTAMA5_READ_LO:
1184 case GBTAMA5_READ_HI:
1185 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1186 case 1:
1187 value = memory->sram[address];
1188 break;
1189 default:
1190 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1191 break;
1192 }
1193 if (tama5->reg == GBTAMA5_READ_HI) {
1194 value >>= 4;
1195 }
1196 value |= 0xF0;
1197 return value;
1198 default:
1199 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1200 return 0xF1;
1201 }
1202 }
1203}
1204
1205void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1206 UNUSED(value);
1207 int bank = address & 0x3F;
1208 switch (address >> 14) {
1209 case 0x0:
1210 GBMBCSwitchBank0(gb, bank * 2);
1211 GBMBCSwitchBank(gb, bank * 2 + 1);
1212 break;
1213 default:
1214 // TODO
1215 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1216 break;
1217 }
1218}
1219
1220void GBMBCRTCRead(struct GB* gb) {
1221 struct GBMBCRTCSaveBuffer rtcBuffer;
1222 struct VFile* vf = gb->sramVf;
1223 if (!vf) {
1224 return;
1225 }
1226 vf->seek(vf, gb->sramSize, SEEK_SET);
1227 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1228 return;
1229 }
1230
1231 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1232 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1233 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1234 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1235 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1236 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1237}
1238
1239void GBMBCRTCWrite(struct GB* gb) {
1240 struct VFile* vf = gb->sramVf;
1241 if (!vf) {
1242 return;
1243 }
1244
1245 uint8_t rtcRegs[5];
1246 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1247 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1248 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1249
1250 struct GBMBCRTCSaveBuffer rtcBuffer;
1251 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1252 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1253 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1254 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1255 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1256 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1257 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1258 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1259 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1260 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1261 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1262
1263 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1264 // Writing past the end of the file can invalidate the file mapping
1265 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1266 gb->memory.sram = NULL;
1267 }
1268 vf->seek(vf, gb->sramSize, SEEK_SET);
1269 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1270 if (!gb->memory.sram) {
1271 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1272 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1273 }
1274}