1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include "util/common.h"
 10
 11#include "core/log.h"
 12
 13#include "lr35902/lr35902.h"
 14
 15mLOG_DECLARE_CATEGORY(GB_MBC);
 16mLOG_DECLARE_CATEGORY(GB_MEM);
 17
 18struct GB;
 19
 20enum {
 21	GB_BASE_CART_BANK0 = 0x0000,
 22	GB_BASE_CART_BANK1 = 0x4000,
 23	GB_BASE_VRAM = 0x8000,
 24	GB_BASE_EXTERNAL_RAM = 0xA000,
 25	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 26	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 27	GB_BASE_OAM = 0xFE00,
 28	GB_BASE_UNUSABLE = 0xFEA0,
 29	GB_BASE_IO = 0xFF00,
 30	GB_BASE_HRAM = 0xFF80,
 31	GB_BASE_IE = 0xFFFF
 32};
 33
 34enum {
 35	GB_REGION_CART_BANK0 = 0x0,
 36	GB_REGION_CART_BANK1 = 0x4,
 37	GB_REGION_VRAM = 0x8,
 38	GB_REGION_EXTERNAL_RAM = 0xA,
 39	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 40	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 41	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 42	GB_REGION_OTHER = 0xF,
 43};
 44
 45enum {
 46	GB_SIZE_CART_BANK0 = 0x4000,
 47	GB_SIZE_VRAM = 0x4000,
 48	GB_SIZE_VRAM_BANK0 = 0x2000,
 49	GB_SIZE_EXTERNAL_RAM = 0x2000,
 50	GB_SIZE_WORKING_RAM = 0x8000,
 51	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 52	GB_SIZE_OAM = 0xA0,
 53	GB_SIZE_IO = 0x80,
 54	GB_SIZE_HRAM = 0x7F,
 55};
 56
 57enum GBMemoryBankControllerType {
 58	GB_MBC_NONE = 0,
 59	GB_MBC1 = 1,
 60	GB_MBC2 = 2,
 61	GB_MBC3 = 3,
 62	GB_MBC5 = 5,
 63	GB_MBC6 = 6,
 64	GB_MBC7 = 7,
 65	GB_MMM01 = 0x10,
 66	GB_HuC1 = 0x11,
 67	GB_HuC3 = 0x12,
 68};
 69
 70struct GBMemory;
 71typedef void (*GBMemoryBankController)(struct GBMemory*, uint16_t address, uint8_t value);
 72
 73DECL_BITFIELD(GBMBC7Field, uint8_t);
 74DECL_BIT(GBMBC7Field, SK, 6);
 75DECL_BIT(GBMBC7Field, CS, 7);
 76DECL_BIT(GBMBC7Field, IO, 1);
 77
 78enum GBMBC7MachineState {
 79	GBMBC7_STATE_NULL = -1,
 80	GBMBC7_STATE_IDLE = 0,
 81	GBMBC7_STATE_READ_COMMAND = 1,
 82	GBMBC7_STATE_READ_ADDRESS = 2,
 83	GBMBC7_STATE_COMMAND_0 = 3,
 84	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 85	GBMBC7_STATE_COMMAND_SR_READ = 5,
 86	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 87	GBMBC7_STATE_READ = 7,
 88	GBMBC7_STATE_WRITE = 8,
 89};
 90
 91struct GBMBC7State {
 92	enum GBMBC7MachineState state;
 93	uint32_t sr;
 94	uint8_t address;
 95	bool writable;
 96	int srBits;
 97	int command;
 98	GBMBC7Field field;
 99};
100
101union GBMBCState {
102	struct GBMBC7State mbc7;
103};
104
105struct mRotationSource;
106struct GBMemory {
107	uint8_t* rom;
108	uint8_t* romBank;
109	enum GBMemoryBankControllerType mbcType;
110	GBMemoryBankController mbc;
111	union GBMBCState mbcState;
112	int currentBank;
113
114	uint8_t* wram;
115	uint8_t* wramBank;
116	int wramCurrentBank;
117
118	bool sramAccess;
119	uint8_t* sram;
120	uint8_t* sramBank;
121	int sramCurrentBank;
122
123	uint8_t io[GB_SIZE_IO];
124	bool ime;
125	uint8_t ie;
126
127	uint8_t hram[GB_SIZE_HRAM];
128
129	int32_t dmaNext;
130	uint16_t dmaSource;
131	uint16_t dmaDest;
132	int dmaRemaining;
133
134	int32_t hdmaNext;
135	uint16_t hdmaSource;
136	uint16_t hdmaDest;
137	int hdmaRemaining;
138	bool isHdma;
139
140	size_t romSize;
141
142	bool rtcAccess;
143	int activeRtcReg;
144	int rtcLatched;
145	uint8_t rtcRegs[5];
146	struct mRTCSource* rtc;
147	struct mRotationSource* rotation;
148};
149
150void GBMemoryInit(struct GB* gb);
151void GBMemoryDeinit(struct GB* gb);
152
153void GBMemoryReset(struct GB* gb);
154void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
155
156uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
157void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
158
159int32_t GBMemoryProcessEvents(struct GB* gb, int32_t cycles);
160void GBMemoryDMA(struct GB* gb, uint16_t base);
161void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
162
163uint8_t GBDMALoad8(struct LR35902Core* cpu, uint16_t address);
164void GBDMAStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
165
166uint16_t GBView16(struct LR35902Core* cpu, uint16_t address);
167uint8_t GBView8(struct LR35902Core* cpu, uint16_t address);
168
169void GBPatch16(struct LR35902Core* cpu, uint16_t address, int16_t value, int16_t* old);
170void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old);
171
172#endif