include/mgba/internal/ds/io.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef DS_IO_H
7#define DS_IO_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/log.h>
14
15enum DSIORegisters {
16 // Video
17 DS_REG_DISPSTAT = 0x004,
18 DS_REG_VCOUNT = 0x006,
19
20 // DMA
21 DS_REG_DMA0SAD_LO = 0x0B0,
22 DS_REG_DMA0SAD_HI = 0x0B2,
23 DS_REG_DMA0DAD_LO = 0x0B4,
24 DS_REG_DMA0DAD_HI = 0x0B6,
25 DS_REG_DMA0CNT_LO = 0x0B8,
26 DS_REG_DMA0CNT_HI = 0x0BA,
27 DS_REG_DMA1SAD_LO = 0x0BC,
28 DS_REG_DMA1SAD_HI = 0x0BE,
29 DS_REG_DMA1DAD_LO = 0x0C0,
30 DS_REG_DMA1DAD_HI = 0x0C2,
31 DS_REG_DMA1CNT_LO = 0x0C4,
32 DS_REG_DMA1CNT_HI = 0x0C6,
33 DS_REG_DMA2SAD_LO = 0x0C8,
34 DS_REG_DMA2SAD_HI = 0x0CA,
35 DS_REG_DMA2DAD_LO = 0x0CC,
36 DS_REG_DMA2DAD_HI = 0x0CE,
37 DS_REG_DMA2CNT_LO = 0x0D0,
38 DS_REG_DMA2CNT_HI = 0x0D2,
39 DS_REG_DMA3SAD_LO = 0x0D4,
40 DS_REG_DMA3SAD_HI = 0x0D6,
41 DS_REG_DMA3DAD_LO = 0x0D8,
42 DS_REG_DMA3DAD_HI = 0x0DA,
43 DS_REG_DMA3CNT_LO = 0x0DC,
44 DS_REG_DMA3CNT_HI = 0x0DE,
45 DS_REG_DMA0FILL_LO = 0x0E0,
46 DS_REG_DMA0FILL_HI = 0x0E2,
47 DS_REG_DMA1FILL_LO = 0x0E4,
48 DS_REG_DMA1FILL_HI = 0x0E6,
49 DS_REG_DMA2FILL_LO = 0x0E8,
50 DS_REG_DMA2FILL_HI = 0x0EA,
51 DS_REG_DMA3FILL_LO = 0x0EC,
52 DS_REG_DMA3FILL_HI = 0x0EE,
53
54 // Timers
55 DS_REG_TM0CNT_LO = 0x100,
56 DS_REG_TM0CNT_HI = 0x102,
57 DS_REG_TM1CNT_LO = 0x104,
58 DS_REG_TM1CNT_HI = 0x106,
59 DS_REG_TM2CNT_LO = 0x108,
60 DS_REG_TM2CNT_HI = 0x10A,
61 DS_REG_TM3CNT_LO = 0x10C,
62 DS_REG_TM3CNT_HI = 0x10E,
63
64 // Keypad
65 DS_REG_KEYINPUT = 0x130,
66 DS_REG_KEYCNT = 0x132,
67
68 // IPC
69 DS_REG_IPCSYNC = 0x180,
70 DS_REG_IPCFIFOCNT = 0x184,
71 DS_REG_IPCFIFOSEND_LO = 0x188,
72 DS_REG_IPCFIFOSEND_HI = 0x18A,
73 DS_REG_IPCFIFORECV_LO = 0x100000,
74 DS_REG_IPCFIFORECV_HI = 0x100002,
75
76 // Game card
77 DS_REG_AUXSPICNT = 0x1A0,
78 DS_REG_AUXSPIDATA = 0x1A2,
79 DS_REG_SLOT1CNT_LO = 0x1A4,
80 DS_REG_SLOT1CNT_HI = 0x1A6,
81 DS_REG_SLOT1CMD_0 = 0x1A8,
82 DS_REG_SLOT1CMD_1 = 0x1A9,
83 DS_REG_SLOT1CMD_2 = 0x1AA,
84 DS_REG_SLOT1CMD_3 = 0x1AB,
85 DS_REG_SLOT1CMD_4 = 0x1AC,
86 DS_REG_SLOT1CMD_5 = 0x1AD,
87 DS_REG_SLOT1CMD_6 = 0x1AE,
88 DS_REG_SLOT1CMD_7 = 0x1AF,
89 DS_REG_SLOT1DATA_0 = 0x100010,
90 DS_REG_SLOT1DATA_1 = 0x100011,
91 DS_REG_SLOT1DATA_2 = 0x100012,
92 DS_REG_SLOT1DATA_3 = 0x100013,
93
94 // Interrupts
95 DS_REG_IME = 0x208,
96 DS_REG_IE_LO = 0x210,
97 DS_REG_IE_HI = 0x212,
98 DS_REG_IF_LO = 0x214,
99 DS_REG_IF_HI = 0x216,
100
101 DS_REG_POSTFLG = 0x300,
102};
103
104enum DS7IORegisters {
105 // Keypad
106 DS7_REG_EXTKEYIN = 0x136,
107 DS7_REG_RTC = 0x138,
108
109 // SPI
110 DS7_REG_SPICNT = 0x1C0,
111 DS7_REG_SPIDATA = 0x1C2,
112
113 // Etc
114 DS7_REG_EXMEMSTAT = 0x204,
115
116 // Memory control
117 DS7_REG_VRAMSTAT = 0x240,
118 DS7_REG_WRAMSTAT = 0x241,
119 DS7_REG_HALTCNT = 0x301,
120 DS7_REG_POWCNT2 = 0x304,
121 DS7_REG_BIOSPROT_LO = 0x308,
122 DS7_REG_BIOSPROT_HI = 0x30A,
123
124 DS7_REG_MAX = 0x51E,
125};
126
127enum DS9IORegisters {
128 // Video
129 DS9_REG_A_DISPCNT_LO = 0x000,
130 DS9_REG_A_DISPCNT_HI = 0x002,
131 DS9_REG_A_BG0CNT = 0x008,
132 DS9_REG_A_BG1CNT = 0x00A,
133 DS9_REG_A_BG2CNT = 0x00C,
134 DS9_REG_A_BG3CNT = 0x00E,
135 DS9_REG_A_BG0HOFS = 0x010,
136 DS9_REG_A_BG0VOFS = 0x012,
137 DS9_REG_A_BG1HOFS = 0x014,
138 DS9_REG_A_BG1VOFS = 0x016,
139 DS9_REG_A_BG2HOFS = 0x018,
140 DS9_REG_A_BG2VOFS = 0x01A,
141 DS9_REG_A_BG3HOFS = 0x01C,
142 DS9_REG_A_BG3VOFS = 0x01E,
143 DS9_REG_A_BG2PA = 0x020,
144 DS9_REG_A_BG2PB = 0x022,
145 DS9_REG_A_BG2PC = 0x024,
146 DS9_REG_A_BG2PD = 0x026,
147 DS9_REG_A_BG2X_LO = 0x028,
148 DS9_REG_A_BG2X_HI = 0x02A,
149 DS9_REG_A_BG2Y_LO = 0x02C,
150 DS9_REG_A_BG2Y_HI = 0x02E,
151 DS9_REG_A_BG3PA = 0x030,
152 DS9_REG_A_BG3PB = 0x032,
153 DS9_REG_A_BG3PC = 0x034,
154 DS9_REG_A_BG3PD = 0x036,
155 DS9_REG_A_BG3X_LO = 0x038,
156 DS9_REG_A_BG3X_HI = 0x03A,
157 DS9_REG_A_BG3Y_LO = 0x03C,
158 DS9_REG_A_BG3Y_HI = 0x03E,
159 DS9_REG_A_WIN0H = 0x040,
160 DS9_REG_A_WIN1H = 0x042,
161 DS9_REG_A_WIN0V = 0x044,
162 DS9_REG_A_WIN1V = 0x046,
163 DS9_REG_A_WININ = 0x048,
164 DS9_REG_A_WINOUT = 0x04A,
165 DS9_REG_A_MOSAIC = 0x04C,
166 DS9_REG_A_BLDCNT = 0x050,
167 DS9_REG_A_BLDALPHA = 0x052,
168 DS9_REG_A_BLDY = 0x054,
169 DS9_REG_DISP3DCNT = 0x060,
170 DS9_REG_DISPCAPCNT_LO = 0x064,
171 DS9_REG_DISPCAPCNT_HI = 0x066,
172 DS9_REG_DISP_MMEM_FIFO_LO = 0x068,
173 DS9_REG_DISP_MMEM_FIFO_HI = 0x06A,
174 DS9_REG_A_MASTER_BRIGHT = 0x06C,
175
176 DS9_REG_B_DISPCNT_LO = 0x1000,
177 DS9_REG_B_DISPCNT_HI = 0x1002,
178 DS9_REG_B_BG0CNT = 0x1008,
179 DS9_REG_B_BG1CNT = 0x100A,
180 DS9_REG_B_BG2CNT = 0x100C,
181 DS9_REG_B_BG3CNT = 0x100E,
182 DS9_REG_B_BG0HOFS = 0x1010,
183 DS9_REG_B_BG0VOFS = 0x1012,
184 DS9_REG_B_BG1HOFS = 0x1014,
185 DS9_REG_B_BG1VOFS = 0x1016,
186 DS9_REG_B_BG2HOFS = 0x1018,
187 DS9_REG_B_BG2VOFS = 0x101A,
188 DS9_REG_B_BG3HOFS = 0x101C,
189 DS9_REG_B_BG3VOFS = 0x101E,
190 DS9_REG_B_BG2PA = 0x1020,
191 DS9_REG_B_BG2PB = 0x1022,
192 DS9_REG_B_BG2PC = 0x1024,
193 DS9_REG_B_BG2PD = 0x1026,
194 DS9_REG_B_BG2X_LO = 0x1028,
195 DS9_REG_B_BG2X_HI = 0x102A,
196 DS9_REG_B_BG2Y_LO = 0x102C,
197 DS9_REG_B_BG2Y_HI = 0x102E,
198 DS9_REG_B_BG3PA = 0x1030,
199 DS9_REG_B_BG3PB = 0x1032,
200 DS9_REG_B_BG3PC = 0x1034,
201 DS9_REG_B_BG3PD = 0x1036,
202 DS9_REG_B_BG3X_LO = 0x1038,
203 DS9_REG_B_BG3X_HI = 0x103A,
204 DS9_REG_B_BG3Y_LO = 0x103C,
205 DS9_REG_B_BG3Y_HI = 0x103E,
206 DS9_REG_B_WIN0H = 0x1040,
207 DS9_REG_B_WIN1H = 0x1042,
208 DS9_REG_B_WIN0V = 0x1044,
209 DS9_REG_B_WIN1V = 0x1046,
210 DS9_REG_B_WININ = 0x1048,
211 DS9_REG_B_WINOUT = 0x104A,
212 DS9_REG_B_MOSAIC = 0x104C,
213 DS9_REG_B_BLDCNT = 0x1050,
214 DS9_REG_B_BLDALPHA = 0x1052,
215 DS9_REG_B_BLDY = 0x1054,
216 DS9_REG_B_MASTER_BRIGHT = 0x106C,
217
218 // Etc
219 DS9_REG_EXMEMCNT = 0x204,
220
221 // Memory control
222 DS9_REG_VRAMCNT_A = 0x240,
223 DS9_REG_VRAMCNT_B = 0x241,
224 DS9_REG_VRAMCNT_C = 0x242,
225 DS9_REG_VRAMCNT_D = 0x243,
226 DS9_REG_VRAMCNT_E = 0x244,
227 DS9_REG_VRAMCNT_F = 0x245,
228 DS9_REG_VRAMCNT_G = 0x246,
229 DS9_REG_WRAMCNT = 0x247,
230 DS9_REG_VRAMCNT_H = 0x248,
231 DS9_REG_VRAMCNT_I = 0x249,
232
233 // Math
234 DS9_REG_DIVCNT = 0x280,
235 DS9_REG_DIV_NUMER_0 = 0x290,
236 DS9_REG_DIV_NUMER_1 = 0x292,
237 DS9_REG_DIV_NUMER_2 = 0x294,
238 DS9_REG_DIV_NUMER_3 = 0x296,
239 DS9_REG_DIV_DENOM_0 = 0x298,
240 DS9_REG_DIV_DENOM_1 = 0x29A,
241 DS9_REG_DIV_DENOM_2 = 0x29C,
242 DS9_REG_DIV_DENOM_3 = 0x29E,
243 DS9_REG_DIV_RESULT_0 = 0x2A0,
244 DS9_REG_DIV_RESULT_1 = 0x2A2,
245 DS9_REG_DIV_RESULT_2 = 0x2A4,
246 DS9_REG_DIV_RESULT_3 = 0x2A6,
247 DS9_REG_DIVREM_RESULT_0 = 0x2A8,
248 DS9_REG_DIVREM_RESULT_1 = 0x2AA,
249 DS9_REG_DIVREM_RESULT_2 = 0x2AC,
250 DS9_REG_DIVREM_RESULT_3 = 0x2AE,
251 DS9_REG_SQRTCNT = 0x2B0,
252 DS9_REG_SQRT_RESULT_LO = 0x2B4,
253 DS9_REG_SQRT_RESULT_HI = 0x2B6,
254 DS9_REG_SQRT_PARAM_0 = 0x2B8,
255 DS9_REG_SQRT_PARAM_1 = 0x2BA,
256 DS9_REG_SQRT_PARAM_2 = 0x2BC,
257 DS9_REG_SQRT_PARAM_3 = 0x2BE,
258
259 DS9_REG_MAX = 0x106E,
260
261 DS9_REG_POWCNT1 = 0x304,
262};
263
264mLOG_DECLARE_CATEGORY(DS_IO);
265
266extern const char* const DS7IORegisterNames[];
267extern const char* const DS9IORegisterNames[];
268
269struct DS;
270void DS7IOInit(struct DS* ds);
271void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value);
272void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
273void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
274uint16_t DS7IORead(struct DS* ds, uint32_t address);
275uint32_t DS7IORead32(struct DS* ds, uint32_t address);
276
277void DS9IOInit(struct DS* ds);
278void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value);
279void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
280void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
281uint16_t DS9IORead(struct DS* ds, uint32_t address);
282uint32_t DS9IORead32(struct DS* ds, uint32_t address);
283
284CXX_GUARD_END
285
286#endif