1#ifndef GBA_SERIALIZE_H
  2#define GBA_SERIALIZE_H
  3
  4#include "common.h"
  5
  6#include "gba.h"
  7
  8const uint32_t GBA_SAVESTATE_MAGIC;
  9
 10/* Savestate format:
 11 * 0x00000 - 0x00003: Version Magic (0x01000000)
 12 * 0x00004 - 0x00007: BIOS checksum (e.g. 0xBAAE187F for official BIOS)
 13 * 0x00008 - 0x0000F: Reserved (leave zero)
 14 * 0x00010 - 0x0001B: Game title (e.g. METROID4USA)
 15 * 0x0001C - 0x0001F: Game code (e.g. AMTE)
 16 * 0x00020 - 0x0012F: CPU state:
 17 * | 0x00020 - 0x0005F: GPRs
 18 * | 0x00060 - 0x00063: CPSR
 19 * | 0x00064 - 0x00067: SPSR
 20 * | 0x00068 - 0x0006B: Cycles since last event
 21 * | 0x0006C - 0x0006F: Cycles until next event
 22 * | 0x00070 - 0x00117: Banked registers
 23 * | 0x00118 - 0x0012F: Banked SPSRs
 24 * 0x00130 - 0x00143: Audio channel 1 state
 25 * | 0x00130 - 0x00133: Next envelope step
 26 * | 0x00134 - 0x00137: Next square wave step
 27 * | 0x00138 - 0x0013B: Next sweep step
 28 * | 0x0013C - 0x0013F: Channel end cycle
 29 * | 0x00140 - 0x00143: Next event
 30 * 0x00144 - 0x00153: Audio channel 2 state
 31 * | 0x00144 - 0x00147: Next envelope step
 32 * | 0x00148 - 0x0014B: Next square wave step
 33 * | 0x0014C - 0x0014F: Channel end cycle
 34 * | 0x00150 - 0x00153: Next event
 35 * 0x00154 - 0x0017B: Audio channel 3 state
 36 * | 0x00154 - 0x00173: Wave banks
 37 * | 0x00174 - 0x00177: Channel end cycle
 38 * | 0x00178 - 0x0017B: Next event
 39 * 0x0017C - 0x0018B: Audio channel 4 state
 40 * | 0x0017C - 0x0017F: Linear feedback shift register state
 41 * | 0x00180 - 0x00183: Next enveleope step
 42 * | 0x00184 - 0x00187: Channel end cycle
 43 * | 0x00188 - 0x0018B: Next event
 44 * 0x0018C - 0x001AB: Audio FIFO 1
 45 * 0x001AC - 0x001CB: Audio FIFO 2
 46 * 0x001CC - 0x001DF: Audio miscellaneous state
 47 * | 0x001CC - 0x001CF: Next event
 48 * | 0x001D0 - 0x001D3: Event diff
 49 * | 0x001D4 - 0x001D7: Next sample
 50 * | 0x001D8 - 0x001DB: FIFO size
 51 * | 0x001DC - 0x001DC: Channel 1 envelope state
 52 *   | bits 0 - 3: Current volume
 53 *   | bit 4: Is dead?
 54 *   | bit 5: Is high?
 55 *   | bits 6 - 7: Reserved
 56 * | 0x001DD - 0x001DD: Channel 2 envelope state
 57 *   | bits 0 - 3: Current volume
 58 *   | bit 4: Is dead?
 59 *   | bit 5: Is high?
 60 *   | bits 6 - 7: Reserved
 61 * | 0x001DE - 0x001DE: Channel 4 envelope state
 62 *   | bits 0 - 3: Current volume
 63 *   | bit 4: Is dead?
 64 *   | bits 5 - 7: Reserved
 65 * | 0x001DF - 0x001DF: Reserved
 66 * 0x001E0 - 0x001FF: Video miscellaneous state
 67 * | 0x001E0 - 0x001E3: Next event
 68 * | 0x001E4 - 0x001E7: Event diff
 69 * | 0x001E8 - 0x001EB: Last hblank
 70 * | 0x001EC - 0x001EF: Next hblank
 71 * | 0x001F0 - 0x001F3: Next hblank IRQ
 72 * | 0x001F4 - 0x001F7: Next vblank IRQ
 73 * | 0x001F8 - 0x001FB: Next vcounter IRQ
 74 * | 0x001FC - 0x001FF: Reserved
 75 * 0x00200 - 0x00213: Timer 0
 76 * | 0x00200 - 0x00201: Reload value
 77 * | 0x00202 - 0x00203: Old reload value
 78 * | 0x00204 - 0x00207: Last event
 79 * | 0x00208 - 0x0020B: Next event
 80 * | 0x0020C - 0x0020F: Overflow interval
 81 * | 0x00210 - 0x00213: Miscellaenous flags
 82 * 0x00214 - 0x00227: Timer 1
 83 * | 0x00214 - 0x00215: Reload value
 84 * | 0x00216 - 0x00217: Old reload value
 85 * | 0x00218 - 0x0021B: Last event
 86 * | 0x0021C - 0x0021F: Next event
 87 * | 0x00220 - 0x00223: Overflow interval
 88 * | 0x00224 - 0x00227: Miscellaenous flags
 89 * 0x00228 - 0x0023B: Timer 2
 90 * | 0x00228 - 0x00229: Reload value
 91 * | 0x0022A - 0x0022B: Old reload value
 92 * | 0x0022C - 0x0022F: Last event
 93 * | 0x00230 - 0x00233: Next event
 94 * | 0x00234 - 0x00237: Overflow interval
 95 * | 0x00238 - 0x0023B: Miscellaenous flags
 96 * 0x0023C - 0x00250: Timer 3
 97 * | 0x0023C - 0x0023D: Reload value
 98 * | 0x0023E - 0x0023F: Old reload value
 99 * | 0x00240 - 0x00243: Last event
100 * | 0x00244 - 0x00247: Next event
101 * | 0x00248 - 0x0024B: Overflow interval
102 * | 0x0024C - 0x0024F: Miscellaenous flags
103 * 0x00250 - 0x0025F: DMA 0
104 * | 0x00250 - 0x00253: DMA next source
105 * | 0x00254 - 0x00257: DMA next destination
106 * | 0x00258 - 0x0025B: DMA next count
107 * | 0x0025C - 0x0025F: DMA next event
108 * 0x00260 - 0x0026F: DMA 1
109 * | 0x00260 - 0x00263: DMA next source
110 * | 0x00264 - 0x00267: DMA next destination
111 * | 0x00268 - 0x0026B: DMA next count
112 * | 0x0026C - 0x0026F: DMA next event
113 * 0x00270 - 0x0027F: DMA 2
114 * | 0x00270 - 0x00273: DMA next source
115 * | 0x00274 - 0x00277: DMA next destination
116 * | 0x00278 - 0x0027B: DMA next count
117 * | 0x0027C - 0x0027F: DMA next event
118 * 0x00280 - 0x0028F: DMA 3
119 * | 0x00280 - 0x00283: DMA next source
120 * | 0x00284 - 0x00287: DMA next destination
121 * | 0x00288 - 0x0028B: DMA next count
122 * | 0x0028C - 0x0028F: DMA next event
123 * 0x00290 - 0x003FF: Reserved (leave zero)
124 * 0x00400 - 0x007FF: I/O memory
125 * 0x00800 - 0x00BFF: Palette
126 * 0x00C00 - 0x00FFF: OAM
127 * 0x01000 - 0x18FFF: VRAM
128 * 0x19000 - 0x20FFF: IWRAM
129 * 0x21000 - 0x60FFF: WRAM
130 * Total size: 0x61000 (397,312) bytes
131 */
132
133struct GBASerializedState {
134	uint32_t versionMagic;
135	uint32_t biosChecksum;
136	uint32_t reservedHeader[2];
137
138	char title[12];
139	uint32_t id;
140
141	struct {
142		int32_t gprs[16];
143		union PSR cpsr;
144		union PSR spsr;
145
146		int32_t cycles;
147		int32_t nextEvent;
148
149		int32_t bankedRegisters[6][7];
150		int32_t bankedSPSRs[6];
151	} cpu;
152
153	struct {
154		struct {
155			int32_t envelopeNextStep;
156			int32_t waveNextStep;
157			int32_t sweepNextStep;
158			int32_t endTime;
159			int32_t nextEvent;
160		} ch1;
161		struct {
162			int32_t envelopeNextStep;
163			int32_t waveNextStep;
164			int32_t endTime;
165			int32_t nextEvent;
166		} ch2;
167		struct {
168			uint32_t wavebanks[8];
169			int32_t endTime;
170			int32_t nextEvent;
171		} ch3;
172		struct {
173			int32_t lfsr;
174			int32_t envelopeNextStep;
175			int32_t endTime;
176			int32_t nextEvent;
177		} ch4;
178		uint32_t fifoA[8];
179		uint32_t fifoB[8];
180		int32_t nextEvent;
181		int32_t eventDiff;
182		int32_t nextSample;
183		int32_t fifoSize;
184		unsigned ch1Volume : 4;
185		unsigned ch1Dead : 1;
186		unsigned ch1Hi : 1;
187		unsigned : 2;
188		unsigned ch2Volume : 4;
189		unsigned ch2Dead : 1;
190		unsigned ch2Hi : 1;
191		unsigned : 2;
192		unsigned ch4Volume : 4;
193		unsigned ch4Dead : 1;
194		unsigned : 3;
195		unsigned : 8;
196	} audio;
197
198	struct {
199		int32_t nextEvent;
200		int32_t eventDiff;
201		int32_t lastHblank;
202		int32_t nextHblank;
203		int32_t nextHblankIRQ;
204		int32_t nextVblankIRQ;
205		int32_t nextVcounterIRQ;
206		int32_t : 32;
207	} video;
208
209	struct GBATimer timers[4];
210
211	struct {
212		uint32_t nextSource;
213		uint32_t nextDest;
214		int32_t nextCount;
215		int32_t nextEvent;
216	} dma[4];
217
218	uint32_t reservedGpio[92];
219
220	uint16_t io[SIZE_IO >> 1];
221	uint16_t pram[SIZE_PALETTE_RAM >> 1];
222	uint16_t oam[SIZE_OAM >> 1];
223	uint16_t vram[SIZE_VRAM >> 1];
224	uint8_t iwram[SIZE_WORKING_IRAM];
225	uint8_t wram[SIZE_WORKING_RAM];
226};
227
228void GBASerialize(struct GBA* gba, struct GBASerializedState* state);
229void GBADeserialize(struct GBA* gba, struct GBASerializedState* state);
230
231int GBASaveState(struct GBA* gba, int slot);
232int GBALoadState(struct GBA* gba, int slot);
233
234struct GBASerializedState* GBAMapState(int fd);
235struct GBASerializedState* GBAAllocateState(void);
236void GBADeallocateState(struct GBASerializedState* state);
237
238struct GBAThread;
239void GBARecordFrame(struct GBAThread* thread);
240void GBARewind(struct GBAThread* thread, int nStates);
241
242#endif