src/arm/isa-arm.c (view raw)
1#include "isa-arm.h"
2
3#include "arm.h"
4#include "isa-inlines.h"
5
6enum {
7 PSR_USER_MASK = 0xF0000000,
8 PSR_PRIV_MASK = 0x000000CF,
9 PSR_STATE_MASK = 0x00000020
10};
11
12// Addressing mode 1
13static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
14 int rm = opcode & 0x0000000F;
15 int immediate = (opcode & 0x00000F80) >> 7;
16 if (!immediate) {
17 cpu->shifterOperand = cpu->gprs[rm];
18 cpu->shifterCarryOut = cpu->cpsr.c;
19 } else {
20 cpu->shifterOperand = cpu->gprs[rm] << immediate;
21 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
22 }
23}
24
25static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
26 int rm = opcode & 0x0000000F;
27 int rs = (opcode >> 8) & 0x0000000F;
28 ++cpu->cycles;
29 int shift = cpu->gprs[rs];
30 if (rs == ARM_PC) {
31 shift += 4;
32 }
33 shift &= 0xFF;
34 int32_t shiftVal = cpu->gprs[rm];
35 if (rm == ARM_PC) {
36 shiftVal += 4;
37 }
38 if (!shift) {
39 cpu->shifterOperand = shiftVal;
40 cpu->shifterCarryOut = cpu->cpsr.c;
41 } else if (shift < 32) {
42 cpu->shifterOperand = shiftVal << shift;
43 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
44 } else if (shift == 32) {
45 cpu->shifterOperand = 0;
46 cpu->shifterCarryOut = shiftVal & 1;
47 } else {
48 cpu->shifterOperand = 0;
49 cpu->shifterCarryOut = 0;
50 }
51}
52
53static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
54 int rm = opcode & 0x0000000F;
55 int immediate = (opcode & 0x00000F80) >> 7;
56 if (immediate) {
57 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
58 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
59 } else {
60 cpu->shifterOperand = 0;
61 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
62 }
63}
64
65static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
66 int rm = opcode & 0x0000000F;
67 int rs = (opcode >> 8) & 0x0000000F;
68 ++cpu->cycles;
69 int shift = cpu->gprs[rs];
70 if (rs == ARM_PC) {
71 shift += 4;
72 }
73 shift &= 0xFF;
74 uint32_t shiftVal = cpu->gprs[rm];
75 if (rm == ARM_PC) {
76 shiftVal += 4;
77 }
78 if (!shift) {
79 cpu->shifterOperand = shiftVal;
80 cpu->shifterCarryOut = cpu->cpsr.c;
81 } else if (shift < 32) {
82 cpu->shifterOperand = shiftVal >> shift;
83 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
84 } else if (shift == 32) {
85 cpu->shifterOperand = 0;
86 cpu->shifterCarryOut = shiftVal >> 31;
87 } else {
88 cpu->shifterOperand = 0;
89 cpu->shifterCarryOut = 0;
90 }
91}
92
93static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
94 int rm = opcode & 0x0000000F;
95 int immediate = (opcode & 0x00000F80) >> 7;
96 if (immediate) {
97 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
98 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
99 } else {
100 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
101 cpu->shifterOperand = cpu->shifterCarryOut;
102 }
103}
104
105static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
106 int rm = opcode & 0x0000000F;
107 int rs = (opcode >> 8) & 0x0000000F;
108 ++cpu->cycles;
109 int shift = cpu->gprs[rs];
110 if (rs == ARM_PC) {
111 shift += 4;
112 }
113 shift &= 0xFF;
114 int shiftVal = cpu->gprs[rm];
115 if (rm == ARM_PC) {
116 shiftVal += 4;
117 }
118 if (!shift) {
119 cpu->shifterOperand = shiftVal;
120 cpu->shifterCarryOut = cpu->cpsr.c;
121 } else if (shift < 32) {
122 cpu->shifterOperand = shiftVal >> shift;
123 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
124 } else if (cpu->gprs[rm] >> 31) {
125 cpu->shifterOperand = 0xFFFFFFFF;
126 cpu->shifterCarryOut = 1;
127 } else {
128 cpu->shifterOperand = 0;
129 cpu->shifterCarryOut = 0;
130 }
131}
132
133static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
134 int rm = opcode & 0x0000000F;
135 int immediate = (opcode & 0x00000F80) >> 7;
136 if (immediate) {
137 cpu->shifterOperand = ARM_ROR(cpu->gprs[rm], immediate);
138 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
139 } else {
140 // RRX
141 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
142 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
143 }
144}
145
146static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
147 int rm = opcode & 0x0000000F;
148 int rs = (opcode >> 8) & 0x0000000F;
149 ++cpu->cycles;
150 int shift = cpu->gprs[rs];
151 if (rs == ARM_PC) {
152 shift += 4;
153 }
154 shift &= 0xFF;
155 int shiftVal = cpu->gprs[rm];
156 if (rm == ARM_PC) {
157 shiftVal += 4;
158 }
159 int rotate = shift & 0x1F;
160 if (!shift) {
161 cpu->shifterOperand = shiftVal;
162 cpu->shifterCarryOut = cpu->cpsr.c;
163 } else if (rotate) {
164 cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
165 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
166 } else {
167 cpu->shifterOperand = shiftVal;
168 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
169 }
170}
171
172static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
173 int rotate = (opcode & 0x00000F00) >> 7;
174 int immediate = opcode & 0x000000FF;
175 if (!rotate) {
176 cpu->shifterOperand = immediate;
177 cpu->shifterCarryOut = cpu->cpsr.c;
178 } else {
179 cpu->shifterOperand = ARM_ROR(immediate, rotate);
180 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
181 }
182}
183
184static const ARMInstruction _armTable[0x1000];
185
186static ARMInstruction _ARMLoadInstructionARM(struct ARMMemory* memory, uint32_t address, uint32_t* opcodeOut) {
187 uint32_t opcode = memory->activeRegion[(address & memory->activeMask) >> 2];
188 *opcodeOut = opcode;
189 return _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
190}
191
192void ARMStep(struct ARMCore* cpu) {
193 // TODO
194 uint32_t opcode;
195 ARMInstruction instruction = _ARMLoadInstructionARM(cpu->memory, cpu->gprs[ARM_PC] - WORD_SIZE_ARM, &opcode);
196 cpu->gprs[ARM_PC] += WORD_SIZE_ARM;
197
198 int condition = opcode >> 28;
199 if (condition == 0xE) {
200 instruction(cpu, opcode);
201 return;
202 } else {
203 switch (condition) {
204 case 0x0:
205 if (!ARM_COND_EQ) {
206 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
207 return;
208 }
209 break;
210 case 0x1:
211 if (!ARM_COND_NE) {
212 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
213 return;
214 }
215 break;
216 case 0x2:
217 if (!ARM_COND_CS) {
218 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
219 return;
220 }
221 break;
222 case 0x3:
223 if (!ARM_COND_CC) {
224 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
225 return;
226 }
227 break;
228 case 0x4:
229 if (!ARM_COND_MI) {
230 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
231 return;
232 }
233 break;
234 case 0x5:
235 if (!ARM_COND_PL) {
236 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
237 return;
238 }
239 break;
240 case 0x6:
241 if (!ARM_COND_VS) {
242 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
243 return;
244 }
245 break;
246 case 0x7:
247 if (!ARM_COND_VC) {
248 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
249 return;
250 }
251 break;
252 case 0x8:
253 if (!ARM_COND_HI) {
254 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
255 return;
256 }
257 break;
258 case 0x9:
259 if (!ARM_COND_LS) {
260 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
261 return;
262 }
263 break;
264 case 0xA:
265 if (!ARM_COND_GE) {
266 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
267 return;
268 }
269 break;
270 case 0xB:
271 if (!ARM_COND_LT) {
272 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
273 return;
274 }
275 break;
276 case 0xC:
277 if (!ARM_COND_GT) {
278 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
279 return;
280 }
281 break;
282 case 0xD:
283 if (!ARM_COND_LE) {
284 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32;
285 return;
286 }
287 break;
288 default:
289 break;
290 }
291 }
292 instruction(cpu, opcode);
293}
294
295// Instruction definitions
296// Beware pre-processor antics
297
298#define ARM_ADDITION_S(M, N, D) \
299 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
300 cpu->cpsr = cpu->spsr; \
301 _ARMReadCPSR(cpu); \
302 } else { \
303 cpu->cpsr.n = ARM_SIGN(D); \
304 cpu->cpsr.z = !(D); \
305 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
306 cpu->cpsr.v = ARM_V_ADDITION(M, N, D); \
307 }
308
309#define ARM_SUBTRACTION_S(M, N, D) \
310 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
311 cpu->cpsr = cpu->spsr; \
312 _ARMReadCPSR(cpu); \
313 } else { \
314 cpu->cpsr.n = ARM_SIGN(D); \
315 cpu->cpsr.z = !(D); \
316 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
317 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
318 }
319
320#define ARM_NEUTRAL_S(M, N, D) \
321 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
322 cpu->cpsr = cpu->spsr; \
323 _ARMReadCPSR(cpu); \
324 } else { \
325 cpu->cpsr.n = ARM_SIGN(D); \
326 cpu->cpsr.z = !(D); \
327 cpu->cpsr.c = cpu->shifterCarryOut; \
328 }
329
330#define ARM_NEUTRAL_HI_S(DLO, DHI) \
331 cpu->cpsr.n = ARM_SIGN(DHI); \
332 cpu->cpsr.z = !((DHI) | (DLO));
333
334#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
335#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
336#define ADDR_MODE_2_ADDRESS (address)
337#define ADDR_MODE_2_RN (cpu->gprs[rn])
338#define ADDR_MODE_2_RM (cpu->gprs[rm])
339#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
340#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
341#define ADDR_MODE_2_WRITEBACK(ADDR) (cpu->gprs[rn] = ADDR)
342#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
343#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
344#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
345#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ARM_ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
346
347#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
348#define ADDR_MODE_3_RN ADDR_MODE_2_RN
349#define ADDR_MODE_3_RM ADDR_MODE_2_RM
350#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
351#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
352#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
353
354#define ARM_LOAD_POST_BODY \
355 if (rd == ARM_PC) { \
356 ARM_WRITE_PC; \
357 }
358
359#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
360 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
361 BODY; \
362 cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; \
363 }
364
365#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
366 DEFINE_INSTRUCTION_ARM(NAME, \
367 int rd = (opcode >> 12) & 0xF; \
368 int rn = (opcode >> 16) & 0xF; \
369 UNUSED(rn); \
370 SHIFTER(cpu, opcode); \
371 BODY; \
372 S_BODY; \
373 if (rd == ARM_PC) { \
374 if (cpu->executionMode == MODE_ARM) { \
375 ARM_WRITE_PC; \
376 } else { \
377 THUMB_WRITE_PC; \
378 } \
379 })
380
381#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
382 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
383 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
384 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
385 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
386 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
387 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
388 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
389 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
390 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
391 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
392 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
393 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
394 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
395 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
396 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
397 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
398 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
399 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
400
401#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
402 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
403 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
404 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
405 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
406 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
407 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
408 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
409 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
410 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
411
412#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
413 DEFINE_INSTRUCTION_ARM(NAME, \
414 int rd = (opcode >> 12) & 0xF; \
415 int rdHi = (opcode >> 16) & 0xF; \
416 int rs = (opcode >> 8) & 0xF; \
417 int rm = opcode & 0xF; \
418 UNUSED(rdHi); \
419 BODY; \
420 S_BODY; \
421 if (rd == ARM_PC) { \
422 ARM_WRITE_PC; \
423 })
424
425#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
426 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
427 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
428
429#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
430 DEFINE_INSTRUCTION_ARM(NAME, \
431 uint32_t address; \
432 int rn = (opcode >> 16) & 0xF; \
433 int rd = (opcode >> 12) & 0xF; \
434 int rm = opcode & 0xF; \
435 UNUSED(rm); \
436 address = ADDRESS; \
437 BODY; \
438 WRITEBACK;)
439
440#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
441 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), BODY) \
442 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), BODY) \
443 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , BODY) \
444 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
445 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , BODY) \
446 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
447
448#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
449 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
450 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
451 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
452 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
453 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
454 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
455 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
456 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
457 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , BODY) \
458 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
459
460#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, BODY) \
461 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), BODY) \
462 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), BODY) \
463 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , BODY) \
464 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
465 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , BODY) \
466 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
467 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), BODY) \
468 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), BODY) \
469 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , BODY) \
470 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
471 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , BODY) \
472 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), BODY) \
473
474#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
475 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
476 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
477
478#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, BODY) \
479 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
480 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
481 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
482 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
483 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
484 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
485
486#define ARM_MS_PRE \
487 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
488 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
489
490#define ARM_MS_POST ARMSetPrivilegeMode(cpu, privilegeMode);
491
492#define ADDR_MODE_4_DA uint32_t addr = cpu->gprs[rn]
493#define ADDR_MODE_4_IA uint32_t addr = cpu->gprs[rn]
494#define ADDR_MODE_4_DB uint32_t addr = cpu->gprs[rn] - 4
495#define ADDR_MODE_4_IB uint32_t addr = cpu->gprs[rn] + 4
496#define ADDR_MODE_4_DAW cpu->gprs[rn] = addr
497#define ADDR_MODE_4_IAW cpu->gprs[rn] = addr
498#define ADDR_MODE_4_DBW cpu->gprs[rn] = addr + 4
499#define ADDR_MODE_4_IBW cpu->gprs[rn] = addr - 4
500
501#define ARM_M_INCREMENT(BODY) \
502 for (m = rs, i = 0; m; m >>= 1, ++i) { \
503 if (m & 1) { \
504 BODY; \
505 addr += 4; \
506 } \
507 }
508
509#define ARM_M_DECREMENT(BODY) \
510 for (m = 0x8000, i = 15; m; m >>= 1, --i) { \
511 if (rs & m) { \
512 BODY; \
513 addr -= 4; \
514 } \
515 }
516
517#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LOOP, S_PRE, S_POST, BODY, POST_BODY) \
518 DEFINE_INSTRUCTION_ARM(NAME, \
519 int rn = (opcode >> 16) & 0xF; \
520 int rs = opcode & 0x0000FFFF; \
521 int m; \
522 int i; \
523 ADDRESS; \
524 S_PRE; \
525 LOOP(BODY); \
526 S_POST; \
527 WRITEBACK; \
528 POST_BODY;)
529
530
531#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY, POST_BODY) \
532 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
533 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
534 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, , , BODY, POST_BODY) \
535 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, , , BODY, POST_BODY) \
536 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
537 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
538 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, , , BODY, POST_BODY) \
539 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, , , BODY, POST_BODY) \
540 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, ADDR_MODE_4_DA, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
541 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, ADDR_MODE_4_DA, ADDR_MODE_4_DAW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
542 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, ADDR_MODE_4_DB, , ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
543 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, ADDR_MODE_4_DB, ADDR_MODE_4_DBW, ARM_M_DECREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
544 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, ADDR_MODE_4_IA, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
545 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, ADDR_MODE_4_IA, ADDR_MODE_4_IAW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
546 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, ADDR_MODE_4_IB, , ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY) \
547 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, ADDR_MODE_4_IB, ADDR_MODE_4_IBW, ARM_M_INCREMENT, ARM_MS_PRE, ARM_MS_POST, BODY, POST_BODY)
548
549// Begin ALU definitions
550
551DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
552 int32_t n = cpu->gprs[rn];
553 cpu->gprs[rd] = n + cpu->shifterOperand;)
554
555DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
556 int32_t n = cpu->gprs[rn];
557 int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
558 cpu->gprs[rd] = n + shifterOperand;)
559
560DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
561 cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
562
563DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
564 cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
565
566DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
567 int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
568
569DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
570 int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
571
572DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
573 cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
574
575DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
576 cpu->gprs[rd] = cpu->shifterOperand;)
577
578DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
579 cpu->gprs[rd] = ~cpu->shifterOperand;)
580
581DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
582 cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
583
584DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
585 int32_t n = cpu->gprs[rn];
586 cpu->gprs[rd] = cpu->shifterOperand - n;)
587
588DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
589 int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
590 cpu->gprs[rd] = cpu->shifterOperand - n;)
591
592DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(n, shifterOperand, cpu->gprs[rd]),
593 int32_t n = cpu->gprs[rn];
594 int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
595 cpu->gprs[rd] = n - shifterOperand;)
596
597DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
598 int32_t n = cpu->gprs[rn];
599 cpu->gprs[rd] = n - cpu->shifterOperand;)
600
601DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
602 int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
603
604DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
605 int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
606
607// End ALU definitions
608
609// Begin multiply definitions
610
611DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
612DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
613
614DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
615 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
616 int32_t dm = cpu->gprs[rd];
617 int32_t dn = d;
618 cpu->gprs[rd] = dm + dn;
619 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
620 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
621
622DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
623 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
624 cpu->gprs[rd] = d;
625 cpu->gprs[rdHi] = d >> 32;,
626 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
627
628DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
629 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
630 int32_t dm = cpu->gprs[rd];
631 int32_t dn = d;
632 cpu->gprs[rd] = dm + dn;
633 cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
634 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
635
636DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
637 uint64_t d = ((uint64_t) cpu->gprs[rm]) * ((uint64_t) cpu->gprs[rs]);
638 cpu->gprs[rd] = d;
639 cpu->gprs[rdHi] = d >> 32;,
640 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
641
642// End multiply definitions
643
644// Begin load/store definitions
645
646DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;)
647DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;)
648DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;)
649DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;)
650DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;)
651DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
652DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
653DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
654
655DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
656 enum PrivilegeMode priv = cpu->privilegeMode;
657 ARMSetPrivilegeMode(cpu, MODE_USER);
658 cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
659 ARMSetPrivilegeMode(cpu, priv);
660 ARM_LOAD_POST_BODY;)
661
662DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
663 enum PrivilegeMode priv = cpu->privilegeMode;
664 ARMSetPrivilegeMode(cpu, MODE_USER);
665 cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
666 ARMSetPrivilegeMode(cpu, priv);
667 ARM_LOAD_POST_BODY;)
668
669DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
670 enum PrivilegeMode priv = cpu->privilegeMode;
671 ARMSetPrivilegeMode(cpu, MODE_USER);
672 cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
673 ARMSetPrivilegeMode(cpu, priv);)
674
675DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
676 enum PrivilegeMode priv = cpu->privilegeMode;
677 ARMSetPrivilegeMode(cpu, MODE_USER);
678 cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
679 ARMSetPrivilegeMode(cpu, priv);)
680
681DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
682 cpu->gprs[i] = cpu->memory->load32(cpu->memory, addr);,
683 if (rs & 0x8000) {
684 ARM_WRITE_PC;
685 })
686
687DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i]);, )
688
689DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB)
690DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
691
692// End load/store definitions
693
694// Begin branch definitions
695
696DEFINE_INSTRUCTION_ARM(B,
697 int32_t offset = opcode << 8;
698 offset >>= 6;
699 cpu->gprs[ARM_PC] += offset;
700 ARM_WRITE_PC;)
701
702DEFINE_INSTRUCTION_ARM(BL,
703 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
704 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
705 cpu->gprs[ARM_PC] += immediate >> 6;
706 ARM_WRITE_PC;)
707
708DEFINE_INSTRUCTION_ARM(BX,
709 int rm = opcode & 0x0000000F;
710 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
711 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
712 if (cpu->executionMode == MODE_THUMB) {
713 THUMB_WRITE_PC;
714 } else {
715 ARM_WRITE_PC;
716 })
717
718// End branch definitions
719
720// Begin miscellaneous definitions
721
722DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
723DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
724
725DEFINE_INSTRUCTION_ARM(MSR,
726 int c = opcode & 0x00010000;
727 int f = opcode & 0x00080000;
728 int32_t operand = cpu->gprs[opcode & 0x0000000F];
729 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
730 if (mask & PSR_USER_MASK) {
731 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
732 }
733 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
734 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
735 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
736 })
737
738DEFINE_INSTRUCTION_ARM(MSRR,
739 int c = opcode & 0x00010000;
740 int f = opcode & 0x00080000;
741 int32_t operand = cpu->gprs[opcode & 0x0000000F];
742 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
743 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
744 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
745
746DEFINE_INSTRUCTION_ARM(MRS, \
747 int rd = (opcode >> 12) & 0xF; \
748 cpu->gprs[rd] = cpu->cpsr.packed;)
749
750DEFINE_INSTRUCTION_ARM(MRSR, \
751 int rd = (opcode >> 12) & 0xF; \
752 cpu->gprs[rd] = cpu->spsr.packed;)
753
754DEFINE_INSTRUCTION_ARM(MSRI,
755 int c = opcode & 0x00010000;
756 int f = opcode & 0x00080000;
757 int rotate = (opcode & 0x00000F00) >> 8;
758 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
759 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
760 if (mask & PSR_USER_MASK) {
761 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
762 }
763 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
764 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
765 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
766 })
767
768DEFINE_INSTRUCTION_ARM(MSRRI,
769 int c = opcode & 0x00010000;
770 int f = opcode & 0x00080000;
771 int rotate = (opcode & 0x00000F00) >> 8;
772 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
773 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
774 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
775 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);)
776
777DEFINE_INSTRUCTION_ARM(SWI, cpu->board->swi32(cpu->board, opcode & 0xFFFFFF))
778
779#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
780 EMITTER ## NAME
781
782#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
783 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
784 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
785
786#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
787 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
788 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
789 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
790 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
791 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
792 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
793 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
794 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
795 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
796 DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
797 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
798 DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
799 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
800 DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
801 DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
802 DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
803
804#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
805 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
806 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
807
808#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
809 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
810 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
811 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
812 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
813 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
814 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
815 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
816 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
817 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
818 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
819 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
820 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
821 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
822 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
823 DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
824 DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
825
826#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
827 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
828 DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
829
830#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
831 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
832
833// TODO: Support coprocessors
834#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, W, N) \
835 DO_8(0), \
836 DO_8(0)
837
838#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
839 DO_8(DO_8(DO_INTERLACE(0, 0))), \
840 DO_8(DO_8(DO_INTERLACE(0, 0)))
841
842#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
843 DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
844
845#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
846 DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
847 DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
848 DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, ILL, ILL, ILL), \
849 DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, ILL, ILL, ILL), \
850 DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
851 DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
852 DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, ILL, ILL, ILL), \
853 DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, ILL, ILL, ILL), \
854 DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
855 DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
856 DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, ILL, ILL, ILL), \
857 DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, ILL, ILL, ILL), \
858 DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
859 DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
860 DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, ILL, ILL, ILL), \
861 DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, ILL, ILL, ILL), \
862 DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
863 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
864 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
865 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
866 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
867 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
868 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
869 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
870 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
871 DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
872 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
873 DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
874 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
875 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
876 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
877 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
878 DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
879 DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
880 DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
881 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
882 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
883 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
884 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
885 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
886 DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
887 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
888 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
889 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
890 DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
891 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
892 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
893 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
894 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
895 DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
896 DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
897 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
898 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
899 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
900 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
901 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
902 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
903 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
904 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
905 DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
906 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
907 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
908 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
909 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
910 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
911 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
912 DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
913 DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
914 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
915 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
916 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
917 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
918 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
919 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
920 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
921 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
922 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
923 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
924 DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
925 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
926 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
927 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
928 DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
929 DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
930 DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
931 DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
932 DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
933 DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
934 DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
935 DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
936 DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
937 DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
938 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
939 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
940 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
941 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
942 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
943 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
944 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
945 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
946 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
947 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
948 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
949 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
950 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
951 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
952 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
953 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
954 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
955 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
956 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
957 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
958 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
959 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
960 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
961 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
962 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
963 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
964 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
965 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
966 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
967 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
968 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
969 DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
970 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
971 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
972 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
973 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
974 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
975 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
976 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
977 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
978 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
979 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
980 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
981 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
982 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
983 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
984 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
985 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
986 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
987 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
988 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
989 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
990 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
991 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
992 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
993 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
994 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
995 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
996 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
997 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
998 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
999 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
1000 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
1001 DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
1002 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
1003 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
1004 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
1005 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
1006 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
1007 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
1008 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
1009 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
1010 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
1011 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
1012 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
1013 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
1014 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
1015 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
1016 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
1017 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
1018 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
1019 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
1020 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
1021 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
1022 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
1023 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
1024 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
1025 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
1026 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
1027 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
1028 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
1029 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
1030 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
1031 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
1032 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
1033 DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
1034 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
1035 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
1036 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
1037 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
1038 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
1039 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
1040 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
1041 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
1042 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
1043 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
1044 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
1045 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
1046 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
1047 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
1048 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
1049 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
1050 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
1051 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
1052 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
1053 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
1054 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
1055 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
1056 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
1057 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
1058 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
1059 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
1060 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
1061 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
1062 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
1063 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
1064 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
1065 DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
1066 DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
1067 DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
1068 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
1069 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
1070 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
1071 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
1072 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
1073 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
1074 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
1075 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
1076 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
1077 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
1078 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
1079 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
1080 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
1081 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
1082 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
1083 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
1084 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
1085 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
1086 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
1087 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
1088 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1089 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1090 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1091 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1092 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
1093 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
1094 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
1095 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
1096 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
1097 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
1098 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
1099 DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
1100 DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
1101 DECLARE_ARM_SWI_BLOCK(EMITTER)
1102
1103static const ARMInstruction _armTable[0x1000] = {
1104 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
1105};