src/arm/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define THUMB_SUBTRACTION(D, M, N) \
42 int n = N; \
43 int m = M; \
44 D = M - N; \
45 THUMB_SUBTRACTION_S(m, n, D)
46
47#define APPLY(F, ...) F(__VA_ARGS__)
48
49#define COUNT_1(EMITTER, PREFIX, ...) \
50 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
51 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
52
53#define COUNT_2(EMITTER, PREFIX, ...) \
54 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
55 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
56 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
57
58#define COUNT_3(EMITTER, PREFIX, ...) \
59 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
60 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
61 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
62 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
63 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
64
65#define COUNT_4(EMITTER, PREFIX, ...) \
66 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
67 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
68 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
69 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
70 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
71 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
72 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
73 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
74 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
75
76#define COUNT_5(EMITTER, PREFIX, ...) \
77 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
78 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
79 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
80 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
81 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
82 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
83 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
84 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
85 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
86 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
87 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
88 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
89 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
90 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
91 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
92 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
93 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
94
95#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
96 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
97 BODY; \
98 cpu->cycles += 1 + cpu->memory->activePrefetchCycles16; \
99 }
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
102 DEFINE_INSTRUCTION_THUMB(NAME, \
103 int immediate = IMMEDIATE; \
104 int rd = opcode & 0x0007; \
105 int rm = (opcode >> 3) & 0x0007; \
106 BODY;)
107
108#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
109 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
110
111DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
112 if (!immediate) {
113 cpu->gprs[rd] = cpu->gprs[rm];
114 } else {
115 cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
116 cpu->gprs[rd] = cpu->gprs[rm] << immediate;
117 }
118 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
119
120DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
121 if (!immediate) {
122 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
123 cpu->gprs[rd] = 0;
124 } else {
125 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
126 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
127 }
128 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
129
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
131 if (!immediate) {
132 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
133 if (cpu->cpsr.c) {
134 cpu->gprs[rd] = 0xFFFFFFFF;
135 } else {
136 cpu->gprs[rd] = 0;
137 }
138 } else {
139 cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
140 cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
141 }
142 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
143
144DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
145DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rm] + immediate))
146DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rm] + immediate * 2))
147DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
148DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory->store8(cpu->memory, cpu->gprs[rm] + immediate, cpu->gprs[rd]))
149DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
150
151#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
152 DEFINE_INSTRUCTION_THUMB(NAME, \
153 int rm = RM; \
154 int rd = opcode & 0x0007; \
155 int rn = (opcode >> 3) & 0x0007; \
156 BODY;)
157
158#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
159 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
160
161DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
162DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
163
164#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
165 DEFINE_INSTRUCTION_THUMB(NAME, \
166 int immediate = IMMEDIATE; \
167 int rd = opcode & 0x0007; \
168 int rn = (opcode >> 3) & 0x0007; \
169 BODY;)
170
171#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
172 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
173
174DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
175DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
176
177#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
178 DEFINE_INSTRUCTION_THUMB(NAME, \
179 int rd = RD; \
180 int immediate = opcode & 0x00FF; \
181 BODY;)
182
183#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
184 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
185
186DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
187DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
188DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
189DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rd], immediate))
190
191#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
192 DEFINE_INSTRUCTION_THUMB(NAME, \
193 int rd = opcode & 0x0007; \
194 int rn = (opcode >> 3) & 0x0007; \
195 BODY;)
196
197DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
198DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
199DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
200 int rs = cpu->gprs[rn] & 0xFF;
201 if (rs) {
202 if (rs < 32) {
203 cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
204 cpu->gprs[rd] <<= rs;
205 } else {
206 if (rs > 32) {
207 cpu->cpsr.c = 0;
208 } else {
209 cpu->cpsr.c = cpu->gprs[rd] & 0x00000001;
210 }
211 cpu->gprs[rd] = 0;
212 }
213 }
214 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
215
216DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
217 int rs = cpu->gprs[rn] & 0xFF;
218 if (rs) {
219 if (rs < 32) {
220 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
221 cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
222 } else {
223 if (rs > 32) {
224 cpu->cpsr.c = 0;
225 } else {
226 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
227 }
228 cpu->gprs[rd] = 0;
229 }
230 }
231 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
232
233DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
234 int rs = cpu->gprs[rn] & 0xFF;
235 if (rs) {
236 if (rs < 32) {
237 cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
238 cpu->gprs[rd] >>= rs;
239 } else {
240 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
241 if (cpu->cpsr.c) {
242 cpu->gprs[rd] = 0xFFFFFFFF;
243 } else {
244 cpu->gprs[rd] = 0;
245 }
246 }
247 }
248 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
249
250DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC,
251 int n = cpu->gprs[rn] + cpu->cpsr.c;
252 int d = cpu->gprs[rd];
253 cpu->gprs[rd] = d + n;
254 THUMB_ADDITION_S(d, n, cpu->gprs[rd]);)
255
256DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC,
257 int n = cpu->gprs[rn] + !cpu->cpsr.c;
258 int d = cpu->gprs[rd];
259 cpu->gprs[rd] = d - n;
260 THUMB_SUBTRACTION_S(d, n, cpu->gprs[rd]);)
261DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
262 int rs = cpu->gprs[rn] & 0xFF;
263 if (rs) {
264 int r4 = rs & 0x1F;
265 if (r4 > 0) {
266 cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
267 cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
268 } else {
269 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
270 }
271 }
272 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
273DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, int32_t aluOut = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
274DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cpu->gprs[rn]))
275DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
276DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
277DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
278DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
279DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
280DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
281
282#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
283 DEFINE_INSTRUCTION_THUMB(NAME, \
284 int rd = (opcode & 0x0007) | H1; \
285 int rm = ((opcode >> 3) & 0x0007) | H2; \
286 BODY;)
287
288#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
289 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
290 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
291 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
292 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
293
294DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4,
295 cpu->gprs[rd] += cpu->gprs[rm];
296 if (rd == ARM_PC) {
297 THUMB_WRITE_PC;
298 })
299
300DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
301DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
302 cpu->gprs[rd] = cpu->gprs[rm];
303 if (rd == ARM_PC) {
304 THUMB_WRITE_PC;
305 })
306
307#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
308 DEFINE_INSTRUCTION_THUMB(NAME, \
309 int rd = RD; \
310 int immediate = (opcode & 0x00FF) << 2; \
311 BODY;)
312
313#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
314 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
315
316DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate))
317DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
318DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
319
320DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
321DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
322
323#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
324 DEFINE_INSTRUCTION_THUMB(NAME, \
325 int rm = RM; \
326 int rd = opcode & 0x0007; \
327 int rn = (opcode >> 3) & 0x0007; \
328 BODY;)
329
330#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
331 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
332
333DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
334DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
335DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
336DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
337DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm]))
338DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory->store32(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd]))
339DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory->store8(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd]))
340DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory->store16(cpu->memory, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd]))
341
342#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
343 DEFINE_INSTRUCTION_THUMB(NAME, \
344 int rn = RN; \
345 int rs = opcode & 0xFF; \
346 int32_t address = ADDRESS; \
347 int m; \
348 int i; \
349 PRE_BODY; \
350 for LOOP { \
351 if (rs & m) { \
352 BODY; \
353 address OP 4; \
354 } \
355 } \
356 POST_BODY; \
357 WRITEBACK;)
358
359#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
360 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
361
362DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
363 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
364 if (!((1 << rn) & rs)) {
365 cpu->gprs[rn] = address;
366 })
367
368DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
369 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
370 cpu->gprs[rn] = address)
371
372#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
373 DEFINE_INSTRUCTION_THUMB(B ## COND, \
374 if (ARM_COND_ ## COND) { \
375 int8_t immediate = opcode; \
376 cpu->gprs[ARM_PC] += immediate << 1; \
377 THUMB_WRITE_PC; \
378 })
379
380DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
381DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
382DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
383DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
384DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
385DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
386DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
387DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
388DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
389DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
390DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
391DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
392DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
393DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
394
395DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
396DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
397
398DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
399 opcode & 0x00FF,
400 cpu->gprs[ARM_SP],
401 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
402 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
403 +=,
404 , ,
405 cpu->gprs[ARM_SP] = address)
406
407DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
408 opcode & 0x00FF,
409 cpu->gprs[ARM_SP],
410 (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
411 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
412 +=,
413 ,
414 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE;
415 address += 4;,
416 cpu->gprs[ARM_SP] = address;
417 THUMB_WRITE_PC;)
418
419DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
420 opcode & 0x00FF,
421 cpu->gprs[ARM_SP] - 4,
422 (m = 0x80, i = 7; m; m >>= 1, --i),
423 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
424 -=,
425 , ,
426 cpu->gprs[ARM_SP] = address + 4)
427
428DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
429 opcode & 0x00FF,
430 cpu->gprs[ARM_SP] - 4,
431 (m = 0x80, i = 7; m; m >>= 1, --i),
432 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
433 -=,
434 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]);
435 address -= 4;,
436 ,
437 cpu->gprs[ARM_SP] = address + 4)
438
439DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
440DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
441DEFINE_INSTRUCTION_THUMB(B,
442 int16_t immediate = (opcode & 0x07FF) << 5;
443 cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
444 THUMB_WRITE_PC;)
445
446DEFINE_INSTRUCTION_THUMB(BL1,
447 int16_t immediate = (opcode & 0x07FF) << 5;
448 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
449
450DEFINE_INSTRUCTION_THUMB(BL2,
451 uint16_t immediate = (opcode & 0x07FF) << 1;
452 uint32_t pc = cpu->gprs[ARM_PC];
453 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
454 cpu->gprs[ARM_LR] = pc - 1;
455 THUMB_WRITE_PC;)
456
457DEFINE_INSTRUCTION_THUMB(BX,
458 int rm = (opcode >> 3) & 0xF;
459 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
460 int misalign = 0;
461 if (rm == ARM_PC) {
462 misalign = cpu->gprs[rm] & 0x00000002;
463 }
464 cpu->gprs[ARM_PC] = (cpu->gprs[rm] & 0xFFFFFFFE) - misalign;
465 if (cpu->executionMode == MODE_THUMB) {
466 THUMB_WRITE_PC;
467 } else {
468 ARM_WRITE_PC;
469 })
470
471DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
472
473#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
474 EMITTER ## NAME
475
476#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
477 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
478 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
479 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
480 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
481
482#define DUMMY(X, ...) X,
483#define DUMMY_4(...) \
484 DUMMY(__VA_ARGS__) \
485 DUMMY(__VA_ARGS__) \
486 DUMMY(__VA_ARGS__) \
487 DUMMY(__VA_ARGS__)
488
489#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
490 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
491 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
492 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
493 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
494 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
495 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
496 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
497 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
498 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
499 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
500 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
501 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
502 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
503 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
504 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
505 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
506 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
507 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
508 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
509 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
510 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
511 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
512 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
513 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
514 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
515 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
516 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
517 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
518 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
519 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
520 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
521 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
522 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
523 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
524 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
525 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
526 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
527 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
528 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
529 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
530 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
531 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
532 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
533 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
534 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
535 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
536 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
537 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
538 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
539 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
540 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
541 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
542 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
543 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
544 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
545 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
546 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
547 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
548 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
549 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
550 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
551 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
552 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
553 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
554 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
555 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
556 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
557 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
558 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
559 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
560 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
561 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
562 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
563 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
564 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
565 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
566 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
567 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
568 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
569 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
570 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
571 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
572 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
573 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
574 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
575 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
576 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
577 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
578 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
579 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
580 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
581
582static const ThumbInstruction _thumbTable[0x400] = {
583 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
584};