src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
33
34static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
35static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
36
37static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
38
39static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
40static void _GBPocketCamCapture(struct GBMemory*);
41
42void GBMBCSwitchBank(struct GB* gb, int bank) {
43 size_t bankStart = bank * GB_SIZE_CART_BANK0;
44 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
45 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
46 bankStart &= (gb->memory.romSize - 1);
47 bank = bankStart / GB_SIZE_CART_BANK0;
48 }
49 gb->memory.romBank = &gb->memory.rom[bankStart];
50 gb->memory.currentBank = bank;
51 if (gb->cpu->pc < GB_BASE_VRAM) {
52 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
53 }
54}
55
56void GBMBCSwitchBank0(struct GB* gb, int bank) {
57 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
58 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
59 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
60 bankStart &= (gb->memory.romSize - 1);
61 }
62 gb->memory.romBase = &gb->memory.rom[bankStart];
63 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
64 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
65 }
66}
67
68void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
69 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
70 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
71 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
72 bankStart &= (gb->memory.romSize - 1);
73 bank = bankStart / GB_SIZE_CART_HALFBANK;
74 if (!bank) {
75 ++bank;
76 }
77 }
78 if (!half) {
79 gb->memory.romBank = &gb->memory.rom[bankStart];
80 gb->memory.currentBank = bank;
81 } else {
82 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
83 gb->memory.mbcState.mbc6.currentBank1 = bank;
84 }
85 if (gb->cpu->pc < GB_BASE_VRAM) {
86 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
87 }
88}
89
90static bool _isMulticart(const uint8_t* mem) {
91 bool success = true;
92 struct VFile* vf;
93
94 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
95 success = success && GBIsROM(vf);
96 vf->close(vf);
97
98 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
99 success = success && GBIsROM(vf);
100 vf->close(vf);
101
102 return success;
103}
104
105void GBMBCSwitchSramBank(struct GB* gb, int bank) {
106 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
107 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
108 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
109 bankStart &= (gb->sramSize - 1);
110 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
111 }
112 gb->memory.sramBank = &gb->memory.sram[bankStart];
113 gb->memory.sramCurrentBank = bank;
114}
115
116void GBMBCInit(struct GB* gb) {
117 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
118 if (gb->memory.rom) {
119 switch (cart->ramSize) {
120 case 0:
121 gb->sramSize = 0;
122 break;
123 case 1:
124 gb->sramSize = 0x800;
125 break;
126 default:
127 case 2:
128 gb->sramSize = 0x2000;
129 break;
130 case 3:
131 gb->sramSize = 0x8000;
132 break;
133 case 4:
134 gb->sramSize = 0x20000;
135 break;
136 case 5:
137 gb->sramSize = 0x10000;
138 break;
139 }
140
141 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
142 switch (cart->type) {
143 case 0:
144 case 8:
145 case 9:
146 gb->memory.mbcType = GB_MBC_NONE;
147 break;
148 case 1:
149 case 2:
150 case 3:
151 gb->memory.mbcType = GB_MBC1;
152 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
153 gb->memory.mbcState.mbc1.multicartStride = 4;
154 } else {
155 gb->memory.mbcState.mbc1.multicartStride = 5;
156 }
157 break;
158 case 5:
159 case 6:
160 gb->memory.mbcType = GB_MBC2;
161 break;
162 case 0x0F:
163 case 0x10:
164 gb->memory.mbcType = GB_MBC3_RTC;
165 break;
166 case 0x11:
167 case 0x12:
168 case 0x13:
169 gb->memory.mbcType = GB_MBC3;
170 break;
171 default:
172 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
173 // Fall through
174 case 0x19:
175 case 0x1A:
176 case 0x1B:
177 gb->memory.mbcType = GB_MBC5;
178 break;
179 case 0x1C:
180 case 0x1D:
181 case 0x1E:
182 gb->memory.mbcType = GB_MBC5_RUMBLE;
183 break;
184 case 0x20:
185 gb->memory.mbcType = GB_MBC6;
186 break;
187 case 0x22:
188 gb->memory.mbcType = GB_MBC7;
189 break;
190 case 0xFC:
191 gb->memory.mbcType = GB_POCKETCAM;
192 break;
193 case 0xFD:
194 gb->memory.mbcType = GB_TAMA5;
195 break;
196 case 0xFE:
197 gb->memory.mbcType = GB_HuC3;
198 break;
199 case 0xFF:
200 gb->memory.mbcType = GB_HuC1;
201 break;
202 }
203 }
204 } else {
205 gb->memory.mbcType = GB_MBC_NONE;
206 }
207 gb->memory.mbcRead = NULL;
208 switch (gb->memory.mbcType) {
209 case GB_MBC_NONE:
210 gb->memory.mbcWrite = _GBMBCNone;
211 break;
212 case GB_MBC1:
213 gb->memory.mbcWrite = _GBMBC1;
214 break;
215 case GB_MBC2:
216 gb->memory.mbcWrite = _GBMBC2;
217 gb->sramSize = 0x200;
218 break;
219 case GB_MBC3:
220 gb->memory.mbcWrite = _GBMBC3;
221 break;
222 default:
223 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
224 // Fall through
225 case GB_MBC5:
226 gb->memory.mbcWrite = _GBMBC5;
227 break;
228 case GB_MBC6:
229 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
230 gb->memory.mbcWrite = _GBMBC6;
231 break;
232 case GB_MBC7:
233 gb->memory.mbcWrite = _GBMBC7;
234 gb->memory.mbcRead = _GBMBC7Read;
235 gb->sramSize = 0x100;
236 break;
237 case GB_MMM01:
238 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
239 gb->memory.mbcWrite = _GBMBC1;
240 break;
241 case GB_HuC1:
242 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
243 gb->memory.mbcWrite = _GBMBC1;
244 break;
245 case GB_HuC3:
246 gb->memory.mbcWrite = _GBHuC3;
247 break;
248 case GB_TAMA5:
249 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
250 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
251 gb->memory.mbcWrite = _GBTAMA5;
252 gb->memory.mbcRead = _GBTAMA5Read;
253 gb->sramSize = 0x20;
254 break;
255 case GB_MBC3_RTC:
256 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
257 gb->memory.mbcWrite = _GBMBC3;
258 break;
259 case GB_MBC5_RUMBLE:
260 gb->memory.mbcWrite = _GBMBC5;
261 break;
262 case GB_POCKETCAM:
263 gb->memory.mbcWrite = _GBPocketCam;
264 gb->memory.mbcRead = _GBPocketCamRead;
265 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
266 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
267 }
268 break;
269 }
270
271 gb->memory.currentBank = 1;
272 gb->memory.sramCurrentBank = 0;
273 gb->memory.sramAccess = false;
274 gb->memory.rtcAccess = false;
275 gb->memory.activeRtcReg = 0;
276 gb->memory.rtcLatched = false;
277 gb->memory.rtcLastLatch = 0;
278 if (gb->memory.rtc) {
279 if (gb->memory.rtc->sample) {
280 gb->memory.rtc->sample(gb->memory.rtc);
281 }
282 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
283 } else {
284 gb->memory.rtcLastLatch = time(0);
285 }
286 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
287
288 GBResizeSram(gb, gb->sramSize);
289
290 if (gb->memory.mbcType == GB_MBC3_RTC) {
291 GBMBCRTCRead(gb);
292 }
293}
294
295static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
296 time_t t;
297 if (rtc) {
298 if (rtc->sample) {
299 rtc->sample(rtc);
300 }
301 t = rtc->unixTime(rtc);
302 } else {
303 t = time(0);
304 }
305 time_t currentLatch = t;
306 t -= *rtcLastLatch;
307 *rtcLastLatch = currentLatch;
308
309 int64_t diff;
310 diff = rtcRegs[0] + t % 60;
311 if (diff < 0) {
312 diff += 60;
313 t -= 60;
314 }
315 rtcRegs[0] = diff % 60;
316 t /= 60;
317 t += diff / 60;
318
319 diff = rtcRegs[1] + t % 60;
320 if (diff < 0) {
321 diff += 60;
322 t -= 60;
323 }
324 rtcRegs[1] = diff % 60;
325 t /= 60;
326 t += diff / 60;
327
328 diff = rtcRegs[2] + t % 24;
329 if (diff < 0) {
330 diff += 24;
331 t -= 24;
332 }
333 rtcRegs[2] = diff % 24;
334 t /= 24;
335 t += diff / 24;
336
337 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
338 rtcRegs[3] = diff;
339 rtcRegs[4] &= 0xFE;
340 rtcRegs[4] |= (diff >> 8) & 1;
341 if (diff & 0x200) {
342 rtcRegs[4] |= 0x80;
343 }
344}
345
346void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
347 struct GBMemory* memory = &gb->memory;
348 int bank = value & 0x1F;
349 int stride = 1 << memory->mbcState.mbc1.multicartStride;
350 switch (address >> 13) {
351 case 0x0:
352 switch (value) {
353 case 0:
354 memory->sramAccess = false;
355 break;
356 case 0xA:
357 memory->sramAccess = true;
358 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
359 break;
360 default:
361 // TODO
362 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
363 break;
364 }
365 break;
366 case 0x1:
367 if (!bank) {
368 ++bank;
369 }
370 bank &= stride - 1;
371 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
372 break;
373 case 0x2:
374 bank &= 3;
375 if (memory->mbcState.mbc1.mode) {
376 GBMBCSwitchBank0(gb, bank);
377 GBMBCSwitchSramBank(gb, bank);
378 }
379 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
380 break;
381 case 0x3:
382 memory->mbcState.mbc1.mode = value & 1;
383 if (memory->mbcState.mbc1.mode) {
384 GBMBCSwitchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
385 } else {
386 GBMBCSwitchBank0(gb, 0);
387 GBMBCSwitchSramBank(gb, 0);
388 }
389 break;
390 default:
391 // TODO
392 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
393 break;
394 }
395}
396
397void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
398 struct GBMemory* memory = &gb->memory;
399 int bank = value & 0xF;
400 switch (address >> 13) {
401 case 0x0:
402 switch (value) {
403 case 0:
404 memory->sramAccess = false;
405 break;
406 case 0xA:
407 memory->sramAccess = true;
408 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
409 break;
410 default:
411 // TODO
412 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
413 break;
414 }
415 break;
416 case 0x1:
417 if (!bank) {
418 ++bank;
419 }
420 GBMBCSwitchBank(gb, bank);
421 break;
422 default:
423 // TODO
424 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
425 break;
426 }
427}
428
429void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
430 struct GBMemory* memory = &gb->memory;
431 int bank = value & 0x7F;
432 switch (address >> 13) {
433 case 0x0:
434 switch (value) {
435 case 0:
436 memory->sramAccess = false;
437 break;
438 case 0xA:
439 memory->sramAccess = true;
440 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
441 break;
442 default:
443 // TODO
444 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
445 break;
446 }
447 break;
448 case 0x1:
449 if (!bank) {
450 ++bank;
451 }
452 GBMBCSwitchBank(gb, bank);
453 break;
454 case 0x2:
455 if (value < 4) {
456 GBMBCSwitchSramBank(gb, value);
457 memory->rtcAccess = false;
458 } else if (value >= 8 && value <= 0xC) {
459 memory->activeRtcReg = value - 8;
460 memory->rtcAccess = true;
461 }
462 break;
463 case 0x3:
464 if (memory->rtcLatched && value == 0) {
465 memory->rtcLatched = false;
466 } else if (!memory->rtcLatched && value == 1) {
467 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
468 memory->rtcLatched = true;
469 }
470 break;
471 }
472}
473
474void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
475 struct GBMemory* memory = &gb->memory;
476 int bank;
477 switch (address >> 12) {
478 case 0x0:
479 case 0x1:
480 switch (value) {
481 case 0:
482 memory->sramAccess = false;
483 break;
484 case 0xA:
485 memory->sramAccess = true;
486 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
487 break;
488 default:
489 // TODO
490 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
491 break;
492 }
493 break;
494 case 0x2:
495 bank = (memory->currentBank & 0x100) | value;
496 GBMBCSwitchBank(gb, bank);
497 break;
498 case 0x3:
499 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
500 GBMBCSwitchBank(gb, bank);
501 break;
502 case 0x4:
503 case 0x5:
504 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
505 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
506 value &= ~8;
507 }
508 GBMBCSwitchSramBank(gb, value & 0xF);
509 break;
510 default:
511 // TODO
512 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
513 break;
514 }
515}
516
517void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
518 struct GBMemory* memory = &gb->memory;
519 int bank = value & 0x7F;
520 switch (address >> 10) {
521 case 0:
522 switch (value) {
523 case 0:
524 memory->sramAccess = false;
525 break;
526 case 0xA:
527 memory->sramAccess = true;
528 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
529 break;
530 default:
531 // TODO
532 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
533 break;
534 }
535 break;
536 case 0x9:
537 GBMBCSwitchHalfBank(gb, 0, bank);
538 break;
539 case 0xD:
540 GBMBCSwitchHalfBank(gb, 1, bank);
541 break;
542 default:
543 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
544 break;
545 }
546}
547
548void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
549 int bank = value & 0x7F;
550 switch (address >> 13) {
551 case 0x0:
552 switch (value) {
553 default:
554 case 0:
555 gb->memory.mbcState.mbc7.access = 0;
556 break;
557 case 0xA:
558 gb->memory.mbcState.mbc7.access |= 1;
559 break;
560 }
561 break;
562 case 0x1:
563 GBMBCSwitchBank(gb, bank);
564 break;
565 case 0x2:
566 if (value == 0x40) {
567 gb->memory.mbcState.mbc7.access |= 2;
568 } else {
569 gb->memory.mbcState.mbc7.access &= ~2;
570 }
571 break;
572 case 0x5:
573 _GBMBC7Write(&gb->memory, address, value);
574 default:
575 // TODO
576 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
577 break;
578 }
579}
580
581uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
582 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
583 if (mbc7->access != 3) {
584 return 0xFF;
585 }
586 switch (address & 0xF0) {
587 case 0x20:
588 if (memory->rotation && memory->rotation->readTiltX) {
589 int32_t x = -memory->rotation->readTiltX(memory->rotation);
590 x >>= 21;
591 x += 0x81D0;
592 return x;
593 }
594 return 0xFF;
595 case 0x30:
596 if (memory->rotation && memory->rotation->readTiltX) {
597 int32_t x = -memory->rotation->readTiltX(memory->rotation);
598 x >>= 21;
599 x += 0x81D0;
600 return x >> 8;
601 }
602 return 7;
603 case 0x40:
604 if (memory->rotation && memory->rotation->readTiltY) {
605 int32_t y = -memory->rotation->readTiltY(memory->rotation);
606 y >>= 21;
607 y += 0x81D0;
608 return y;
609 }
610 return 0xFF;
611 case 0x50:
612 if (memory->rotation && memory->rotation->readTiltY) {
613 int32_t y = -memory->rotation->readTiltY(memory->rotation);
614 y >>= 21;
615 y += 0x81D0;
616 return y >> 8;
617 }
618 return 7;
619 case 0x60:
620 return 0;
621 case 0x80:
622 return mbc7->eeprom;
623 default:
624 return 0xFF;
625 }
626}
627
628static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
629 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
630 if (mbc7->access != 3) {
631 return;
632 }
633 switch (address & 0xF0) {
634 case 0x00:
635 mbc7->latch = (value & 0x55) == 0x55;
636 return;
637 case 0x10:
638 mbc7->latch |= (value & 0xAA);
639 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
640 memory->rotation->sample(memory->rotation);
641 }
642 mbc7->latch = 0;
643 return;
644 default:
645 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
646 return;
647 case 0x80:
648 break;
649 }
650 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
651 value = GBMBC7FieldFillDO(value); // Hi-Z
652 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
653 mbc7->state = GBMBC7_STATE_IDLE;
654 }
655 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
656 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
657 mbc7->sr <<= 1;
658 mbc7->sr |= GBMBC7FieldGetDI(value);
659 ++mbc7->srBits;
660 }
661 switch (mbc7->state) {
662 case GBMBC7_STATE_IDLE:
663 if (GBMBC7FieldIsDI(value)) {
664 mbc7->state = GBMBC7_STATE_READ_COMMAND;
665 mbc7->srBits = 0;
666 mbc7->sr = 0;
667 }
668 break;
669 case GBMBC7_STATE_READ_COMMAND:
670 if (mbc7->srBits == 10) {
671 mbc7->state = 0x10 | (mbc7->sr >> 6);
672 if (mbc7->state & 0xC) {
673 mbc7->state &= ~0x3;
674 }
675 mbc7->srBits = 0;
676 mbc7->address = mbc7->sr & 0x7F;
677 }
678 break;
679 case GBMBC7_STATE_DO:
680 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
681 mbc7->sr <<= 1;
682 --mbc7->srBits;
683 if (!mbc7->srBits) {
684 mbc7->state = GBMBC7_STATE_IDLE;
685 }
686 break;
687 default:
688 break;
689 }
690 switch (mbc7->state) {
691 case GBMBC7_STATE_EEPROM_EWEN:
692 mbc7->writable = true;
693 mbc7->state = GBMBC7_STATE_IDLE;
694 break;
695 case GBMBC7_STATE_EEPROM_EWDS:
696 mbc7->writable = false;
697 mbc7->state = GBMBC7_STATE_IDLE;
698 break;
699 case GBMBC7_STATE_EEPROM_WRITE:
700 if (mbc7->srBits == 16) {
701 if (mbc7->writable) {
702 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
703 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
704 }
705 mbc7->state = GBMBC7_STATE_IDLE;
706 }
707 break;
708 case GBMBC7_STATE_EEPROM_ERASE:
709 if (mbc7->writable) {
710 memory->sram[mbc7->address * 2] = 0xFF;
711 memory->sram[mbc7->address * 2 + 1] = 0xFF;
712 }
713 mbc7->state = GBMBC7_STATE_IDLE;
714 break;
715 case GBMBC7_STATE_EEPROM_READ:
716 mbc7->srBits = 16;
717 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
718 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
719 mbc7->state = GBMBC7_STATE_DO;
720 value = GBMBC7FieldClearDO(value);
721 break;
722 case GBMBC7_STATE_EEPROM_WRAL:
723 if (mbc7->srBits == 16) {
724 if (mbc7->writable) {
725 int i;
726 for (i = 0; i < 128; ++i) {
727 memory->sram[i * 2] = mbc7->sr >> 8;
728 memory->sram[i * 2 + 1] = mbc7->sr;
729 }
730 }
731 mbc7->state = GBMBC7_STATE_IDLE;
732 }
733 break;
734 case GBMBC7_STATE_EEPROM_ERAL:
735 if (mbc7->writable) {
736 int i;
737 for (i = 0; i < 128; ++i) {
738 memory->sram[i * 2] = 0xFF;
739 memory->sram[i * 2 + 1] = 0xFF;
740 }
741 }
742 mbc7->state = GBMBC7_STATE_IDLE;
743 break;
744 default:
745 break;
746 }
747 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
748 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
749 }
750 mbc7->eeprom = value;
751}
752
753void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
754 struct GBMemory* memory = &gb->memory;
755 int bank = value & 0x3F;
756 if (address & 0x1FFF) {
757 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
758 }
759
760 switch (address >> 13) {
761 case 0x0:
762 switch (value) {
763 case 0xA:
764 memory->sramAccess = true;
765 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
766 break;
767 default:
768 memory->sramAccess = false;
769 break;
770 }
771 break;
772 case 0x1:
773 GBMBCSwitchBank(gb, bank);
774 break;
775 case 0x2:
776 GBMBCSwitchSramBank(gb, bank);
777 break;
778 default:
779 // TODO
780 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
781 break;
782 }
783}
784
785void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
786 struct GBMemory* memory = &gb->memory;
787 int bank = value & 0x3F;
788 switch (address >> 13) {
789 case 0x0:
790 switch (value) {
791 case 0:
792 memory->sramAccess = false;
793 break;
794 case 0xA:
795 memory->sramAccess = true;
796 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
797 break;
798 default:
799 // TODO
800 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
801 break;
802 }
803 break;
804 case 0x1:
805 GBMBCSwitchBank(gb, bank);
806 break;
807 case 0x2:
808 if (value < 0x10) {
809 GBMBCSwitchSramBank(gb, value);
810 memory->mbcState.pocketCam.registersActive = false;
811 } else {
812 memory->mbcState.pocketCam.registersActive = true;
813 }
814 break;
815 case 0x5:
816 address &= 0x7F;
817 if (address == 0 && value & 1) {
818 value &= 6; // TODO: Timing
819 _GBPocketCamCapture(memory);
820 }
821 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
822 memory->mbcState.pocketCam.registers[address] = value;
823 }
824 break;
825 default:
826 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
827 break;
828 }
829}
830
831uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
832 if (memory->mbcState.pocketCam.registersActive) {
833 if ((address & 0x7F) == 0) {
834 return memory->mbcState.pocketCam.registers[0];
835 }
836 return 0;
837 }
838 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
839}
840
841void _GBPocketCamCapture(struct GBMemory* memory) {
842 if (!memory->cam) {
843 return;
844 }
845 const void* image = NULL;
846 size_t stride;
847 enum mColorFormat format;
848 memory->cam->requestImage(memory->cam, &image, &stride, &format);
849 if (!image) {
850 return;
851 }
852 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
853 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
854 size_t x, y;
855 for (y = 0; y < GBCAM_HEIGHT; ++y) {
856 for (x = 0; x < GBCAM_WIDTH; ++x) {
857 uint32_t gray;
858 uint32_t color;
859 switch (format) {
860 case mCOLOR_XBGR8:
861 case mCOLOR_XRGB8:
862 case mCOLOR_ARGB8:
863 case mCOLOR_ABGR8:
864 color = ((const uint32_t*) image)[y * stride + x];
865 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
866 break;
867 case mCOLOR_BGRX8:
868 case mCOLOR_RGBX8:
869 case mCOLOR_RGBA8:
870 case mCOLOR_BGRA8:
871 color = ((const uint32_t*) image)[y * stride + x];
872 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
873 break;
874 case mCOLOR_BGR5:
875 case mCOLOR_RGB5:
876 case mCOLOR_ARGB5:
877 case mCOLOR_ABGR5:
878 color = ((const uint16_t*) image)[y * stride + x];
879 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
880 break;
881 case mCOLOR_BGR565:
882 case mCOLOR_RGB565:
883 color = ((const uint16_t*) image)[y * stride + x];
884 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
885 break;
886 case mCOLOR_BGRA5:
887 case mCOLOR_RGBA5:
888 color = ((const uint16_t*) image)[y * stride + x];
889 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
890 break;
891 default:
892 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
893 return;
894 }
895 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
896 gray = (gray + 1) * exposure / 0x300;
897 // TODO: Additional processing
898 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
899 if (gray < pocketCam->registers[matrixEntry + 6]) {
900 gray = 0x101;
901 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
902 gray = 0x100;
903 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
904 gray = 0x001;
905 } else {
906 gray = 0;
907 }
908 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
909 uint16_t existing;
910 LOAD_16LE(existing, coord + 0x100, memory->sram);
911 existing |= gray << (7 - (x & 7));
912 STORE_16LE(existing, coord + 0x100, memory->sram);
913 }
914 }
915}
916
917void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
918 struct GBMemory* memory = &gb->memory;
919 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
920 switch (address >> 13) {
921 case 0x5:
922 if (address & 1) {
923 tama5->reg = value;
924 } else {
925 value &= 0xF;
926 if (tama5->reg < GBTAMA5_MAX) {
927 tama5->registers[tama5->reg] = value;
928 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
929 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
930 switch (tama5->reg) {
931 case GBTAMA5_BANK_LO:
932 case GBTAMA5_BANK_HI:
933 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
934 break;
935 case GBTAMA5_WRITE_LO:
936 case GBTAMA5_WRITE_HI:
937 case GBTAMA5_CS:
938 break;
939 case GBTAMA5_ADDR_LO:
940 switch (tama5->registers[GBTAMA5_CS] >> 1) {
941 case 0x0: // RAM write
942 memory->sram[address] = out;
943 break;
944 case 0x1: // RAM read
945 break;
946 default:
947 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
948 }
949 break;
950 default:
951 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
952 break;
953 }
954 } else {
955 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
956 }
957 }
958 break;
959 default:
960 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
961 }
962}
963
964uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
965 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
966 if ((address & 0x1FFF) > 1) {
967 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
968 }
969 if (address & 1) {
970 return 0xFF;
971 } else {
972 uint8_t value = 0xF0;
973 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
974 switch (tama5->reg) {
975 case GBTAMA5_ACTIVE:
976 return 0xF1;
977 case GBTAMA5_READ_LO:
978 case GBTAMA5_READ_HI:
979 switch (tama5->registers[GBTAMA5_CS] >> 1) {
980 case 1:
981 value = memory->sram[address];
982 break;
983 default:
984 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
985 break;
986 }
987 if (tama5->reg == GBTAMA5_READ_HI) {
988 value >>= 4;
989 }
990 value |= 0xF0;
991 return value;
992 default:
993 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
994 return 0xF1;
995 }
996 }
997}
998
999void GBMBCRTCRead(struct GB* gb) {
1000 struct GBMBCRTCSaveBuffer rtcBuffer;
1001 struct VFile* vf = gb->sramVf;
1002 if (!vf) {
1003 return;
1004 }
1005 vf->seek(vf, gb->sramSize, SEEK_SET);
1006 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1007 return;
1008 }
1009
1010 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1011 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1012 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1013 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1014 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1015 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1016}
1017
1018void GBMBCRTCWrite(struct GB* gb) {
1019 struct VFile* vf = gb->sramVf;
1020 if (!vf) {
1021 return;
1022 }
1023
1024 uint8_t rtcRegs[5];
1025 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1026 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1027 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1028
1029 struct GBMBCRTCSaveBuffer rtcBuffer;
1030 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1031 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1032 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1033 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1034 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1035 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1036 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1037 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1038 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1039 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1040 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1041
1042 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1043 // Writing past the end of the file can invalidate the file mapping
1044 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1045 gb->memory.sram = NULL;
1046 }
1047 vf->seek(vf, gb->sramSize, SEEK_SET);
1048 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1049 if (!gb->memory.sram) {
1050 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1051 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1052 }
1053}