1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg.gb".
  3
  4[labels]
  50001:4bf2 print_load_font
  60001:4bff print_string
  70001:4c09 print_a
  80001:4c13 print_newline
  90001:4c1e print_digit
 100001:4c2b print_regs
 110001:4c34 _print_sl_data0
 120001:4c3a _print_sl_out0
 130001:4c47 _print_sl_data1
 140001:4c4d _print_sl_out1
 150001:4c5f _print_sl_data2
 160001:4c65 _print_sl_out2
 170001:4c72 _print_sl_data3
 180001:4c78 _print_sl_out3
 190001:4c8a _print_sl_data4
 200001:4c90 _print_sl_out4
 210001:4c9d _print_sl_data5
 220001:4ca3 _print_sl_out5
 230001:4cb5 _print_sl_data6
 240001:4cbb _print_sl_out6
 250001:4cc8 _print_sl_data7
 260001:4cce _print_sl_out7
 270001:4000 font
 280000:c000 regs_save
 290000:c000 regs_save.f
 300000:c001 regs_save.a
 310000:c002 regs_save.c
 320000:c003 regs_save.b
 330000:c004 regs_save.e
 340000:c005 regs_save.d
 350000:c006 regs_save.l
 360000:c007 regs_save.h
 370000:c008 regs_flags
 380000:c009 regs_assert
 390000:c009 regs_assert.f
 400000:c00a regs_assert.a
 410000:c00b regs_assert.c
 420000:c00c regs_assert.b
 430000:c00d regs_assert.e
 440000:c00e regs_assert.d
 450000:c00f regs_assert.l
 460000:c010 regs_assert.h
 470000:c011 memdump_len
 480000:c012 memdump_addr
 490001:47f0 memcpy
 500001:47f9 memset
 510001:4802 clear_vram
 520001:480d reset_screen
 530001:481a process_results
 540001:481f _wait_ly_0
 550001:4825 _wait_ly_1
 560001:4841 _wait_ly_2
 570001:4847 _wait_ly_3
 580001:4860 _process_results_cb
 590001:486b _print_sl_data8
 600001:4875 _print_sl_out8
 610001:488f _print_sl_data9
 620001:489a _print_sl_out9
 630001:48b2 _print_sl_data10
 640001:48be _print_sl_out10
 650001:48bf dump_mem
 660001:48cf _wait_ly_4
 670001:48d5 _wait_ly_5
 680001:48f1 _dump_mem_line
 690001:491b _check_asserts
 700001:4929 _print_sl_data11
 710001:492c _print_sl_out11
 720001:4938 _print_sl_data12
 730001:493a _print_sl_out12
 740001:4942 _print_sl_data13
 750001:4945 _print_sl_out13
 760001:494f __check_assert_fail0
 770001:495a _print_sl_data14
 780001:495d _print_sl_out14
 790001:4960 __check_assert_ok0
 800001:4968 _print_sl_data15
 810001:496d _print_sl_out15
 820001:496f __check_assert_skip0
 830001:4977 _print_sl_data16
 840001:497f _print_sl_out16
 850001:497f __check_assert_out0
 860001:498b _print_sl_data17
 870001:498d _print_sl_out17
 880001:4995 _print_sl_data18
 890001:4998 _print_sl_out18
 900001:49a2 __check_assert_fail1
 910001:49ad _print_sl_data19
 920001:49b0 _print_sl_out19
 930001:49b3 __check_assert_ok1
 940001:49bb _print_sl_data20
 950001:49c0 _print_sl_out20
 960001:49c2 __check_assert_skip1
 970001:49ca _print_sl_data21
 980001:49d2 _print_sl_out21
 990001:49d2 __check_assert_out1
1000001:49dd _print_sl_data22
1010001:49e0 _print_sl_out22
1020001:49ec _print_sl_data23
1030001:49ee _print_sl_out23
1040001:49f6 _print_sl_data24
1050001:49f9 _print_sl_out24
1060001:4a03 __check_assert_fail2
1070001:4a0e _print_sl_data25
1080001:4a11 _print_sl_out25
1090001:4a14 __check_assert_ok2
1100001:4a1c _print_sl_data26
1110001:4a21 _print_sl_out26
1120001:4a23 __check_assert_skip2
1130001:4a2b _print_sl_data27
1140001:4a33 _print_sl_out27
1150001:4a33 __check_assert_out2
1160001:4a3f _print_sl_data28
1170001:4a41 _print_sl_out28
1180001:4a49 _print_sl_data29
1190001:4a4c _print_sl_out29
1200001:4a56 __check_assert_fail3
1210001:4a61 _print_sl_data30
1220001:4a64 _print_sl_out30
1230001:4a67 __check_assert_ok3
1240001:4a6f _print_sl_data31
1250001:4a74 _print_sl_out31
1260001:4a76 __check_assert_skip3
1270001:4a7e _print_sl_data32
1280001:4a86 _print_sl_out32
1290001:4a86 __check_assert_out3
1300001:4a91 _print_sl_data33
1310001:4a94 _print_sl_out33
1320001:4aa0 _print_sl_data34
1330001:4aa2 _print_sl_out34
1340001:4aaa _print_sl_data35
1350001:4aad _print_sl_out35
1360001:4ab7 __check_assert_fail4
1370001:4ac2 _print_sl_data36
1380001:4ac5 _print_sl_out36
1390001:4ac8 __check_assert_ok4
1400001:4ad0 _print_sl_data37
1410001:4ad5 _print_sl_out37
1420001:4ad7 __check_assert_skip4
1430001:4adf _print_sl_data38
1440001:4ae7 _print_sl_out38
1450001:4ae7 __check_assert_out4
1460001:4af3 _print_sl_data39
1470001:4af5 _print_sl_out39
1480001:4afd _print_sl_data40
1490001:4b00 _print_sl_out40
1500001:4b0a __check_assert_fail5
1510001:4b15 _print_sl_data41
1520001:4b18 _print_sl_out41
1530001:4b1b __check_assert_ok5
1540001:4b23 _print_sl_data42
1550001:4b28 _print_sl_out42
1560001:4b2a __check_assert_skip5
1570001:4b32 _print_sl_data43
1580001:4b3a _print_sl_out43
1590001:4b3a __check_assert_out5
1600001:4b45 _print_sl_data44
1610001:4b48 _print_sl_out44
1620001:4b54 _print_sl_data45
1630001:4b56 _print_sl_out45
1640001:4b5e _print_sl_data46
1650001:4b61 _print_sl_out46
1660001:4b6b __check_assert_fail6
1670001:4b76 _print_sl_data47
1680001:4b79 _print_sl_out47
1690001:4b7c __check_assert_ok6
1700001:4b84 _print_sl_data48
1710001:4b89 _print_sl_out48
1720001:4b8b __check_assert_skip6
1730001:4b93 _print_sl_data49
1740001:4b9b _print_sl_out49
1750001:4b9b __check_assert_out6
1760001:4ba7 _print_sl_data50
1770001:4ba9 _print_sl_out50
1780001:4bb1 _print_sl_data51
1790001:4bb4 _print_sl_out51
1800001:4bbe __check_assert_fail7
1810001:4bc9 _print_sl_data52
1820001:4bcc _print_sl_out52
1830001:4bcf __check_assert_ok7
1840001:4bd7 _print_sl_data53
1850001:4bdc _print_sl_out53
1860001:4bde __check_assert_skip7
1870001:4be6 _print_sl_data54
1880001:4bee _print_sl_out54
1890001:4bee __check_assert_out7
1900000:01d2 invalid_sp
1910000:01d7 _wait_ly_6
1920000:01dd _wait_ly_7
1930000:01f9 _wait_ly_8
1940000:01ff _wait_ly_9
1950000:0218 _test_failure_cb_0
1960000:0220 _print_sl_data55
1970000:0231 _print_sl_out55
1980000:c014 sp_save