src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/arm/decoder.h>
10#include <mgba/internal/arm/debugger/debugger.h>
11#include <mgba/internal/arm/isa-inlines.h>
12#include <mgba/internal/ds/bios.h>
13
14#include <mgba-util/crc32.h>
15#include <mgba-util/memory.h>
16#include <mgba-util/math.h>
17#include <mgba-util/vfs.h>
18
19#define SLICE_CYCLES 2048
20
21mLOG_DEFINE_CATEGORY(DS, "DS");
22
23const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
24const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
25const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
26const uint8_t DS_CHIP_ID[4] = { 0xC2, 0x0F, 0x00, 0x00 };
27
28static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
29static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
30static const uint8_t DS_ROM_MAGIC_2[] = { 0x1A, 0x9E };
31
32static const size_t DS_FIRMWARE_MAGIC_OFFSET = 0x8;
33static const uint8_t DS_FIRMWARE_MAGIC[] = { 0x4D, 0x41, 0x43 };
34
35enum {
36 DS7_SP_BASE = 0x380FD80,
37 DS7_SP_BASE_IRQ = 0x380FF80,
38 DS7_SP_BASE_SVC = 0x380FFC0,
39
40 DS9_SP_BASE = 0x3002F7C,
41 DS9_SP_BASE_IRQ = 0x3003F80,
42 DS9_SP_BASE_SVC = 0x3003FC0,
43};
44
45static void DSInit(void* cpu, struct mCPUComponent* component);
46
47static void DS7Reset(struct ARMCore* cpu);
48static void DS7TestIRQ(struct ARMCore* cpu);
49static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
50static void DS7ProcessEvents(struct ARMCore* cpu);
51
52static void DS9Reset(struct ARMCore* cpu);
53static void DS9TestIRQ(struct ARMCore* cpu);
54static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
55static uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2);
56static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
57static void DS9ProcessEvents(struct ARMCore* cpu);
58
59static void DSProcessEvents(struct DSCommon* dscore);
60static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
61static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
62static void DSBreakpoint(struct ARMCore* cpu, int immediate);
63
64static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
65 UNUSED(cyclesLate);
66 struct DS* ds = context;
67 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
68 if (ds->activeCpu == ds->ds9.cpu) {
69 ds->activeCpu = ds->ds7.cpu;
70 ds->cycleDrift += cycles;
71 cycles = ds->cycleDrift >> 1;
72 timing = &ds->ds7.timing;
73 } else {
74 ds->activeCpu = ds->ds9.cpu;
75 ds->cycleDrift -= cycles << 1;
76 cycles = ds->cycleDrift + SLICE_CYCLES;
77 timing = &ds->ds9.timing;
78 }
79 mTimingSchedule(timing, &ds->slice, cycles);
80 ds->sliceStart = mTimingCurrentTime(timing);
81 ds->earlyExit = true;
82}
83
84static void _divide(struct mTiming* timing, void* context, uint32_t cyclesLate) {
85 UNUSED(timing);
86 UNUSED(cyclesLate);
87 struct DS* ds = context;
88 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x8000;
89 int64_t numerator;
90 int64_t denominator;
91 LOAD_64LE(numerator, DS9_REG_DIV_NUMER_0, ds->memory.io9);
92 LOAD_64LE(denominator, DS9_REG_DIV_DENOM_0, ds->memory.io9);
93 bool max = false;
94 switch (ds->memory.io9[DS9_REG_DIVCNT >> 1] & 0x3) {
95 case 0:
96 numerator = (int64_t)(int32_t) numerator;
97 case 1:
98 case 3:
99 denominator = (int64_t)(int32_t) denominator;
100 break;
101 }
102 if (numerator == INT64_MIN) {
103 max = true;
104 }
105 if (!denominator) {
106 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
107 STORE_64LE(numerator, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
108 numerator >>= 63LL;
109 numerator = -numerator;
110 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
111 return;
112 }
113 if (denominator == -1LL && max) {
114 ds->memory.io9[DS9_REG_DIVCNT >> 1] |= 0x4000;
115 STORE_64LE(numerator, DS9_REG_DIV_RESULT_0, ds->memory.io9);
116 return;
117 }
118 ds->memory.io9[DS9_REG_DIVCNT >> 1] &= ~0x4000;
119 int64_t result = numerator / denominator;
120 int64_t remainder = numerator % denominator; // TODO: defined behavior for negative denominator?
121 STORE_64LE(result, DS9_REG_DIV_RESULT_0, ds->memory.io9);
122 STORE_64LE(remainder, DS9_REG_DIVREM_RESULT_0, ds->memory.io9);
123}
124
125 static void _sqrt(struct mTiming* timing, void* context, uint32_t cyclesLate) {
126 UNUSED(timing);
127 UNUSED(cyclesLate);
128 struct DS* ds = context;
129 ds->memory.io9[DS9_REG_SQRTCNT >> 1] &= ~0x8000;
130 uint64_t param;
131 LOAD_64LE(param, DS9_REG_SQRT_PARAM_0, ds->memory.io9);
132 if (!(ds->memory.io9[DS9_REG_SQRTCNT >> 1] & 1)) {
133 param &= 0xFFFFFFFFULL;
134 }
135
136 uint64_t result = 0;
137 uint64_t bit = 0x4000000000000000ULL; // The second-to-top bit is set: 1 << 30 for 32 bits
138
139 // "bit" starts at the highest power of four <= the argument.
140 while (bit > param) {
141 bit >>= 2;
142 }
143
144 while (bit != 0) {
145 if (param >= param + bit) {
146 param -= param + bit;
147 param = (result >> 1) + bit;
148 } else {
149 param >>= 1;
150 }
151 bit >>= 2;
152 }
153 STORE_32LE(result, DS9_REG_SQRT_RESULT_LO, ds->memory.io9);
154}
155
156void DSCreate(struct DS* ds) {
157 ds->d.id = DS_COMPONENT_MAGIC;
158 ds->d.init = DSInit;
159 ds->d.deinit = NULL;
160 ds->ds7.p = ds;
161 ds->ds9.p = ds;
162 ds->ds7.cpu = NULL;
163 ds->ds9.cpu = NULL;
164 ds->ds7.ipc = &ds->ds9;
165 ds->ds9.ipc = &ds->ds7;
166}
167
168static void DSInit(void* cpu, struct mCPUComponent* component) {
169 struct DS* ds = (struct DS*) component;
170 struct ARMCore* core = cpu;
171 if (!ds->ds7.cpu) {
172 // The ARM7 must get initialized first
173 ds->ds7.cpu = core;
174 ds->debugger = 0;
175 ds->sync = 0;
176 return;
177 }
178 ds->ds9.cpu = cpu;
179 ds->activeCpu = NULL;
180
181 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
182
183 ds->slice.name = "DS CPU Time Slicing";
184 ds->slice.callback = _slice;
185 ds->slice.context = ds;
186 ds->slice.priority = UINT_MAX;
187
188 CircleBufferInit(&ds->ds7.fifo, 64);
189 CircleBufferInit(&ds->ds9.fifo, 64);
190
191 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
192 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
193 DSMemoryInit(ds);
194 DSDMAInit(ds);
195
196 DSVideoInit(&ds->video);
197 ds->video.p = ds;
198
199 ds->ds7.springIRQ = 0;
200 ds->ds9.springIRQ = 0;
201 DSTimerInit(ds);
202 ds->keySource = NULL;
203 ds->rtcSource = NULL;
204 ds->rumble = NULL;
205
206 ds->romVf = NULL;
207 DSSlot1SPIInit(ds, NULL);
208
209 ds->keyCallback = NULL;
210
211 ds->divEvent.name = "DS Hardware Divide";
212 ds->divEvent.callback = _divide;
213 ds->divEvent.context = ds;
214 ds->divEvent.priority = 0x50;
215
216 ds->sqrtEvent.name = "DS Hardware Sqrt";
217 ds->sqrtEvent.callback = _sqrt;
218 ds->sqrtEvent.context = ds;
219 ds->sqrtEvent.priority = 0x51;
220
221 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
222 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
223}
224
225void DSUnloadROM(struct DS* ds) {
226 if (ds->romVf) {
227 ds->romVf->close(ds->romVf);
228 ds->romVf = NULL;
229 }
230}
231
232void DSDestroy(struct DS* ds) {
233 CircleBufferDeinit(&ds->ds7.fifo);
234 CircleBufferDeinit(&ds->ds9.fifo);
235 DSUnloadROM(ds);
236 DSMemoryDeinit(ds);
237 mTimingDeinit(&ds->ds7.timing);
238 mTimingDeinit(&ds->ds9.timing);
239}
240
241void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
242 irqh->reset = DS7Reset;
243 irqh->processEvents = DS7ProcessEvents;
244 irqh->swi16 = DS7Swi16;
245 irqh->swi32 = DS7Swi32;
246 irqh->hitIllegal = DSIllegal;
247 irqh->readCPSR = DS7TestIRQ;
248 irqh->writeCP15 = NULL;
249 irqh->readCP15 = NULL;
250 irqh->hitStub = DSHitStub;
251 irqh->bkpt16 = DSBreakpoint;
252 irqh->bkpt32 = DSBreakpoint;
253}
254
255void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
256 irqh->reset = DS9Reset;
257 irqh->processEvents = DS9ProcessEvents;
258 irqh->swi16 = DS9Swi16;
259 irqh->swi32 = DS9Swi32;
260 irqh->hitIllegal = DSIllegal;
261 irqh->readCPSR = DS9TestIRQ;
262 irqh->writeCP15 = DS9WriteCP15;
263 irqh->readCP15 = DS9ReadCP15;
264 irqh->hitStub = DSHitStub;
265 irqh->bkpt16 = DSBreakpoint;
266 irqh->bkpt32 = DSBreakpoint;
267}
268
269void DS7Reset(struct ARMCore* cpu) {
270 ARMSetPrivilegeMode(cpu, MODE_IRQ);
271 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
272 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
273 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
274 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
275 cpu->gprs[ARM_SP] = DS7_SP_BASE;
276
277 struct DS* ds = (struct DS*) cpu->master;
278 mTimingClear(&ds->ds7.timing);
279 CircleBufferInit(&ds->ds7.fifo, 64);
280 DSMemoryReset(ds);
281 DSDMAReset(&ds->ds7);
282 DS7IOInit(ds);
283
284 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
285 if (header) {
286 memcpy(&ds->memory.ram[0x3FF800 >> 2], DS_CHIP_ID, 4);
287 memcpy(&ds->memory.ram[0x3FF804 >> 2], DS_CHIP_ID, 4);
288 memcpy(&ds->memory.ram[0x3FFC00 >> 2], DS_CHIP_ID, 4);
289 memcpy(&ds->memory.ram[0x3FFC04 >> 2], DS_CHIP_ID, 4);
290 memcpy(&ds->memory.ram[0x3FFE00 >> 2], header, 0x170);
291 DS7IOWrite32(ds, DS_REG_ROMCNT_LO, header->busTiming | 0x2700000);
292 // TODO: Error check
293 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
294 uint32_t base = header->arm7Base - DS_BASE_RAM;
295 uint32_t* basePointer = &ds->memory.ram[base >> 2];
296 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
297 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
298 }
299 cpu->gprs[12] = header->arm7Entry;
300 cpu->gprs[ARM_LR] = header->arm7Entry;
301 cpu->gprs[ARM_PC] = header->arm7Entry;
302 int currentCycles = 0;
303 ARM_WRITE_PC;
304
305 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
306 }
307}
308
309void DS9Reset(struct ARMCore* cpu) {
310 ARMSetPrivilegeMode(cpu, MODE_IRQ);
311 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
312 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
313 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
314 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
315 cpu->gprs[ARM_SP] = DS9_SP_BASE;
316
317 struct DS* ds = (struct DS*) cpu->master;
318 mTimingClear(&ds->ds9.timing);
319 CircleBufferInit(&ds->ds9.fifo, 64);
320 DSVideoReset(&ds->video);
321 DSDMAReset(&ds->ds9);
322 DS9IOInit(ds);
323
324 ds->activeCpu = cpu;
325 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
326 ds->cycleDrift = 0;
327 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
328
329 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
330 if (header) {
331 // TODO: Error check
332 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
333 uint32_t base = header->arm9Base - DS_BASE_RAM;
334 uint32_t* basePointer = &ds->memory.ram[base >> 2];
335 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
336 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
337 }
338 cpu->gprs[12] = header->arm9Entry;
339 cpu->gprs[ARM_LR] = header->arm9Entry;
340 cpu->gprs[ARM_PC] = header->arm9Entry;
341 int currentCycles = 0;
342 ARM_WRITE_PC;
343
344 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
345 }
346}
347
348static void DS7ProcessEvents(struct ARMCore* cpu) {
349 struct DS* ds = (struct DS*) cpu->master;
350 DSProcessEvents(&ds->ds7);
351}
352
353static void DS9ProcessEvents(struct ARMCore* cpu) {
354 struct DS* ds = (struct DS*) cpu->master;
355 DSProcessEvents(&ds->ds9);
356}
357
358static void DSProcessEvents(struct DSCommon* dscore) {
359 struct ARMCore* cpu = dscore->cpu;
360 struct DS* ds = dscore->p;
361 if (dscore->springIRQ && !cpu->cpsr.i) {
362 ARMRaiseIRQ(cpu);
363 dscore->springIRQ = 0;
364 }
365
366 int32_t nextEvent = cpu->nextEvent;
367 while (cpu->cycles >= nextEvent) {
368 int32_t cycles = cpu->cycles;
369
370 cpu->cycles = 0;
371 cpu->nextEvent = 0;
372
373#ifndef NDEBUG
374 if (cycles < 0) {
375 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
376 }
377#endif
378 nextEvent = cycles;
379 do {
380 nextEvent = mTimingTick(&dscore->timing, nextEvent);
381 } while (ds->cpuBlocked);
382
383 if (ds->earlyExit) {
384 ds->earlyExit = false;
385 break;
386 }
387
388 cpu->nextEvent = nextEvent;
389 if (cpu->halted) {
390 cpu->cycles = nextEvent;
391 }
392#ifndef NDEBUG
393 else if (nextEvent < 0) {
394 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
395 }
396#endif
397 }
398}
399
400void DSRunLoop(struct DS* ds) {
401 if (ds->activeCpu == ds->ds9.cpu) {
402 ARMv5RunLoop(ds->ds9.cpu);
403 } else {
404 ARMv4RunLoop(ds->ds7.cpu);
405 }
406}
407
408void DS7Step(struct DS* ds) {
409 int32_t pc = ds->ds7.cpu->gprs[ARM_PC];
410 do {
411 while (ds->activeCpu == ds->ds9.cpu) {
412 ARMv5RunLoop(ds->ds9.cpu);
413 }
414 ARMv4Run(ds->ds7.cpu);
415 } while (ds->ds7.cpu->halted || ds->ds7.cpu->gprs[ARM_PC] == pc);
416}
417
418void DS9Step(struct DS* ds) {
419 int32_t pc = ds->ds9.cpu->gprs[ARM_PC];
420 do {
421 while (ds->activeCpu == ds->ds7.cpu) {
422 ARMv4RunLoop(ds->ds7.cpu);
423 }
424 ARMv5Run(ds->ds9.cpu);
425 } while (ds->ds9.cpu->halted || ds->ds9.cpu->gprs[ARM_PC] == pc);
426}
427
428void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
429 ds->debugger = (struct ARMDebugger*) debugger->platform;
430 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
431 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
432 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
433 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
434}
435
436void DSDetachDebugger(struct DS* ds) {
437 ds->debugger = NULL;
438 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
439 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
440 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
441 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
442}
443
444bool DSLoadROM(struct DS* ds, struct VFile* vf) {
445 DSUnloadROM(ds);
446 ds->romVf = vf;
447 // TODO: error check
448 return true;
449}
450
451bool DSLoadSave(struct DS* ds, struct VFile* sav) {
452 DSSlot1SPIInit(ds, sav);
453 return true;
454}
455
456bool DSIsROM(struct VFile* vf) {
457 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
458 return false;
459 }
460 uint8_t signature[sizeof(DS_ROM_MAGIC)];
461 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
462 return false;
463 }
464 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0 || memcmp(signature, DS_ROM_MAGIC_2, sizeof(signature)) == 0;
465}
466
467bool DSIsBIOS7(struct VFile* vf) {
468 size_t size = vf->size(vf);
469 void* data = NULL;
470 uint32_t crc;
471 if (size == DS7_SIZE_BIOS) {
472 data = vf->map(vf, size, MAP_READ);
473 }
474 if (!data) {
475 return false;
476 }
477 crc = doCrc32(data, size);
478 vf->unmap(vf, data, size);
479 return crc == DS7_BIOS_CHECKSUM;
480}
481
482bool DSIsBIOS9(struct VFile* vf) {
483 size_t size = vf->size(vf);
484 void* data = NULL;
485 uint32_t crc;
486 if (size == DS9_SIZE_BIOS) {
487 data = vf->map(vf, 0x1000, MAP_READ);
488 } else if (size == 0x1000) {
489 data = vf->map(vf, 0x1000, MAP_READ);
490 }
491 if (!data) {
492 return false;
493 }
494 crc = doCrc32(data, 0x1000);
495 vf->unmap(vf, data, 0x1000);
496 return crc == DS9_BIOS_CHECKSUM;
497}
498
499bool DSIsFirmware(struct VFile* vf) {
500 if (vf->seek(vf, DS_FIRMWARE_MAGIC_OFFSET, SEEK_SET) < 0) {
501 return false;
502 }
503 uint8_t signature[sizeof(DS_FIRMWARE_MAGIC)];
504 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
505 return false;
506 }
507 return memcmp(signature, DS_FIRMWARE_MAGIC, sizeof(signature)) == 0;
508}
509
510bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
511 size_t size = vf->size(vf);
512 void* data = NULL;
513 uint32_t crc;
514 if (size == DS7_SIZE_BIOS) {
515 data = vf->map(vf, size, MAP_READ);
516 } else if (size == 0x1000) {
517 data = calloc(DS9_SIZE_BIOS, 1);
518 vf->read(vf, data, size);
519 } else if (size == DS9_SIZE_BIOS) {
520 data = vf->map(vf, size, MAP_READ);
521 } else if (size == DS_SIZE_FIRMWARE) {
522 return DSLoadFirmware(ds, vf);
523 }
524 if (!data) {
525 return false;
526 }
527 crc = doCrc32(data, size);
528 if (crc == DS7_BIOS_CHECKSUM) {
529 ds->bios7Vf = vf;
530 ds->memory.bios7 = data;
531 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
532 } else if (crc == DS9_BIOS_CHECKSUM) {
533 ds->bios9Vf = vf;
534 ds->memory.bios9 = data;
535 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
536 } else {
537 mLOG(DS, WARN, "BIOS checksum incorrect");
538 vf->unmap(vf, data, size);
539 return false;
540 }
541 return true;
542}
543
544bool DSLoadFirmware(struct DS* ds, struct VFile* vf) {
545 size_t size = vf->size(vf);
546 void* data = NULL;
547 if (!DSIsFirmware(vf)) {
548 return false;
549 }
550 if (size == DS_SIZE_FIRMWARE) {
551 data = vf->map(vf, size, MAP_WRITE);
552 }
553 if (!data) {
554 return false;
555 }
556 mLOG(DS, INFO, "Found DS firmware");
557 ds->firmwareVf = vf;
558 return true;
559}
560
561void DSGetGameCode(struct DS* ds, char* out) {
562 memset(out, 0, 8);
563 if (!ds->romVf) {
564 return;
565 }
566
567 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
568 // TODO: TWL-?
569 memcpy(out, "NTR-", 4);
570 memcpy(&out[4], &cart->id, 4);
571 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
572}
573
574void DSGetGameTitle(struct DS* ds, char* out) {
575 memset(out, 0, 12);
576 if (!ds->romVf) {
577 return;
578 }
579
580 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
581 memcpy(out, &cart->title, 12);
582 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
583}
584
585void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
586 struct DS* ds = (struct DS*) cpu->master;
587 if (ds->debugger) {
588 struct mDebuggerEntryInfo info = {
589 .address = _ARMPCAddress(cpu),
590 .opcode = opcode
591 };
592 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
593 }
594 // TODO: More sensible category?
595 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
596}
597
598void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
599 struct DS* ds = (struct DS*) cpu->master;
600 if ((opcode & 0xFFFF) == (redzoneInstruction & 0xFFFF)) {
601 int currentCycles = 0;
602 if (cpu->executionMode == MODE_THUMB) {
603 cpu->gprs[ARM_PC] -= WORD_SIZE_THUMB * 2;
604 THUMB_WRITE_PC;
605 } else {
606 cpu->gprs[ARM_PC] -= WORD_SIZE_ARM * 2;
607 ARM_WRITE_PC;
608 }
609 } else if (ds->debugger) {
610 struct mDebuggerEntryInfo info = {
611 .address = _ARMPCAddress(cpu),
612 .opcode = opcode
613 };
614 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
615 } else {
616 ARMRaiseUndefined(cpu);
617 }
618}
619
620void DSBreakpoint(struct ARMCore* cpu, int immediate) {
621 struct DS* ds = (struct DS*) cpu->master;
622 if (immediate >= CPU_COMPONENT_MAX) {
623 return;
624 }
625 switch (immediate) {
626 case CPU_COMPONENT_DEBUGGER:
627 if (ds->debugger) {
628 struct mDebuggerEntryInfo info = {
629 .address = _ARMPCAddress(cpu)
630 };
631 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
632 }
633 break;
634 default:
635 break;
636 }
637}
638
639void DS7TestIRQ(struct ARMCore* cpu) {
640 struct DS* ds = (struct DS*) cpu->master;
641 if (!ds->memory.io7[DS_REG_IME >> 1]) {
642 return;
643 }
644 uint32_t test = (ds->memory.io7[DS_REG_IE_LO >> 1] & ds->memory.io7[DS_REG_IF_LO >> 1]);
645 test |= (ds->memory.io7[DS_REG_IE_HI >> 1] & ds->memory.io7[DS_REG_IF_HI >> 1]) << 16;
646 if (test) {
647 ds->ds7.springIRQ = test;
648 cpu->nextEvent = cpu->cycles;
649 }
650}
651
652void DS9TestIRQ(struct ARMCore* cpu) {
653 struct DS* ds = (struct DS*) cpu->master;
654 if (!ds->memory.io9[DS_REG_IME >> 1]) {
655 return;
656 }
657 uint32_t test = (ds->memory.io9[DS_REG_IE_LO >> 1] & ds->memory.io9[DS_REG_IF_LO >> 1]);
658 test |= (ds->memory.io9[DS_REG_IE_HI >> 1] & ds->memory.io9[DS_REG_IF_HI >> 1]) << 16;
659 if (test) {
660 ds->ds9.springIRQ = test;
661 cpu->nextEvent = cpu->cycles;
662 }
663}
664
665static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
666 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
667}
668
669static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
670 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
671 switch (opcode2) {
672 case 0:
673 cpu->cp15.r2.d = value;
674 break;
675 case 1:
676 cpu->cp15.r2.i = value;
677 break;
678 default:
679 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
680 break;
681 }
682}
683
684static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
685 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
686 switch (opcode2) {
687 case 0:
688 cpu->cp15.r3.d = value;
689 break;
690 default:
691 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
692 break;
693 }
694}
695
696static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
697 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
698}
699
700static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
701 cpu->cp15.r6.region[crm] = value;
702 uint32_t base = ARMProtectionGetBase(value) << 12;
703 uint32_t size = 2 << ARMProtectionGetSize(value);
704 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
705}
706
707static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
708 switch (crm) {
709 case 0:
710 if (opcode2 == 4) {
711 ARMHalt(cpu);
712 return;
713 }
714 break;
715 }
716 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
717}
718
719static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
720 uint32_t base = ARMTCMControlGetBase(value) << 12;
721 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
722 struct DS* ds = (struct DS*) cpu->master;
723 mLOG(DS, DEBUG, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
724 switch (opcode2) {
725 case 0:
726 cpu->cp15.r9.d = value;
727 ds->memory.dtcmBase = base;
728 ds->memory.dtcmSize = size;
729 break;
730 case 1:
731 cpu->cp15.r9.i = value;
732 ds->memory.itcmSize = size;
733 break;
734 default:
735 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
736 break;
737 }
738}
739
740void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
741 switch (crn) {
742 default:
743 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
744 break;
745 case 0:
746 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
747 ARMRaiseUndefined(cpu);
748 break;
749 case 1:
750 _writeSysControl(cpu, crm, opcode2, value);
751 break;
752 case 2:
753 _writeCacheControl(cpu, crm, opcode2, value);
754 break;
755 case 3:
756 _writeWriteBufferControl(cpu, crm, opcode2, value);
757 break;
758 case 5:
759 _writeAccessControl(cpu, crm, opcode2, value);
760 break;
761 case 6:
762 _writeRegionConfiguration(cpu, crm, opcode2, value);
763 break;
764 case 7:
765 _writeCache(cpu, crm, opcode2, value);
766 break;
767 case 9:
768 _writeTCMControl(cpu, crm, opcode2, value);
769 break;
770 }
771}
772
773static uint32_t _readTCMControl(struct ARMCore* cpu, int crm, int opcode2) {
774 switch (opcode2) {
775 case 0:
776 return cpu->cp15.r9.d;
777 case 1:
778 return cpu->cp15.r9.i;
779 default:
780 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
781 return 0;
782 }
783}
784
785uint32_t DS9ReadCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2) {
786 switch (crn) {
787 default:
788 mLOG(DS, STUB, "CP15 unknown read: CRn: %i, CRm: %i, Op1: %i, Op2: %i", crn, crm, opcode1, opcode2);
789 return 0;
790 case 9:
791 return _readTCMControl(cpu, crm, opcode2);
792 }
793}
794
795void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
796 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
797 ARMRaiseIRQ(cpu);
798 }
799}
800void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
801 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
802 ARMRaiseIRQ(cpu);
803 }
804}
805
806void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
807 if (irq < 16) {
808 io[DS_REG_IF_LO >> 1] |= 1 << irq;
809 } else {
810 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
811 }
812
813 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
814 cpu->halted = 0;
815 if (io[DS_REG_IME >> 1]) {
816 ARMRaiseIRQ(cpu);
817 }
818 }
819}
820
821void DSFrameStarted(struct DS* ds) {
822 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
823 if (callbacks && callbacks->videoFrameStarted) {
824 callbacks->videoFrameStarted(callbacks->context);
825 }
826}
827
828void DSFrameEnded(struct DS* ds) {
829 struct mCoreCallbacks* callbacks = ds->coreCallbacks;
830 if (callbacks && callbacks->videoFrameEnded) {
831 callbacks->videoFrameEnded(callbacks->context);
832 }
833}