include/mgba/internal/gb/serialize.h (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#ifndef GB_SERIALIZE_H
7#define GB_SERIALIZE_H
8
9#include <mgba-util/common.h>
10
11CXX_GUARD_START
12
13#include <mgba/core/core.h>
14#include <mgba/internal/gb/gb.h>
15
16extern const uint32_t GB_SAVESTATE_MAGIC;
17extern const uint32_t GB_SAVESTATE_VERSION;
18
19mLOG_DECLARE_CATEGORY(GB_STATE);
20
21/* Savestate format:
22 * 0x00000 - 0x00003: Version Magic (0x01000002)
23 * 0x00004 - 0x00007: ROM CRC32
24 * 0x00008: Game Boy model
25 * 0x00009 - 0x0000B: Reserved (leave zero)
26 * 0x0000C - 0x0000F: Master cycles
27 * 0x00010 - 0x0001F: Game title/code (e.g. PM_CRYSTALBYTE)
28 * 0x00020 - 0x00047: CPU state:
29 * | 0x00020: A register
30 * | 0x00021: F register
31 * | 0x00022: B register
32 * | 0x00023: C register
33 * | 0x00024: D register
34 * | 0x00025: E register
35 * | 0x00026: H register
36 * | 0x00027: L register
37 * | 0x00028 - 0x00029: SP register
38 * | 0x0002A - 0x0002B: PC register
39 * | 0x0002C - 0x0002F: Cycles since last event
40 * | 0x00030 - 0x00033: Cycles until next event
41 * | 0x00034 - 0x00035: Reserved (current instruction)
42 * | 0x00036 - 0x00037: Index address
43 * | 0x00038: Bus value
44 * | 0x00039: Execution state
45 * | 0x0003A - 0x0003B: Reserved
46 * | 0x0003C - 0x0003F: EI pending cycles
47 * | 0x00040 - 0x00043: Reserved (DI pending cycles)
48 * | 0x00044 - 0x00047: Flags
49 * | bit 0: Is condition met?
50 * | bit 1: Is IRQ pending?
51 * | bit 2: Double speed
52 * | bit 3: Is EI pending?
53 * | bits 4 - 31: Reserved
54 * 0x00048 - 0x0005B: Audio channel 1/framer state
55 * | 0x00048 - 0x0004B: Envelepe timing
56 * | bits 0 - 6: Remaining length
57 * | bits 7 - 9: Next step
58 * | bits 10 - 20: Shadow frequency register
59 * | bits 21 - 31: Reserved
60 * | 0x0004C - 0x0004F: Next frame
61 * | 0x00050 - 0x00053: Next channel 3 fade
62 * | 0x00054 - 0x00057: Sweep state
63 * | bits 0 - 2: Timesteps
64 * | bits 3 - 31: Reserved
65 * | 0x00058 - 0x0005B: Next event
66 * 0x0005C - 0x0006B: Audio channel 2 state
67 * | 0x0005C - 0x0005F: Envelepe timing
68 * | bits 0 - 2: Remaining length
69 * | bits 3 - 5: Next step
70 * | bits 6 - 31: Reserved
71 * | 0x00060 - 0x00067: Reserved
72 * | 0x00068 - 0x0006B: Next event
73 * 0x0006C - 0x00093: Audio channel 3 state
74 * | 0x0006C - 0x0008B: Wave banks
75 * | 0x0008C - 0x0008D: Remaining length
76 * | 0x0008E - 0x0008F: Reserved
77 * | 0x00090 - 0x00093: Next event
78 * 0x00094 - 0x000A3: Audio channel 4 state
79 * | 0x00094 - 0x00097: Linear feedback shift register state
80 * | 0x00098 - 0x0009B: Envelepe timing
81 * | bits 0 - 2: Remaining length
82 * | bits 3 - 5: Next step
83 * | bits 6 - 31: Reserved
84 * | 0x0009C - 0x0009F: Last event
85 * | 0x000A0 - 0x000A3: Next event
86 * 0x000A4 - 0x000B7: Audio miscellaneous state
87 * | TODO: Fix this, they're in big-endian order, but field is little-endian
88 * | 0x000A4: Channel 1 envelope state
89 * | bits 0 - 3: Current volume
90 * | bits 4 - 5: Is dead?
91 * | bit 6: Is high?
92* | bit 7: Reserved
93 * | 0x000A5: Channel 2 envelope state
94 * | bits 0 - 3: Current volume
95 * | bits 4 - 5: Is dead?
96 * | bit 6: Is high?
97* | bit 7: Reserved
98 * | 0x000A6: Channel 4 envelope state
99 * | bits 0 - 3: Current volume
100 * | bits 4 - 5: Is dead?
101 * | bits 6 - 7: Current frame (continued)
102 * | 0x000A7: Miscellaneous audio flags
103 * | bit 0: Current frame (continuation)
104 * | bit 1: Is channel 1 sweep enabled?
105 * | bit 2: Has channel 1 sweep occurred?
106 * | bit 3: Is channel 3's memory readable?
107 * | bit 4: Skip frame
108 * | bits 5 - 7: Reserved
109 * | 0x000A8 - 0x000AB: Left capacitor charge
110 * | 0x000AC - 0x000AF: Right capacitor charge
111 * | 0x000B0 - 0x000B3: Next sample
112 * 0x000B4 - 0x000153: Video state
113 * | 0x000B4 - 0x000B5: Current x
114 * | 0x000B6 - 0x000B7: Current y (ly)
115 * | 0x000B8 - 0x000BB: Next frame
116 * | 0x000BC - 0x000BF: Reserved
117 * | 0x000C0 - 0x000C3: Next mode
118 * | 0x000C4 - 0x000C7: Dot cycle counter
119 * | 0x000C8 - 0x000CB: Frame counter
120 * | 0x000CC: Current VRAM bank
121 * | 0x000CD: Palette flags
122 * | bit 0: BCP increment
123 * | bit 1: OCP increment
124 * | bits 2 - 3: Mode
125 * | bits 4 - 7: Reserved
126 * | 0x000CE - 0x000CF: Reserved
127 * | 0x000D0 - 0x000D1: BCP index
128 * | 0x000D1 - 0x000D3: OCP index
129 * | 0x000D4 - 0x00153: Palette entries
130 * 0x00154 - 0x000167: Timer state
131 * | 0x00154 - 0x00157: Next event
132 * | 0x00158 - 0x0015B: Next IRQ
133 * | 0x0015C - 0x0015F: Next DIV
134 * | 0x00160 - 0x00163: Inernal DIV
135 * | 0x00164: TIMA period
136 * | 0x00165: Flags
137 * | bit 0: Is IRQ pending?
138 * | 0x00166 - 0x00167: Reserved
139 * 0x000168 - 0x000197: Memory state
140 * | 0x00168 - 0x00169: Current ROM bank
141 * | 0x0016A: Current WRAM bank
142 * | 0x0016B: Current SRAM bank
143 * | 0x0016C - 0x0016F: Next DMA
144 * | 0x00170 - 0x00171: Next DMA source
145 * | 0x00172 - 0x00173: Next DMA destination
146 * | 0x00174 - 0x00177: Next HDMA
147 * | 0x00178 - 0x00179: Next HDMA source
148 * | 0x0017A - 0x0017B: Next HDMA destination
149 * | 0x0017C - 0x0017D: HDMA remaining
150 * | 0x0017E: DMA remaining
151 * | 0x0017F - 0x00183: RTC registers
152 * | 0x00184 - 0x00193: MBC state
153 * | 0x00194 - 0x00195: Flags
154 * | bit 0: SRAM accessable
155 * | bit 1: RTC accessible
156 * | bit 2: RTC latched
157 * | bit 3: IME
158 * | bit 4: Is HDMA active?
159 * | bits 5 - 7: Active RTC register
160 * | 0x00196 - 0x00197: Reserved (leave zero)
161 * 0x00198 - 0x0019F: Global cycle counter
162 * 0x001A0 - 0x0025F: Reserved (leave zero)
163 * 0x00260 - 0x002FF: OAM
164 * 0x00300 - 0x0037F: I/O memory
165 * 0x00380 - 0x003FE: HRAM
166 * 0x003FF: Interrupts enabled
167 * 0x00400 - 0x043FF: VRAM
168 * 0x04400 - 0x0C3FF: WRAM
169 * 0x0C400 - 0x0C77F: Reserved
170 * 0x0C780 - 0x117FF: Super Game Boy
171 * | 0x0C780 - 0x0C7D9: Current attributes
172 * | 0x0C7DA: Current command
173 * | 0x0C7DB: Current bit count
174 * | 0x0C7DC - 0x0C7DF: Flags
175 * | bits 0 - 1: Current P1 bits
176 * | bits 2 - 3: Current render mode
177 * | bit 4: Is a mode event not scheduled?
178 * | bit 5: Is a frame event not scheduled?
179 * | bits 6 - 31: Reserved (leave 0)
180 * | 0x0C7E0 - 0x0C7EF: Current packet
181 * | 0x0C7F0 - 0x0C7FF: Reserved
182 * | 0x0C800 - 0x0E7FF: Character VRAM
183 * | 0x0E800 - 0x0F7FF: Tile map VRAM
184 * | 0x0F800 - 0x107FF: Palette VRAM
185 * | 0x10800 - 0x117FF: Attribute file
186 * Total size: 0x11800 (71,680) bytes
187*/
188
189DECL_BITFIELD(GBSerializedAudioFlags, uint32_t);
190DECL_BITS(GBSerializedAudioFlags, Ch1Volume, 0, 4);
191DECL_BITS(GBSerializedAudioFlags, Ch1Dead, 4, 2);
192DECL_BIT(GBSerializedAudioFlags, Ch1Hi, 6);
193DECL_BITS(GBSerializedAudioFlags, Ch2Volume, 8, 4);
194DECL_BITS(GBSerializedAudioFlags, Ch2Dead, 12, 2);
195DECL_BIT(GBSerializedAudioFlags, Ch2Hi, 14);
196DECL_BITS(GBSerializedAudioFlags, Ch4Volume, 16, 4);
197DECL_BITS(GBSerializedAudioFlags, Ch4Dead, 20, 2);
198DECL_BITS(GBSerializedAudioFlags, Frame, 22, 3);
199DECL_BIT(GBSerializedAudioFlags, Ch1SweepEnabled, 25);
200DECL_BIT(GBSerializedAudioFlags, Ch1SweepOccurred, 26);
201DECL_BIT(GBSerializedAudioFlags, Ch3Readable, 27);
202DECL_BIT(GBSerializedAudioFlags, SkipFrame, 28);
203
204DECL_BITFIELD(GBSerializedAudioEnvelope, uint32_t);
205DECL_BITS(GBSerializedAudioEnvelope, Length, 0, 7);
206DECL_BITS(GBSerializedAudioEnvelope, NextStep, 7, 3);
207DECL_BITS(GBSerializedAudioEnvelope, Frequency, 10, 11);
208
209
210DECL_BITFIELD(GBSerializedAudioSweep, uint32_t);
211DECL_BITS(GBSerializedAudioSweep, Time, 0, 3);
212
213struct GBSerializedPSGState {
214 struct {
215 GBSerializedAudioEnvelope envelope;
216 int32_t nextFrame;
217 int32_t nextCh3Fade;
218 GBSerializedAudioSweep sweep;
219 uint32_t nextEvent;
220 } ch1;
221 struct {
222 GBSerializedAudioEnvelope envelope;
223 int32_t reserved[2];
224 int32_t nextEvent;
225 } ch2;
226 struct {
227 uint32_t wavebanks[8];
228 int16_t length;
229 int16_t reserved;
230 uint32_t nextEvent;
231 } ch3;
232 struct {
233 int32_t lfsr;
234 GBSerializedAudioEnvelope envelope;
235 int32_t lastEvent;
236 uint32_t nextEvent;
237 } ch4;
238};
239
240DECL_BITFIELD(GBSerializedCpuFlags, uint32_t);
241DECL_BIT(GBSerializedCpuFlags, Condition, 0);
242DECL_BIT(GBSerializedCpuFlags, IrqPending, 1);
243DECL_BIT(GBSerializedCpuFlags, DoubleSpeed, 2);
244DECL_BIT(GBSerializedCpuFlags, EiPending, 3);
245DECL_BIT(GBSerializedCpuFlags, Halted, 4);
246DECL_BIT(GBSerializedCpuFlags, Blocked, 5);
247
248DECL_BITFIELD(GBSerializedTimerFlags, uint8_t);
249DECL_BIT(GBSerializedTimerFlags, IrqPending, 0);
250
251DECL_BITFIELD(GBSerializedVideoFlags, uint8_t);
252DECL_BIT(GBSerializedVideoFlags, BcpIncrement, 0);
253DECL_BIT(GBSerializedVideoFlags, OcpIncrement, 1);
254DECL_BITS(GBSerializedVideoFlags, Mode, 2, 2);
255DECL_BIT(GBSerializedVideoFlags, NotModeEventScheduled, 4);
256DECL_BIT(GBSerializedVideoFlags, NotFrameEventScheduled, 5);
257
258DECL_BITFIELD(GBSerializedMBC7Flags, uint8_t);
259DECL_BITS(GBSerializedMBC7Flags, Command, 0, 2);
260DECL_BIT(GBSerializedMBC7Flags, Writable, 2);
261
262DECL_BITFIELD(GBSerializedMemoryFlags, uint16_t);
263DECL_BIT(GBSerializedMemoryFlags, SramAccess, 0);
264DECL_BIT(GBSerializedMemoryFlags, RtcAccess, 1);
265DECL_BIT(GBSerializedMemoryFlags, RtcLatched, 2);
266DECL_BIT(GBSerializedMemoryFlags, Ime, 3);
267DECL_BIT(GBSerializedMemoryFlags, IsHdma, 4);
268DECL_BITS(GBSerializedMemoryFlags, ActiveRtcReg, 5, 3);
269
270DECL_BITFIELD(GBSerializedSGBFlags, uint32_t);
271DECL_BITS(GBSerializedSGBFlags, P1Bits, 0, 2);
272DECL_BITS(GBSerializedSGBFlags, RenderMode, 2, 2);
273DECL_BITS(GBSerializedSGBFlags, BufferIndex, 4, 3);
274DECL_BITS(GBSerializedSGBFlags, CurrentController, 7, 2);
275DECL_BITS(GBSerializedSGBFlags, ReqControllers, 9, 2);
276DECL_BIT(GBSerializedSGBFlags, Increment, 11);
277
278#pragma pack(push, 1)
279struct GBSerializedState {
280 uint32_t versionMagic;
281 uint32_t romCrc32;
282 uint8_t model;
283 uint8_t reservedHeader[3];
284 uint32_t masterCycles;
285
286 char title[16];
287
288 struct {
289 uint8_t a;
290 uint8_t f;
291 uint8_t b;
292 uint8_t c;
293 uint8_t d;
294 uint8_t e;
295 uint8_t h;
296 uint8_t l;
297 uint16_t sp;
298 uint16_t pc;
299
300 int32_t cycles;
301 int32_t nextEvent;
302
303 uint16_t reservedInstruction;
304 uint16_t index;
305 uint8_t bus;
306 uint8_t executionState;
307
308 uint16_t reserved;
309
310 uint32_t eiPending;
311 int32_t reservedDiPending;
312 GBSerializedCpuFlags flags;
313 } cpu;
314
315 struct {
316 struct GBSerializedPSGState psg;
317 GBSerializedAudioFlags flags;
318 int32_t capLeft;
319 int32_t capRight;
320 uint32_t nextSample;
321 } audio;
322
323 struct {
324 int16_t x;
325 int16_t ly;
326 uint32_t nextFrame;
327 uint32_t reserved;
328 uint32_t nextMode;
329 int32_t dotCounter;
330 int32_t frameCounter;
331
332 uint8_t vramCurrentBank;
333 GBSerializedVideoFlags flags;
334 uint16_t reserved2;
335
336 uint16_t bcpIndex;
337 uint16_t ocpIndex;
338
339 uint16_t palette[64];
340 } video;
341
342 struct {
343 uint32_t nextEvent;
344 uint32_t nextIRQ;
345
346 uint32_t nextDiv;
347 uint32_t internalDiv;
348 uint8_t timaPeriod;
349 GBSerializedTimerFlags flags;
350 uint16_t reserved;
351 } timer;
352
353 struct {
354 uint16_t currentBank;
355 uint8_t wramCurrentBank;
356 uint8_t sramCurrentBank;
357
358 uint32_t dmaNext;
359 uint16_t dmaSource;
360 uint16_t dmaDest;
361
362 uint32_t hdmaNext;
363 uint16_t hdmaSource;
364 uint16_t hdmaDest;
365
366 uint16_t hdmaRemaining;
367 uint8_t dmaRemaining;
368 uint8_t rtcRegs[5];
369
370 union {
371 struct {
372 uint8_t mode;
373 uint8_t multicartStride;
374 uint8_t bankLo;
375 uint8_t bankHi;
376 } mbc1;
377 struct {
378 uint64_t lastLatch;
379 } rtc;
380 struct {
381 uint8_t state;
382 GBMBC7Field eeprom;
383 uint8_t address;
384 uint8_t access;
385 uint8_t latch;
386 uint8_t srBits;
387 uint16_t sr;
388 uint32_t writable;
389 } mbc7;
390 struct {
391 uint8_t locked;
392 uint8_t bank0;
393 } mmm01;
394 struct {
395 uint8_t dataSwapMode;
396 uint8_t bankSwapMode;
397 } bbd;
398 struct {
399 uint8_t reserved[16];
400 } padding;
401 };
402
403 GBSerializedMemoryFlags flags;
404 uint16_t reserved;
405 } memory;
406
407 uint64_t globalCycles;
408
409 uint32_t reserved[48];
410
411 uint8_t oam[GB_SIZE_OAM];
412
413 uint8_t io[GB_SIZE_IO];
414 uint8_t hram[GB_SIZE_HRAM];
415 uint8_t ie;
416
417 uint8_t vram[GB_SIZE_VRAM];
418 uint8_t wram[GB_SIZE_WORKING_RAM];
419
420 uint32_t reserved2[0xC4];
421
422 struct {
423 uint8_t attributes[90];
424 uint8_t command;
425 uint8_t bits;
426 GBSerializedSGBFlags flags;
427 uint8_t inProgressPacket[16];
428 uint8_t packet[128];
429 uint8_t charRam[SGB_SIZE_CHAR_RAM];
430 uint8_t mapRam[SGB_SIZE_MAP_RAM];
431 uint8_t palRam[SGB_SIZE_PAL_RAM];
432 uint8_t atfRam[SGB_SIZE_ATF_RAM];
433 } sgb;
434};
435#pragma pack(pop)
436
437bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state);
438void GBSerialize(struct GB* gb, struct GBSerializedState* state);
439
440CXX_GUARD_END
441
442#endif