1; this file was created with wlalink by ville helin <vhelin@iki.fi>.
  2; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/intr_2_oam_ok_timing.gb".
  3
  4[labels]
  501:47f0 check_asserts_cb
  601:4842 check_asserts_cb@check_asserts
  701:4864 check_asserts_cb@fail0
  801:4870 check_asserts_cb@ok0
  901:487a check_asserts_cb@skip0
 1001:4885 check_asserts_cb@out0
 1101:489c check_asserts_cb@fail1
 1201:48a8 check_asserts_cb@ok1
 1301:48b2 check_asserts_cb@skip1
 1401:48bd check_asserts_cb@out1
 1501:48dd check_asserts_cb@fail2
 1601:48e9 check_asserts_cb@ok2
 1701:48f3 check_asserts_cb@skip2
 1801:48fe check_asserts_cb@out2
 1901:4915 check_asserts_cb@fail3
 2001:4921 check_asserts_cb@ok3
 2101:492b check_asserts_cb@skip3
 2201:4936 check_asserts_cb@out3
 2301:4956 check_asserts_cb@fail4
 2401:4962 check_asserts_cb@ok4
 2501:496c check_asserts_cb@skip4
 2601:4977 check_asserts_cb@out4
 2701:498e check_asserts_cb@fail5
 2801:499a check_asserts_cb@ok5
 2901:49a4 check_asserts_cb@skip5
 3001:49af check_asserts_cb@out5
 3101:49cf check_asserts_cb@fail6
 3201:49db check_asserts_cb@ok6
 3301:49e5 check_asserts_cb@skip6
 3401:49f0 check_asserts_cb@out6
 3501:4a07 check_asserts_cb@fail7
 3601:4a13 check_asserts_cb@ok7
 3701:4a1d check_asserts_cb@skip7
 3801:4a28 check_asserts_cb@out7
 3901:4b7b clear_oam
 4001:4b85 clear_vram
 4101:4b3a disable_lcd_safe
 4201:4b40 disable_lcd_safe@wait_ly_0
 4301:4b99 memcpy
 4401:4ba2 memset
 4501:4b58 print_hex4
 4601:4b8f print_hex8
 4701:4bb2 print_inline_string
 4801:4b64 print_load_font
 4901:4b70 print_newline
 5001:4a2b print_reg_dump
 5101:4bab print_string
 5201:4ab0 quit
 5301:4ac5 quit@cb_return
 5401:4aca quit@wait_ly_1
 5501:4ad0 quit@wait_ly_2
 5601:4ad6 quit@wait_ly_3
 5701:4adc quit@wait_ly_4
 5801:4ae6 quit@success
 5901:4b0d quit@failure
 6001:4b22 quit@halt
 6101:4b23 quit@halt_execution_0
 6201:4b26 reset_screen
 6301:4b49 serial_send_byte
 6401:4000 font
 6500:ff80 v_regs_save
 6600:ff80 v_regs_save.reg_f
 6700:ff81 v_regs_save.reg_a
 6800:ff82 v_regs_save.reg_c
 6900:ff83 v_regs_save.reg_b
 7000:ff84 v_regs_save.reg_e
 7100:ff85 v_regs_save.reg_d
 7200:ff86 v_regs_save.reg_l
 7300:ff87 v_regs_save.reg_h
 7400:ff88 v_regs_flags
 7500:ff89 v_regs_assert
 7600:ff89 v_regs_assert.reg_f
 7700:ff8a v_regs_assert.reg_a
 7800:ff8b v_regs_assert.reg_c
 7900:ff8c v_regs_assert.reg_b
 8000:ff8d v_regs_assert.reg_e
 8100:ff8e v_regs_assert.reg_d
 8200:ff8f v_regs_assert.reg_l
 8300:ff90 v_regs_assert.reg_h
 8400:0150 main
 8500:0151 main@wait_ly_5
 8600:0157 main@wait_ly_6
 8700:0211 setup_and_wait_mode2
 8800:0211 setup_and_wait_mode2@wait_ly_7
 8900:0234 fail_halt
 9000:023b fail_halt@quit_inline_1
 91
 92[definitions]
 930000023b _sizeof_check_asserts_cb
 940000000a _sizeof_clear_oam
 950000000a _sizeof_clear_vram
 960000000f _sizeof_disable_lcd_safe
 9700000009 _sizeof_memcpy
 9800000009 _sizeof_memset
 990000000c _sizeof_print_hex4
1000000000a _sizeof_print_hex8
10100000006 _sizeof_print_inline_string
1020000000c _sizeof_print_load_font
1030000000b _sizeof_print_newline
10400000085 _sizeof_print_reg_dump
10500000007 _sizeof_print_string
10600000076 _sizeof_quit
10700000014 _sizeof_reset_screen
1080000000f _sizeof_serial_send_byte
109000007f0 _sizeof_font
11000000008 _sizeof_v_regs_save
11100000001 _sizeof_v_regs_save.reg_f
11200000001 _sizeof_v_regs_save.reg_a
11300000001 _sizeof_v_regs_save.reg_c
11400000001 _sizeof_v_regs_save.reg_b
11500000001 _sizeof_v_regs_save.reg_e
11600000001 _sizeof_v_regs_save.reg_d
11700000001 _sizeof_v_regs_save.reg_l
11800000001 _sizeof_v_regs_save.reg_h
11900000001 _sizeof_v_regs_flags
12000000008 _sizeof_v_regs_assert
12100000001 _sizeof_v_regs_assert.reg_f
12200000001 _sizeof_v_regs_assert.reg_a
12300000001 _sizeof_v_regs_assert.reg_c
12400000001 _sizeof_v_regs_assert.reg_b
12500000001 _sizeof_v_regs_assert.reg_e
12600000001 _sizeof_v_regs_assert.reg_d
12700000001 _sizeof_v_regs_assert.reg_l
12800000001 _sizeof_v_regs_assert.reg_h
129000000c1 _sizeof_main
13000000023 _sizeof_setup_and_wait_mode2