src/isa-thumb.c (view raw)
1#include "isa-thumb.h"
2
3#include "isa-inlines.h"
4
5static const ThumbInstruction _thumbTable[0x400];
6
7void ThumbStep(struct ARMCore* cpu) {
8 uint32_t address = cpu->gprs[ARM_PC];
9 cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
10 address -= WORD_SIZE_THUMB;
11 uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
12 ThumbInstruction instruction = _thumbTable[opcode >> 6];
13 instruction(cpu, opcode);
14}
15
16// Instruction definitions
17// Beware pre-processor insanity
18
19#define THUMB_ADDITION_S(M, N, D) \
20 cpu->cpsr.n = ARM_SIGN(D); \
21 cpu->cpsr.z = !(D); \
22 cpu->cpsr.c = ARM_CARRY_FROM(M, N, D); \
23 cpu->cpsr.v = ARM_V_ADDITION(M, N, D);
24
25#define THUMB_SUBTRACTION_S(M, N, D) \
26 cpu->cpsr.n = ARM_SIGN(D); \
27 cpu->cpsr.z = !(D); \
28 cpu->cpsr.c = ARM_BORROW_FROM(M, N, D); \
29 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D);
30
31#define THUMB_NEUTRAL_S(M, N, D) \
32 cpu->cpsr.n = ARM_SIGN(D); \
33 cpu->cpsr.z = !(D);
34
35#define THUMB_ADDITION(D, M, N) \
36 int n = N; \
37 int m = M; \
38 D = M + N; \
39 THUMB_ADDITION_S(m, n, D)
40
41#define APPLY(F, ...) F(__VA_ARGS__)
42
43#define COUNT_1(EMITTER, PREFIX, ...) \
44 EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
45 EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
46
47#define COUNT_2(EMITTER, PREFIX, ...) \
48 COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
49 EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
50 EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
51
52#define COUNT_3(EMITTER, PREFIX, ...) \
53 COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
54 EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
55 EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
56 EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
57 EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
58
59#define COUNT_4(EMITTER, PREFIX, ...) \
60 COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
61 EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
62 EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
63 EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
64 EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
65 EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
66 EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
67 EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
68 EMITTER(PREFIX ## F, 15, __VA_ARGS__)
69
70#define COUNT_5(EMITTER, PREFIX, ...) \
71 COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
72 EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
73 EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
74 EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
75 EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
76 EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
77 EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
78 EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
79 EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
80 EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
81 EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
82 EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
83 EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
84 EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
85 EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
86 EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
87 EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
88
89#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
90 static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
91 BODY; \
92 }
93
94#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
95 DEFINE_INSTRUCTION_THUMB(NAME, \
96 int immediate = IMMEDIATE; \
97 int rd = opcode & 0x0007; \
98 int rm = (opcode >> 3) & 0x0007; \
99 BODY;)
100
101#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
102 COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
103
104DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
105 if (!immediate) { \
106 cpu->gprs[rd] = cpu->gprs[rm]; \
107 } else { \
108 cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
109 cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
110 } \
111 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
112
113DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
114 if (!immediate) { \
115 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
116 cpu->gprs[rd] = 0; \
117 } else { \
118 cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
119 cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
120 } \
121 THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
122
123DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
124
125DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[rm] + immediate * 4))
126DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
127DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
128DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory->store32(cpu->memory, cpu->gprs[rm] + immediate * 4, cpu->gprs[rd]))
129DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
130DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory->store16(cpu->memory, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd]))
131
132#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
133 DEFINE_INSTRUCTION_THUMB(NAME, \
134 int rm = RM; \
135 int rd = opcode & 0x0007; \
136 int rn = (opcode >> 3) & 0x0007; \
137 BODY;)
138
139#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
140 COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
141
142DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
143DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
144
145#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
146 DEFINE_INSTRUCTION_THUMB(NAME, \
147 int immediate = IMMEDIATE; \
148 int rd = opcode & 0x0007; \
149 int rn = (opcode >> 3) & 0x0007; \
150 BODY;)
151
152#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
153 COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
154
155DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
156
157DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
158
159#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
160 DEFINE_INSTRUCTION_THUMB(NAME, \
161 int rd = RD; \
162 int immediate = opcode & 0x00FF; \
163 BODY;)
164
165#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
166 COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
167
168DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
169
170
171DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
172DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
173DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
174
175#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
176 DEFINE_INSTRUCTION_THUMB(NAME, \
177 int rd = opcode & 0x0007; \
178 int rn = (opcode >> 3) & 0x0007; \
179 BODY;)
180
181DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
182DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
183DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
184DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
185DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, \
186 int rs = cpu->gprs[rn] & 0xFF; \
187 if (rs) { \
188 if (rs < 32) { \
189 cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
190 cpu->gprs[rd] >>= rs; \
191 } else { \
192 cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
193 if (cpu->cpsr.c) { \
194 cpu->gprs[rd] = 0xFFFFFFFF; \
195 } else { \
196 cpu->gprs[rd] = 0; \
197 } \
198 } \
199 } \
200 THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
201
202DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
203DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
204DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
205DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
206DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
207DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
208DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
209DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
210DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
211DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
212DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
213
214#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
215 DEFINE_INSTRUCTION_THUMB(NAME, \
216 int rd = opcode & 0x0007 | H1; \
217 int rm = (opcode >> 3) & 0x0007 | H2; \
218 BODY;)
219
220#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
221 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
222 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
223 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
224 DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
225
226DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, cpu->gprs[rd] += cpu->gprs[rm])
227DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rm]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rm], aluOut))
228DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
229
230#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
231 DEFINE_INSTRUCTION_THUMB(NAME, \
232 int rd = RD; \
233 int immediate = (opcode & 0x00FF) << 2; \
234 BODY;)
235
236#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
237 COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
238
239DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_PC] + immediate))
240DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, cpu->gprs[ARM_SP] + immediate))
241DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory->store32(cpu->memory, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd]))
242
243DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
244DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
245
246#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
247 DEFINE_INSTRUCTION_THUMB(NAME, \
248 int rm = RM; \
249 BODY;)
250
251#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
252 COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
253
254DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
255DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
256DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
257DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
258DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
259DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
260DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
261DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
262
263#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
264 DEFINE_INSTRUCTION_THUMB(NAME, \
265 int rn = (opcode >> 8) & 0x000F; \
266 int rs = RS; \
267 int32_t address = ADDRESS; \
268 int m; \
269 int i; \
270 PRE_BODY; \
271 for LOOP { \
272 if (rs & m) { \
273 BODY; \
274 address OP 4; \
275 } \
276 } \
277 POST_BODY; \
278 WRITEBACK;)
279
280#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
281 COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
282
283DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
284 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
285 if (!((1 << rn) & rs)) { \
286 cpu->gprs[rn] = address; \
287 })
288
289DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
290 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
291 cpu->gprs[rn] = address)
292
293#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
294 DEFINE_INSTRUCTION_THUMB(B ## COND, \
295 if (ARM_COND_ ## COND) { \
296 int8_t immediate = opcode; \
297 cpu->gprs[ARM_PC] += immediate << 1; \
298 THUMB_WRITE_PC; \
299 })
300
301DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
302DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
303DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
304DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
305DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
306DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
307DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
308DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
309DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
310DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
311DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
312DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
313DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
314DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
315
316DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
317DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
318
319DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
320 opcode & 0x00FF, \
321 cpu->gprs[ARM_SP], \
322 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
323 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
324 +=, \
325 , , \
326 cpu->gprs[ARM_SP] = address)
327
328DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
329 opcode & 0x00FF, \
330 cpu->gprs[ARM_SP], \
331 (m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
332 cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
333 +=, \
334 , \
335 cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
336 address += 4;, \
337 cpu->gprs[ARM_SP] = address)
338
339DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
340 opcode & 0x00FF, \
341 cpu->gprs[ARM_SP] - 4, \
342 (m = 0x80, i = 7; m; m >>= 1, --i), \
343 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
344 -=, \
345 , , \
346 cpu->gprs[ARM_SP] = address + 4)
347
348DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
349 opcode & 0x00FF, \
350 cpu->gprs[ARM_SP] - 4, \
351 (m = 0x80, i = 7; m; m >>= 1, --i), \
352 cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
353 -=, \
354 cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
355 address -= 4;, \
356 , \
357 cpu->gprs[ARM_SP] = address + 4)
358
359DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
360DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
361DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
362DEFINE_INSTRUCTION_THUMB(BL1, \
363 int16_t immediate = (opcode & 0x07FF) << 5; \
364 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
365
366DEFINE_INSTRUCTION_THUMB(BL2, \
367 uint16_t immediate = (opcode & 0x07FF) << 1; \
368 uint32_t pc = cpu->gprs[ARM_PC]; \
369 cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
370 cpu->gprs[ARM_LR] = pc - 1; \
371 THUMB_WRITE_PC;)
372
373DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
374DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
375
376#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
377 EMITTER ## NAME
378
379#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
380 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
381 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
382 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
383 DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
384
385#define DUMMY(X, ...) X,
386#define DUMMY_4(...) \
387 DUMMY(__VA_ARGS__) \
388 DUMMY(__VA_ARGS__) \
389 DUMMY(__VA_ARGS__) \
390 DUMMY(__VA_ARGS__)
391
392#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
393 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
394 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
395 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
396 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
397 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
398 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
399 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
400 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
401 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
402 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
403 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
404 DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
405 DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
406 DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
407 DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
408 DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
409 DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
410 DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
411 DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
412 DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
413 DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
414 DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
415 DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
416 DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
417 DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
418 DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
419 DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
420 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
421 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
422 DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
423 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
424 DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
425 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
426 DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
427 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
428 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
429 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
430 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
431 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
432 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
433 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
434 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
435 APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
436 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
437 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
438 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
439 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
440 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
441 APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
442 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
443 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
444 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
445 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
446 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
447 DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
448 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
449 DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
450 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
451 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
452 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
453 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
454 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
455 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
456 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
457 DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
458 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
459 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
460 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
461 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
462 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
463 APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
464 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
465 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
466 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
467 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
468 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
469 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
470 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
471 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
472 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
473 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
474 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
475 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
476 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
477 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
478 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
479 DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
480 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
481 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
482 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
483 DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
484
485static const ThumbInstruction _thumbTable[0x400] = {
486 DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
487};