src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25static int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait);
26
27static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
28static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 7, 7, 9, 9, 13, 13, 9 };
29static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
30static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 1, 1, 0, 5, 5, 9, 9, 17, 17, 9 };
31static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
32static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
33static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
34
35void GBAMemoryInit(struct GBA* gba) {
36 struct ARMCore* cpu = gba->cpu;
37 cpu->memory.load32 = GBALoad32;
38 cpu->memory.load16 = GBALoad16;
39 cpu->memory.load8 = GBALoad8;
40 cpu->memory.loadMultiple = GBALoadMultiple;
41 cpu->memory.store32 = GBAStore32;
42 cpu->memory.store16 = GBAStore16;
43 cpu->memory.store8 = GBAStore8;
44 cpu->memory.storeMultiple = GBAStoreMultiple;
45 cpu->memory.stall = GBAMemoryStall;
46
47 gba->memory.bios = (uint32_t*) hleBios;
48 gba->memory.fullBios = 0;
49 gba->memory.wram = 0;
50 gba->memory.iwram = 0;
51 gba->memory.rom = 0;
52 gba->memory.romSize = 0;
53 gba->memory.hw.p = gba;
54
55 int i;
56 for (i = 0; i < 16; ++i) {
57 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
58 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
59 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
60 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
61 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
62 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
63 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
64 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
65 }
66 for (; i < 256; ++i) {
67 gba->memory.waitstatesNonseq16[i] = 0;
68 gba->memory.waitstatesSeq16[i] = 0;
69 gba->memory.waitstatesNonseq32[i] = 0;
70 gba->memory.waitstatesSeq32[i] = 0;
71 }
72
73 gba->memory.activeRegion = -1;
74 cpu->memory.activeRegion = 0;
75 cpu->memory.activeMask = 0;
76 cpu->memory.setActiveRegion = GBASetActiveRegion;
77 cpu->memory.activeSeqCycles32 = 0;
78 cpu->memory.activeSeqCycles16 = 0;
79 cpu->memory.activeNonseqCycles32 = 0;
80 cpu->memory.activeNonseqCycles16 = 0;
81 gba->memory.biosPrefetch = 0;
82}
83
84void GBAMemoryDeinit(struct GBA* gba) {
85 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
86 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
87 if (gba->memory.rom) {
88 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
89 }
90 GBASavedataDeinit(&gba->memory.savedata);
91}
92
93void GBAMemoryReset(struct GBA* gba) {
94 if (gba->memory.wram) {
95 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
96 }
97 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
98
99 if (gba->memory.iwram) {
100 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
101 }
102 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
103
104 memset(gba->memory.io, 0, sizeof(gba->memory.io));
105 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
106 int i;
107 for (i = 0; i < 4; ++i) {
108 gba->memory.dma[i].count = 0x4000;
109 gba->memory.dma[i].nextEvent = INT_MAX;
110 }
111 gba->memory.dma[3].count = 0x10000;
112 gba->memory.activeDMA = -1;
113 gba->memory.nextDMA = INT_MAX;
114 gba->memory.eventDiff = 0;
115
116 gba->memory.prefetch = false;
117 gba->memory.prefetchCycles = 0;
118 gba->memory.prefetchStalls = 0;
119 gba->memory.lastPrefetchedPc = 0;
120
121 if (!gba->memory.wram || !gba->memory.iwram) {
122 GBAMemoryDeinit(gba);
123 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
124 }
125}
126
127static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
128 struct ARMInstructionInfo info;
129 uint32_t nextAddress = address;
130 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
131 if (cpu->executionMode == MODE_THUMB) {
132 while (true) {
133 uint16_t opcode;
134 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
135 ARMDecodeThumb(opcode, &info);
136 switch (info.branchType) {
137 case ARM_BRANCH_NONE:
138 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
139 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
140 gba->idleDetectionStep = -1;
141 return;
142 }
143 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
144 uint32_t offset = 0;
145 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
146 offset = info.memory.offset.immediate;
147 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
148 int reg = info.memory.offset.reg;
149 if (gba->cachedRegisters[reg]) {
150 gba->idleDetectionStep = -1;
151 return;
152 }
153 offset = gba->cachedRegisters[reg];
154 }
155 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
156 loadAddress -= offset;
157 } else {
158 loadAddress += offset;
159 }
160 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
161 gba->idleDetectionStep = -1;
162 return;
163 }
164 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
165 gba->taintedRegisters[info.op1.reg] = true;
166 } else {
167 switch (info.memory.width) {
168 case 1:
169 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
170 break;
171 case 2:
172 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
173 break;
174 case 4:
175 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
176 break;
177 }
178 }
179 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
180 gba->taintedRegisters[info.op1.reg] = true;
181 }
182 nextAddress += WORD_SIZE_THUMB;
183 break;
184 case ARM_BRANCH:
185 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
186 gba->idleLoop = address;
187 gba->idleOptimization = IDLE_LOOP_REMOVE;
188 }
189 gba->idleDetectionStep = -1;
190 return;
191 default:
192 gba->idleDetectionStep = -1;
193 return;
194 }
195 }
196 } else {
197 gba->idleDetectionStep = -1;
198 }
199}
200
201static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
202 struct GBA* gba = (struct GBA*) cpu->master;
203 struct GBAMemory* memory = &gba->memory;
204
205 int newRegion = address >> BASE_OFFSET;
206 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
207 if (address == gba->idleLoop) {
208 if (gba->haltPending) {
209 gba->haltPending = false;
210 GBAHalt(gba);
211 } else {
212 gba->haltPending = true;
213 }
214 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
215 if (address == gba->lastJump) {
216 switch (gba->idleDetectionStep) {
217 case 0:
218 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
219 ++gba->idleDetectionStep;
220 break;
221 case 1:
222 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
223 gba->idleDetectionStep = -1;
224 ++gba->idleDetectionFailures;
225 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
226 gba->idleOptimization = IDLE_LOOP_IGNORE;
227 }
228 break;
229 }
230 _analyzeForIdleLoop(gba, cpu, address);
231 break;
232 }
233 } else {
234 gba->idleDetectionStep = 0;
235 }
236 }
237 }
238
239 gba->lastJump = address;
240 GBAMemoryInvalidatePrefetch(gba);
241 memory->lastPrefetchedPc = 0;
242 memory->lastPrefetchedLoads = 0;
243 if (newRegion == memory->activeRegion && (newRegion < REGION_CART0 || (address & (SIZE_CART0 - 1)) < memory->romSize)) {
244 return;
245 }
246
247 if (memory->activeRegion == REGION_BIOS) {
248 memory->biosPrefetch = cpu->prefetch[1];
249 }
250 memory->activeRegion = newRegion;
251 switch (newRegion) {
252 case REGION_BIOS:
253 cpu->memory.activeRegion = memory->bios;
254 cpu->memory.activeMask = SIZE_BIOS - 1;
255 break;
256 case REGION_WORKING_RAM:
257 cpu->memory.activeRegion = memory->wram;
258 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
259 break;
260 case REGION_WORKING_IRAM:
261 cpu->memory.activeRegion = memory->iwram;
262 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
263 break;
264 case REGION_VRAM:
265 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
266 cpu->memory.activeMask = 0x0000FFFF;
267 break;
268 case REGION_CART0:
269 case REGION_CART0_EX:
270 case REGION_CART1:
271 case REGION_CART1_EX:
272 case REGION_CART2:
273 case REGION_CART2_EX:
274 cpu->memory.activeRegion = memory->rom;
275 cpu->memory.activeMask = SIZE_CART0 - 1;
276 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
277 break;
278 }
279 // Fall through
280 default:
281 memory->activeRegion = -1;
282 cpu->memory.activeRegion = _deadbeef;
283 cpu->memory.activeMask = 0;
284 if (!gba->yankedRomSize) {
285 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
286 }
287 return;
288 }
289 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
290 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
291 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
292 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
293}
294
295#define LOAD_BAD \
296 if (gba->performingDMA) { \
297 value = gba->bus; \
298 } else { \
299 value = cpu->prefetch[1]; \
300 if (cpu->executionMode == MODE_THUMB) { \
301 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
302 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
303 case REGION_BIOS: \
304 case REGION_OAM: \
305 /* This isn't right half the time, but we don't have $+6 handy */ \
306 value <<= 16; \
307 value |= cpu->prefetch[0]; \
308 break; \
309 case REGION_WORKING_IRAM: \
310 /* This doesn't handle prefetch clobbering */ \
311 if (cpu->gprs[ARM_PC] & 2) { \
312 value |= cpu->prefetch[0] << 16; \
313 } else { \
314 value <<= 16; \
315 value |= cpu->prefetch[0]; \
316 } \
317 default: \
318 value |= value << 16; \
319 } \
320 } \
321 }
322
323#define LOAD_BIOS \
324 if (address < SIZE_BIOS) { \
325 if (memory->activeRegion == REGION_BIOS) { \
326 LOAD_32(value, address, memory->bios); \
327 } else { \
328 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
329 value = memory->biosPrefetch; \
330 } \
331 } else { \
332 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
333 LOAD_BAD; \
334 }
335
336#define LOAD_WORKING_RAM \
337 LOAD_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
338 wait += waitstatesRegion[REGION_WORKING_RAM];
339
340#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
341#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
342
343#define LOAD_PALETTE_RAM \
344 LOAD_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
345 wait += waitstatesRegion[REGION_PALETTE_RAM];
346
347#define LOAD_VRAM \
348 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
349 LOAD_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
350 } else { \
351 LOAD_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
352 } \
353 wait += waitstatesRegion[REGION_VRAM];
354
355#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
356
357#define LOAD_CART \
358 wait += waitstatesRegion[address >> BASE_OFFSET]; \
359 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
360 LOAD_32(value, address & (SIZE_CART0 - 4), memory->rom); \
361 } else { \
362 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
363 value = (address >> 1) & 0xFFFF; \
364 value |= ((address + 2) >> 1) << 16; \
365 }
366
367#define LOAD_SRAM \
368 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
369 value = GBALoad8(cpu, address, 0); \
370 value |= value << 8; \
371 value |= value << 16;
372
373uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
374 struct GBA* gba = (struct GBA*) cpu->master;
375 struct GBAMemory* memory = &gba->memory;
376 uint32_t value = 0;
377 int wait = 0;
378 char* waitstatesRegion = memory->waitstatesNonseq32;
379
380 switch (address >> BASE_OFFSET) {
381 case REGION_BIOS:
382 LOAD_BIOS;
383 break;
384 case REGION_WORKING_RAM:
385 LOAD_WORKING_RAM;
386 break;
387 case REGION_WORKING_IRAM:
388 LOAD_WORKING_IRAM;
389 break;
390 case REGION_IO:
391 LOAD_IO;
392 break;
393 case REGION_PALETTE_RAM:
394 LOAD_PALETTE_RAM;
395 break;
396 case REGION_VRAM:
397 LOAD_VRAM;
398 break;
399 case REGION_OAM:
400 LOAD_OAM;
401 break;
402 case REGION_CART0:
403 case REGION_CART0_EX:
404 case REGION_CART1:
405 case REGION_CART1_EX:
406 case REGION_CART2:
407 case REGION_CART2_EX:
408 LOAD_CART;
409 break;
410 case REGION_CART_SRAM:
411 case REGION_CART_SRAM_MIRROR:
412 LOAD_SRAM;
413 break;
414 default:
415 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
416 LOAD_BAD;
417 break;
418 }
419
420 if (cycleCounter) {
421 wait += 2;
422 if (address >> BASE_OFFSET < REGION_CART0) {
423 wait = GBAMemoryStall(cpu, wait);
424 }
425 *cycleCounter += wait;
426 }
427 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
428 int rotate = (address & 3) << 3;
429 return ROR(value, rotate);
430}
431
432uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
433 struct GBA* gba = (struct GBA*) cpu->master;
434 struct GBAMemory* memory = &gba->memory;
435 uint32_t value = 0;
436 int wait = 0;
437
438 switch (address >> BASE_OFFSET) {
439 case REGION_BIOS:
440 if (address < SIZE_BIOS) {
441 if (memory->activeRegion == REGION_BIOS) {
442 LOAD_16(value, address, memory->bios);
443 } else {
444 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
445 LOAD_16(value, address & 2, &memory->biosPrefetch);
446 }
447 } else {
448 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
449 LOAD_BAD;
450 uint32_t v2 = value;
451 LOAD_16(value, address & 2, &v2);
452 }
453 break;
454 case REGION_WORKING_RAM:
455 LOAD_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
456 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
457 break;
458 case REGION_WORKING_IRAM:
459 LOAD_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
460 break;
461 case REGION_IO:
462 value = GBAIORead(gba, address & (SIZE_IO - 2));
463 break;
464 case REGION_PALETTE_RAM:
465 LOAD_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
466 break;
467 case REGION_VRAM:
468 if ((address & 0x0001FFFF) < SIZE_VRAM) {
469 LOAD_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
470 } else {
471 LOAD_16(value, address & 0x00017FFE, gba->video.renderer->vram);
472 }
473 break;
474 case REGION_OAM:
475 LOAD_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
476 break;
477 case REGION_CART0:
478 case REGION_CART0_EX:
479 case REGION_CART1:
480 case REGION_CART1_EX:
481 case REGION_CART2:
482 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
483 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
484 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
485 } else {
486 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
487 value = (address >> 1) & 0xFFFF;
488 }
489 break;
490 case REGION_CART2_EX:
491 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
492 if (memory->savedata.type == SAVEDATA_EEPROM) {
493 value = GBASavedataReadEEPROM(&memory->savedata);
494 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
495 LOAD_16(value, address & (SIZE_CART0 - 2), memory->rom);
496 } else {
497 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
498 value = (address >> 1) & 0xFFFF;
499 }
500 break;
501 case REGION_CART_SRAM:
502 case REGION_CART_SRAM_MIRROR:
503 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
504 value = GBALoad8(cpu, address, 0);
505 value |= value << 8;
506 break;
507 default:
508 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
509 LOAD_BAD;
510 uint32_t v2 = value;
511 LOAD_16(value, address & 2, &v2);
512 break;
513 }
514
515 if (cycleCounter) {
516 wait += 2;
517 if (address >> BASE_OFFSET < REGION_CART0) {
518 wait = GBAMemoryStall(cpu, wait);
519 }
520 *cycleCounter += wait;
521 }
522 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
523 int rotate = (address & 1) << 3;
524 return ROR(value, rotate);
525}
526
527uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
528 struct GBA* gba = (struct GBA*) cpu->master;
529 struct GBAMemory* memory = &gba->memory;
530 uint32_t value = 0;
531 int wait = 0;
532
533 switch (address >> BASE_OFFSET) {
534 case REGION_BIOS:
535 if (address < SIZE_BIOS) {
536 if (memory->activeRegion == REGION_BIOS) {
537 value = ((uint8_t*) memory->bios)[address];
538 } else {
539 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
540 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
541 }
542 } else {
543 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
544 LOAD_BAD;
545 value = ((uint8_t*) &value)[address & 3];
546 }
547 break;
548 case REGION_WORKING_RAM:
549 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
550 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
551 break;
552 case REGION_WORKING_IRAM:
553 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
554 break;
555 case REGION_IO:
556 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
557 break;
558 case REGION_PALETTE_RAM:
559 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
560 break;
561 case REGION_VRAM:
562 if ((address & 0x0001FFFF) < SIZE_VRAM) {
563 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
564 } else {
565 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
566 }
567 break;
568 case REGION_OAM:
569 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
570 break;
571 case REGION_CART0:
572 case REGION_CART0_EX:
573 case REGION_CART1:
574 case REGION_CART1_EX:
575 case REGION_CART2:
576 case REGION_CART2_EX:
577 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
578 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
579 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
580 } else {
581 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
582 value = (address >> 1) & 0xFF;
583 }
584 break;
585 case REGION_CART_SRAM:
586 case REGION_CART_SRAM_MIRROR:
587 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
588 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
589 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
590 GBASavedataInitSRAM(&memory->savedata);
591 }
592 if (memory->savedata.type == SAVEDATA_SRAM) {
593 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
594 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
595 value = GBASavedataReadFlash(&memory->savedata, address);
596 } else if (memory->hw.devices & HW_TILT) {
597 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
598 } else {
599 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
600 value = 0xFF;
601 }
602 value &= 0xFF;
603 break;
604 default:
605 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
606 LOAD_BAD;
607 value = ((uint8_t*) &value)[address & 3];
608 break;
609 }
610
611 if (cycleCounter) {
612 wait += 2;
613 if (address >> BASE_OFFSET < REGION_CART0) {
614 wait = GBAMemoryStall(cpu, wait);
615 }
616 *cycleCounter += wait;
617 }
618 return value;
619}
620
621#define STORE_WORKING_RAM \
622 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram); \
623 wait += waitstatesRegion[REGION_WORKING_RAM];
624
625#define STORE_WORKING_IRAM \
626 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
627
628#define STORE_IO \
629 GBAIOWrite32(gba, address & (SIZE_IO - 4), value);
630
631#define STORE_PALETTE_RAM \
632 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette); \
633 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16); \
634 wait += waitstatesRegion[REGION_PALETTE_RAM]; \
635 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
636
637#define STORE_VRAM \
638 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
639 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram); \
640 } else { \
641 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram); \
642 } \
643 wait += waitstatesRegion[REGION_VRAM];
644
645#define STORE_OAM \
646 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw); \
647 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
648 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
649
650#define STORE_CART \
651 wait += waitstatesRegion[address >> BASE_OFFSET]; \
652 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
653
654#define STORE_SRAM \
655 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
656
657#define STORE_BAD \
658 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
659
660void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
661 struct GBA* gba = (struct GBA*) cpu->master;
662 struct GBAMemory* memory = &gba->memory;
663 int wait = 0;
664 char* waitstatesRegion = memory->waitstatesNonseq32;
665
666 switch (address >> BASE_OFFSET) {
667 case REGION_WORKING_RAM:
668 STORE_WORKING_RAM;
669 break;
670 case REGION_WORKING_IRAM:
671 STORE_WORKING_IRAM
672 break;
673 case REGION_IO:
674 STORE_IO;
675 break;
676 case REGION_PALETTE_RAM:
677 STORE_PALETTE_RAM;
678 break;
679 case REGION_VRAM:
680 STORE_VRAM;
681 break;
682 case REGION_OAM:
683 STORE_OAM;
684 break;
685 case REGION_CART0:
686 case REGION_CART0_EX:
687 case REGION_CART1:
688 case REGION_CART1_EX:
689 case REGION_CART2:
690 case REGION_CART2_EX:
691 STORE_CART;
692 break;
693 case REGION_CART_SRAM:
694 case REGION_CART_SRAM_MIRROR:
695 STORE_SRAM;
696 break;
697 default:
698 STORE_BAD;
699 break;
700 }
701
702 if (cycleCounter) {
703 ++wait;
704 if (address >> BASE_OFFSET < REGION_CART0) {
705 wait = GBAMemoryStall(cpu, wait);
706 }
707 *cycleCounter += wait;
708 }
709}
710
711void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
712 struct GBA* gba = (struct GBA*) cpu->master;
713 struct GBAMemory* memory = &gba->memory;
714 int wait = 0;
715
716 switch (address >> BASE_OFFSET) {
717 case REGION_WORKING_RAM:
718 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
719 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
720 break;
721 case REGION_WORKING_IRAM:
722 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
723 break;
724 case REGION_IO:
725 GBAIOWrite(gba, address & (SIZE_IO - 2), value);
726 break;
727 case REGION_PALETTE_RAM:
728 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
729 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
730 break;
731 case REGION_VRAM:
732 if ((address & 0x0001FFFF) < SIZE_VRAM) {
733 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
734 } else {
735 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
736 }
737 break;
738 case REGION_OAM:
739 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
740 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
741 break;
742 case REGION_CART0:
743 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFE)) {
744 uint32_t reg = address & 0xFFFFFE;
745 GBAHardwareGPIOWrite(&memory->hw, reg, value);
746 } else {
747 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
748 }
749 break;
750 case REGION_CART2_EX:
751 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
752 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
753 GBASavedataInitEEPROM(&memory->savedata);
754 }
755 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
756 break;
757 case REGION_CART_SRAM:
758 case REGION_CART_SRAM_MIRROR:
759 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
760 break;
761 default:
762 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
763 break;
764 }
765
766 if (cycleCounter) {
767 ++wait;
768 if (address >> BASE_OFFSET < REGION_CART0) {
769 wait = GBAMemoryStall(cpu, wait);
770 }
771 *cycleCounter += wait;
772 }
773}
774
775void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
776 struct GBA* gba = (struct GBA*) cpu->master;
777 struct GBAMemory* memory = &gba->memory;
778 int wait = 0;
779
780 switch (address >> BASE_OFFSET) {
781 case REGION_WORKING_RAM:
782 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
783 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
784 break;
785 case REGION_WORKING_IRAM:
786 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
787 break;
788 case REGION_IO:
789 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
790 break;
791 case REGION_PALETTE_RAM:
792 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
793 break;
794 case REGION_VRAM:
795 if (address >= 0x06018000) {
796 // TODO: check BG mode
797 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
798 break;
799 }
800 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
801 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
802 break;
803 case REGION_OAM:
804 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
805 break;
806 case REGION_CART0:
807 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
808 break;
809 case REGION_CART_SRAM:
810 case REGION_CART_SRAM_MIRROR:
811 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
812 if (address == SAVEDATA_FLASH_BASE) {
813 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
814 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
815 } else {
816 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
817 GBASavedataInitSRAM(&memory->savedata);
818 }
819 }
820 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
821 GBASavedataWriteFlash(&memory->savedata, address, value);
822 } else if (memory->savedata.type == SAVEDATA_SRAM) {
823 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
824 } else if (memory->hw.devices & HW_TILT) {
825 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
826 } else {
827 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
828 }
829 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
830 break;
831 default:
832 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
833 break;
834 }
835
836 if (cycleCounter) {
837 ++wait;
838 if (address >> BASE_OFFSET < REGION_CART0) {
839 wait = GBAMemoryStall(cpu, wait);
840 }
841 *cycleCounter += wait;
842 }
843}
844
845void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
846 struct GBA* gba = (struct GBA*) cpu->master;
847 struct GBAMemory* memory = &gba->memory;
848 int32_t oldValue = -1;
849
850 switch (address >> BASE_OFFSET) {
851 case REGION_WORKING_RAM:
852 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 4), memory->wram);
853 STORE_32(value, address & (SIZE_WORKING_RAM - 4), memory->wram);
854 break;
855 case REGION_WORKING_IRAM:
856 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
857 STORE_32(value, address & (SIZE_WORKING_IRAM - 4), memory->iwram);
858 break;
859 case REGION_IO:
860 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
861 break;
862 case REGION_PALETTE_RAM:
863 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
864 STORE_32(value, address & (SIZE_PALETTE_RAM - 4), gba->video.palette);
865 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 4), value);
866 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 4)) + 2, value >> 16);
867 break;
868 case REGION_VRAM:
869 if ((address & 0x0001FFFF) < SIZE_VRAM) {
870 LOAD_32(oldValue, address & 0x0001FFFC, gba->video.renderer->vram);
871 STORE_32(value, address & 0x0001FFFC, gba->video.renderer->vram);
872 } else {
873 LOAD_32(oldValue, address & 0x00017FFC, gba->video.renderer->vram);
874 STORE_32(value, address & 0x00017FFC, gba->video.renderer->vram);
875 }
876 break;
877 case REGION_OAM:
878 LOAD_32(oldValue, address & (SIZE_OAM - 4), gba->video.oam.raw);
879 STORE_32(value, address & (SIZE_OAM - 4), gba->video.oam.raw);
880 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1);
881 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) + 2) >> 1);
882 break;
883 case REGION_CART0:
884 case REGION_CART0_EX:
885 case REGION_CART1:
886 case REGION_CART1_EX:
887 case REGION_CART2:
888 case REGION_CART2_EX:
889 _pristineCow(gba);
890 if ((address & (SIZE_CART0 - 4)) >= gba->memory.romSize) {
891 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
892 }
893 LOAD_32(oldValue, address & (SIZE_CART0 - 4), gba->memory.rom);
894 STORE_32(value, address & (SIZE_CART0 - 4), gba->memory.rom);
895 break;
896 case REGION_CART_SRAM:
897 case REGION_CART_SRAM_MIRROR:
898 if (memory->savedata.type == SAVEDATA_SRAM) {
899 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
900 STORE_32(value, address & (SIZE_CART_SRAM - 4), memory->savedata.data);
901 } else {
902 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
903 }
904 break;
905 default:
906 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
907 break;
908 }
909 if (old) {
910 *old = oldValue;
911 }
912}
913
914void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
915 struct GBA* gba = (struct GBA*) cpu->master;
916 struct GBAMemory* memory = &gba->memory;
917 int16_t oldValue = -1;
918
919 switch (address >> BASE_OFFSET) {
920 case REGION_WORKING_RAM:
921 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 2), memory->wram);
922 STORE_16(value, address & (SIZE_WORKING_RAM - 2), memory->wram);
923 break;
924 case REGION_WORKING_IRAM:
925 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
926 STORE_16(value, address & (SIZE_WORKING_IRAM - 2), memory->iwram);
927 break;
928 case REGION_IO:
929 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
930 break;
931 case REGION_PALETTE_RAM:
932 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
933 STORE_16(value, address & (SIZE_PALETTE_RAM - 2), gba->video.palette);
934 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 2), value);
935 break;
936 case REGION_VRAM:
937 if ((address & 0x0001FFFF) < SIZE_VRAM) {
938 LOAD_16(oldValue, address & 0x0001FFFE, gba->video.renderer->vram);
939 STORE_16(value, address & 0x0001FFFE, gba->video.renderer->vram);
940 } else {
941 LOAD_16(oldValue, address & 0x00017FFE, gba->video.renderer->vram);
942 STORE_16(value, address & 0x00017FFE, gba->video.renderer->vram);
943 }
944 break;
945 case REGION_OAM:
946 LOAD_16(oldValue, address & (SIZE_OAM - 2), gba->video.oam.raw);
947 STORE_16(value, address & (SIZE_OAM - 2), gba->video.oam.raw);
948 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 2)) >> 1);
949 break;
950 case REGION_CART0:
951 case REGION_CART0_EX:
952 case REGION_CART1:
953 case REGION_CART1_EX:
954 case REGION_CART2:
955 case REGION_CART2_EX:
956 _pristineCow(gba);
957 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
958 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
959 }
960 LOAD_16(oldValue, address & (SIZE_CART0 - 2), gba->memory.rom);
961 STORE_16(value, address & (SIZE_CART0 - 2), gba->memory.rom);
962 break;
963 case REGION_CART_SRAM:
964 case REGION_CART_SRAM_MIRROR:
965 if (memory->savedata.type == SAVEDATA_SRAM) {
966 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
967 STORE_16(value, address & (SIZE_CART_SRAM - 2), memory->savedata.data);
968 } else {
969 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
970 }
971 break;
972 default:
973 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
974 break;
975 }
976 if (old) {
977 *old = oldValue;
978 }
979}
980
981void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
982 struct GBA* gba = (struct GBA*) cpu->master;
983 struct GBAMemory* memory = &gba->memory;
984 int8_t oldValue = -1;
985
986 switch (address >> BASE_OFFSET) {
987 case REGION_WORKING_RAM:
988 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
989 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
990 break;
991 case REGION_WORKING_IRAM:
992 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
993 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
994 break;
995 case REGION_IO:
996 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
997 break;
998 case REGION_PALETTE_RAM:
999 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1000 break;
1001 case REGION_VRAM:
1002 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1003 break;
1004 case REGION_OAM:
1005 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
1006 break;
1007 case REGION_CART0:
1008 case REGION_CART0_EX:
1009 case REGION_CART1:
1010 case REGION_CART1_EX:
1011 case REGION_CART2:
1012 case REGION_CART2_EX:
1013 _pristineCow(gba);
1014 if ((address & (SIZE_CART0 - 1)) >= gba->memory.romSize) {
1015 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
1016 }
1017 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
1018 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
1019 break;
1020 case REGION_CART_SRAM:
1021 case REGION_CART_SRAM_MIRROR:
1022 if (memory->savedata.type == SAVEDATA_SRAM) {
1023 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
1024 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
1025 } else {
1026 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
1027 }
1028 break;
1029 default:
1030 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
1031 break;
1032 }
1033 if (old) {
1034 *old = oldValue;
1035 }
1036}
1037
1038#define LDM_LOOP(LDM) \
1039 for (i = 0; i < 16; i += 4) { \
1040 if (UNLIKELY(mask & (1 << i))) { \
1041 LDM; \
1042 waitstatesRegion = memory->waitstatesSeq32; \
1043 cpu->gprs[i] = value; \
1044 ++wait; \
1045 address += 4; \
1046 } \
1047 if (UNLIKELY(mask & (2 << i))) { \
1048 LDM; \
1049 waitstatesRegion = memory->waitstatesSeq32; \
1050 cpu->gprs[i + 1] = value; \
1051 ++wait; \
1052 address += 4; \
1053 } \
1054 if (UNLIKELY(mask & (4 << i))) { \
1055 LDM; \
1056 waitstatesRegion = memory->waitstatesSeq32; \
1057 cpu->gprs[i + 2] = value; \
1058 ++wait; \
1059 address += 4; \
1060 } \
1061 if (UNLIKELY(mask & (8 << i))) { \
1062 LDM; \
1063 waitstatesRegion = memory->waitstatesSeq32; \
1064 cpu->gprs[i + 3] = value; \
1065 ++wait; \
1066 address += 4; \
1067 } \
1068 }
1069
1070uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1071 struct GBA* gba = (struct GBA*) cpu->master;
1072 struct GBAMemory* memory = &gba->memory;
1073 uint32_t value;
1074 int wait = 0;
1075 char* waitstatesRegion = memory->waitstatesNonseq32;
1076
1077 int i;
1078 int offset = 4;
1079 int popcount = 0;
1080 if (direction & LSM_D) {
1081 offset = -4;
1082 popcount = _popcount32(mask);
1083 address -= (popcount << 2) - 4;
1084 }
1085
1086 if (direction & LSM_B) {
1087 address += offset;
1088 }
1089
1090 uint32_t addressMisalign = address & 0x3;
1091 address &= 0xFFFFFFFC;
1092
1093 switch (address >> BASE_OFFSET) {
1094 case REGION_BIOS:
1095 LDM_LOOP(LOAD_BIOS);
1096 break;
1097 case REGION_WORKING_RAM:
1098 LDM_LOOP(LOAD_WORKING_RAM);
1099 break;
1100 case REGION_WORKING_IRAM:
1101 LDM_LOOP(LOAD_WORKING_IRAM);
1102 break;
1103 case REGION_IO:
1104 LDM_LOOP(LOAD_IO);
1105 break;
1106 case REGION_PALETTE_RAM:
1107 LDM_LOOP(LOAD_PALETTE_RAM);
1108 break;
1109 case REGION_VRAM:
1110 LDM_LOOP(LOAD_VRAM);
1111 break;
1112 case REGION_OAM:
1113 LDM_LOOP(LOAD_OAM);
1114 break;
1115 case REGION_CART0:
1116 case REGION_CART0_EX:
1117 case REGION_CART1:
1118 case REGION_CART1_EX:
1119 case REGION_CART2:
1120 case REGION_CART2_EX:
1121 LDM_LOOP(LOAD_CART);
1122 break;
1123 case REGION_CART_SRAM:
1124 case REGION_CART_SRAM_MIRROR:
1125 LDM_LOOP(LOAD_SRAM);
1126 break;
1127 default:
1128 LDM_LOOP(LOAD_BAD);
1129 break;
1130 }
1131
1132 if (cycleCounter) {
1133 ++wait;
1134 if (address >> BASE_OFFSET < REGION_CART0) {
1135 wait = GBAMemoryStall(cpu, wait);
1136 }
1137 *cycleCounter += wait;
1138 }
1139
1140 if (direction & LSM_B) {
1141 address -= offset;
1142 }
1143
1144 if (direction & LSM_D) {
1145 address -= (popcount << 2) + 4;
1146 }
1147
1148 return address | addressMisalign;
1149}
1150
1151#define STM_LOOP(STM) \
1152 for (i = 0; i < 16; i += 4) { \
1153 if (UNLIKELY(mask & (1 << i))) { \
1154 value = cpu->gprs[i]; \
1155 STM; \
1156 waitstatesRegion = memory->waitstatesSeq32; \
1157 ++wait; \
1158 address += 4; \
1159 } \
1160 if (UNLIKELY(mask & (2 << i))) { \
1161 value = cpu->gprs[i + 1]; \
1162 STM; \
1163 waitstatesRegion = memory->waitstatesSeq32; \
1164 ++wait; \
1165 address += 4; \
1166 } \
1167 if (UNLIKELY(mask & (4 << i))) { \
1168 value = cpu->gprs[i + 2]; \
1169 STM; \
1170 waitstatesRegion = memory->waitstatesSeq32; \
1171 ++wait; \
1172 address += 4; \
1173 } \
1174 if (UNLIKELY(mask & (8 << i))) { \
1175 value = cpu->gprs[i + 3]; \
1176 STM; \
1177 waitstatesRegion = memory->waitstatesSeq32; \
1178 ++wait; \
1179 address += 4; \
1180 } \
1181 }
1182
1183uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1184 struct GBA* gba = (struct GBA*) cpu->master;
1185 struct GBAMemory* memory = &gba->memory;
1186 uint32_t value;
1187 int wait = 0;
1188 char* waitstatesRegion = memory->waitstatesNonseq32;
1189
1190 int i;
1191 int offset = 4;
1192 int popcount = 0;
1193 if (direction & LSM_D) {
1194 offset = -4;
1195 popcount = _popcount32(mask);
1196 address -= (popcount << 2) - 4;
1197 }
1198
1199 if (direction & LSM_B) {
1200 address += offset;
1201 }
1202
1203 uint32_t addressMisalign = address & 0x3;
1204 address &= 0xFFFFFFFC;
1205
1206 switch (address >> BASE_OFFSET) {
1207 case REGION_WORKING_RAM:
1208 STM_LOOP(STORE_WORKING_RAM);
1209 break;
1210 case REGION_WORKING_IRAM:
1211 STM_LOOP(STORE_WORKING_IRAM);
1212 break;
1213 case REGION_IO:
1214 STM_LOOP(STORE_IO);
1215 break;
1216 case REGION_PALETTE_RAM:
1217 STM_LOOP(STORE_PALETTE_RAM);
1218 break;
1219 case REGION_VRAM:
1220 STM_LOOP(STORE_VRAM);
1221 break;
1222 case REGION_OAM:
1223 STM_LOOP(STORE_OAM);
1224 break;
1225 case REGION_CART0:
1226 case REGION_CART0_EX:
1227 case REGION_CART1:
1228 case REGION_CART1_EX:
1229 case REGION_CART2:
1230 case REGION_CART2_EX:
1231 STM_LOOP(STORE_CART);
1232 break;
1233 case REGION_CART_SRAM:
1234 case REGION_CART_SRAM_MIRROR:
1235 STM_LOOP(STORE_SRAM);
1236 break;
1237 default:
1238 STM_LOOP(STORE_BAD);
1239 break;
1240 }
1241
1242 if (cycleCounter) {
1243 if (address >> BASE_OFFSET < REGION_CART0) {
1244 wait = GBAMemoryStall(cpu, wait);
1245 }
1246 *cycleCounter += wait;
1247 }
1248
1249 if (direction & LSM_B) {
1250 address -= offset;
1251 }
1252
1253 if (direction & LSM_D) {
1254 address -= (popcount << 2) + 4;
1255 }
1256
1257 return address | addressMisalign;
1258}
1259
1260void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1261 struct GBAMemory* memory = &gba->memory;
1262 struct ARMCore* cpu = gba->cpu;
1263 int sram = parameters & 0x0003;
1264 int ws0 = (parameters & 0x000C) >> 2;
1265 int ws0seq = (parameters & 0x0010) >> 4;
1266 int ws1 = (parameters & 0x0060) >> 5;
1267 int ws1seq = (parameters & 0x0080) >> 7;
1268 int ws2 = (parameters & 0x0300) >> 8;
1269 int ws2seq = (parameters & 0x0400) >> 10;
1270 int prefetch = parameters & 0x4000;
1271
1272 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1273 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1274 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1275 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1276
1277 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1278 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1279 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1280
1281 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1282 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1283 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1284
1285 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1286 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1287 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1288
1289 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1290 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1291 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1292
1293 memory->prefetch = prefetch;
1294
1295 cpu->memory.activeSeqCycles32 = memory->waitstatesSeq32[memory->activeRegion];
1296 cpu->memory.activeSeqCycles16 = memory->waitstatesSeq16[memory->activeRegion];
1297
1298 cpu->memory.activeNonseqCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1299 cpu->memory.activeNonseqCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1300}
1301
1302void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1303 struct GBAMemory* memory = &gba->memory;
1304 memory->dma[dma].source = address & 0x0FFFFFFE;
1305}
1306
1307void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1308 struct GBAMemory* memory = &gba->memory;
1309 memory->dma[dma].dest = address & 0x0FFFFFFE;
1310}
1311
1312void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1313 struct GBAMemory* memory = &gba->memory;
1314 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1315}
1316
1317uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1318 struct GBAMemory* memory = &gba->memory;
1319 struct GBADMA* currentDma = &memory->dma[dma];
1320 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1321 currentDma->reg = control;
1322
1323 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1324 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1325 }
1326
1327 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1328 currentDma->nextSource = currentDma->source;
1329 currentDma->nextDest = currentDma->dest;
1330 currentDma->nextCount = currentDma->count;
1331 GBAMemoryScheduleDMA(gba, dma, currentDma);
1332 }
1333 // If the DMA has already occurred, this value might have changed since the function started
1334 return currentDma->reg;
1335};
1336
1337void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1338 struct ARMCore* cpu = gba->cpu;
1339 switch (GBADMARegisterGetTiming(info->reg)) {
1340 case DMA_TIMING_NOW:
1341 info->nextEvent = cpu->cycles;
1342 GBAMemoryUpdateDMAs(gba, 0);
1343 break;
1344 case DMA_TIMING_HBLANK:
1345 // Handled implicitly
1346 info->nextEvent = INT_MAX;
1347 break;
1348 case DMA_TIMING_VBLANK:
1349 // Handled implicitly
1350 info->nextEvent = INT_MAX;
1351 break;
1352 case DMA_TIMING_CUSTOM:
1353 info->nextEvent = INT_MAX;
1354 switch (number) {
1355 case 0:
1356 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1357 break;
1358 case 1:
1359 case 2:
1360 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1361 break;
1362 case 3:
1363 // GBAVideoScheduleVCaptureDma(dma, info);
1364 break;
1365 }
1366 }
1367}
1368
1369void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1370 struct GBAMemory* memory = &gba->memory;
1371 struct GBADMA* dma;
1372 int i;
1373 for (i = 0; i < 4; ++i) {
1374 dma = &memory->dma[i];
1375 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1376 dma->nextEvent = cycles;
1377 }
1378 }
1379 GBAMemoryUpdateDMAs(gba, 0);
1380}
1381
1382void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1383 struct GBAMemory* memory = &gba->memory;
1384 struct GBADMA* dma;
1385 int i;
1386 for (i = 0; i < 4; ++i) {
1387 dma = &memory->dma[i];
1388 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1389 dma->nextEvent = cycles;
1390 }
1391 }
1392 GBAMemoryUpdateDMAs(gba, 0);
1393}
1394
1395int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1396 struct GBAMemory* memory = &gba->memory;
1397 if (memory->nextDMA == INT_MAX) {
1398 return INT_MAX;
1399 }
1400 memory->nextDMA -= cycles;
1401 memory->eventDiff += cycles;
1402 if (memory->nextDMA <= 0) {
1403 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1404 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1405 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1406 memory->eventDiff = 0;
1407 }
1408 return memory->nextDMA;
1409}
1410
1411void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1412 int i;
1413 struct GBAMemory* memory = &gba->memory;
1414 struct ARMCore* cpu = gba->cpu;
1415 memory->activeDMA = -1;
1416 memory->nextDMA = INT_MAX;
1417 for (i = 3; i >= 0; --i) {
1418 struct GBADMA* dma = &memory->dma[i];
1419 if (dma->nextEvent != INT_MAX) {
1420 dma->nextEvent -= cycles;
1421 if (GBADMARegisterIsEnable(dma->reg)) {
1422 memory->activeDMA = i;
1423 memory->nextDMA = dma->nextEvent;
1424 }
1425 }
1426 }
1427 if (memory->nextDMA < cpu->nextEvent) {
1428 cpu->nextEvent = memory->nextDMA;
1429 }
1430}
1431
1432void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1433 struct GBAMemory* memory = &gba->memory;
1434 struct ARMCore* cpu = gba->cpu;
1435 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1436 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1437 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1438 int32_t wordsRemaining = info->nextCount;
1439 uint32_t source = info->nextSource;
1440 uint32_t dest = info->nextDest;
1441 uint32_t sourceRegion = source >> BASE_OFFSET;
1442 uint32_t destRegion = dest >> BASE_OFFSET;
1443 int32_t cycles = 2;
1444
1445 if (source == info->source) {
1446 // TODO: support 4 cycles for ROM access
1447 cycles += 2;
1448 if (width == 4) {
1449 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1450 source &= 0xFFFFFFFC;
1451 dest &= 0xFFFFFFFC;
1452 } else {
1453 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1454 }
1455 } else {
1456 if (width == 4) {
1457 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1458 } else {
1459 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1460 }
1461 }
1462
1463 gba->performingDMA = true;
1464 int32_t word;
1465 if (width == 4) {
1466 word = cpu->memory.load32(cpu, source, 0);
1467 gba->bus = word;
1468 cpu->memory.store32(cpu, dest, word, 0);
1469 source += sourceOffset;
1470 dest += destOffset;
1471 --wordsRemaining;
1472 } else {
1473 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1474 word = GBASavedataReadEEPROM(&memory->savedata);
1475 gba->bus = word | (word << 16);
1476 cpu->memory.store16(cpu, dest, word, 0);
1477 source += sourceOffset;
1478 dest += destOffset;
1479 --wordsRemaining;
1480 } else if (destRegion == REGION_CART2_EX) {
1481 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1482 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1483 GBASavedataInitEEPROM(&memory->savedata);
1484 }
1485 word = cpu->memory.load16(cpu, source, 0);
1486 gba->bus = word | (word << 16);
1487 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1488 source += sourceOffset;
1489 dest += destOffset;
1490 --wordsRemaining;
1491 } else {
1492 word = cpu->memory.load16(cpu, source, 0);
1493 gba->bus = word | (word << 16);
1494 cpu->memory.store16(cpu, dest, word, 0);
1495 source += sourceOffset;
1496 dest += destOffset;
1497 --wordsRemaining;
1498 }
1499 }
1500 gba->performingDMA = false;
1501
1502 if (!wordsRemaining) {
1503 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1504 info->reg = GBADMARegisterClearEnable(info->reg);
1505 info->nextEvent = INT_MAX;
1506
1507 // Clear the enable bit in memory
1508 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1509 } else {
1510 info->nextCount = info->count;
1511 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1512 info->nextDest = info->dest;
1513 }
1514 GBAMemoryScheduleDMA(gba, number, info);
1515 }
1516 if (GBADMARegisterIsDoIRQ(info->reg)) {
1517 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1518 }
1519 } else {
1520 info->nextDest = dest;
1521 info->nextCount = wordsRemaining;
1522 }
1523 info->nextSource = source;
1524
1525 if (info->nextEvent != INT_MAX) {
1526 info->nextEvent += cycles;
1527 }
1528 cpu->cycles += cycles;
1529}
1530
1531int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
1532 struct GBA* gba = (struct GBA*) cpu->master;
1533 struct GBAMemory* memory = &gba->memory;
1534
1535 if (memory->activeRegion < REGION_CART0 || !memory->prefetch) {
1536 // The wait is the stall
1537 return wait;
1538 }
1539
1540 // Offload the prefetch timing until the next event, which will happen too early.
1541 memory->prefetchCycles += wait;
1542 ++memory->prefetchStalls;
1543 return wait;
1544}
1545
1546void GBAMemoryInvalidatePrefetch(struct GBA* gba) {
1547 int32_t waited = gba->memory.prefetchCycles;
1548 int32_t nWaits = gba->memory.prefetchStalls;
1549 gba->memory.prefetchCycles = 0;
1550 gba->memory.prefetchStalls = 0;
1551
1552 if (!waited) {
1553 return;
1554 }
1555
1556 int32_t s = gba->cpu->memory.activeSeqCycles16 + 1;
1557 int32_t n2s = gba->cpu->memory.activeNonseqCycles16 - gba->cpu->memory.activeSeqCycles16;
1558
1559 // Figure out how many sequential loads we can jam in
1560 int32_t loads = (waited - 1) / s;
1561 int32_t diff = waited - loads * s;
1562
1563 // The next |loads|S waitstates disappear entirely, so long as they're all in a row.
1564 // Each instruction that waited has an N cycle that was converted into an S, so those
1565 // disappear as well.
1566 int32_t toRemove = (s - 1) * loads + n2s * nWaits + diff;
1567 if (toRemove > gba->cpu->cycles) {
1568 // We have to delay invalidating...
1569 gba->memory.prefetchCycles = gba->memory.prefetchCycles;
1570 gba->memory.prefetchStalls = gba->memory.prefetchStalls;
1571 return;
1572 }
1573 gba->cpu->cycles -= toRemove;
1574}
1575
1576void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1577 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1578 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1579}
1580
1581void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1582 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1583 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1584}
1585
1586uint32_t _popcount32(unsigned bits) {
1587 bits = bits - ((bits >> 1) & 0x55555555);
1588 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1589 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1590}
1591
1592void _pristineCow(struct GBA* gba) {
1593 if (gba->memory.rom != gba->pristineRom) {
1594 return;
1595 }
1596 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1597 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1598 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1599}