src/gba/gba-memory.c (view raw)
1#include "gba-memory.h"
2
3#include "gba-io.h"
4#include "hle-bios.h"
5
6#include <limits.h>
7#include <string.h>
8#include <sys/mman.h>
9
10static const char* GBA_CANNOT_MMAP = "Could not map memory";
11
12static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region);
13
14static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
15static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
16static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
17static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
18static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
19
20void GBAMemoryInit(struct GBAMemory* memory) {
21 memory->d.load32 = GBALoad32;
22 memory->d.load16 = GBALoad16;
23 memory->d.loadU16 = GBALoadU16;
24 memory->d.load8 = GBALoad8;
25 memory->d.loadU8 = GBALoadU8;
26 memory->d.store32 = GBAStore32;
27 memory->d.store16 = GBAStore16;
28 memory->d.store8 = GBAStore8;
29
30 memory->bios = (uint32_t*) hleBios;
31 memory->wram = mmap(0, SIZE_WORKING_RAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
32 memory->iwram = mmap(0, SIZE_WORKING_IRAM, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANON, -1, 0);
33 memory->rom = 0;
34 memset(memory->io, 0, sizeof(memory->io));
35 memset(memory->dma, 0, sizeof(memory->dma));
36
37 if (!memory->wram || !memory->iwram) {
38 GBAMemoryDeinit(memory);
39 memory->p->errno = GBA_OUT_OF_MEMORY;
40 memory->p->errstr = GBA_CANNOT_MMAP;
41 }
42
43 GBASavedataInit(&memory->savedata, "test.sav");
44
45 int i;
46 for (i = 0; i < 16; ++i) {
47 memory->waitstates16[i] = GBA_BASE_WAITSTATES[i];
48 memory->waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
49 memory->waitstates32[i] = GBA_BASE_WAITSTATES[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
50 memory->waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ[i] + GBA_BASE_WAITSTATES_SEQ[i] + 1;
51 }
52 for (; i < 256; ++i) {
53 memory->waitstates16[i] = 0;
54 memory->waitstatesSeq16[i] = 0;
55 memory->waitstates32[i] = 0;
56 memory->waitstatesSeq32[i] = 0;
57 }
58
59 memory->activeRegion = 0;
60 memory->d.activeRegion = 0;
61 memory->d.activeMask = 0;
62 memory->d.setActiveRegion = GBASetActiveRegion;
63 memory->d.activePrefetchCycles32 = 0;
64 memory->d.activePrefetchCycles16 = 0;
65}
66
67void GBAMemoryDeinit(struct GBAMemory* memory) {
68 munmap(memory->wram, SIZE_WORKING_RAM);
69 munmap(memory->iwram, SIZE_WORKING_IRAM);
70 GBASavedataDeinit(&memory->savedata);
71}
72
73static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) {
74 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
75
76 memory->activePrefetchCycles32 = gbaMemory->waitstates32[address >> BASE_OFFSET];
77 memory->activePrefetchCycles16 = gbaMemory->waitstates16[address >> BASE_OFFSET];
78 gbaMemory->activeRegion = address >> BASE_OFFSET;
79 switch (address & ~OFFSET_MASK) {
80 case BASE_BIOS:
81 memory->activeRegion = gbaMemory->bios;
82 memory->activeMask = SIZE_BIOS - 1;
83 break;
84 case BASE_WORKING_RAM:
85 memory->activeRegion = gbaMemory->wram;
86 memory->activeMask = SIZE_WORKING_RAM - 1;
87 break;
88 case BASE_WORKING_IRAM:
89 memory->activeRegion = gbaMemory->iwram;
90 memory->activeMask = SIZE_WORKING_IRAM - 1;
91 break;
92 case BASE_CART0:
93 case BASE_CART0_EX:
94 case BASE_CART1:
95 case BASE_CART1_EX:
96 case BASE_CART2:
97 case BASE_CART2_EX:
98 memory->activeRegion = gbaMemory->rom;
99 memory->activeMask = SIZE_CART0 - 1;
100 break;
101 default:
102 memory->activeRegion = 0;
103 memory->activeMask = 0;
104 break;
105 }
106}
107
108int32_t GBALoad32(struct ARMMemory* memory, uint32_t address) {
109 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
110 uint32_t value = 0;
111
112 switch (address & ~OFFSET_MASK) {
113 case BASE_BIOS:
114 break;
115 case BASE_WORKING_RAM:
116 value = gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2];
117 break;
118 case BASE_WORKING_IRAM:
119 value = gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2];
120 break;
121 case BASE_IO:
122 value = GBAIORead(gbaMemory->p, address & (SIZE_IO - 1)) | (GBAIORead(gbaMemory->p, (address & (SIZE_IO - 1)) | 2) << 16);
123 break;
124 case BASE_PALETTE_RAM:
125 value = ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2];
126 break;
127 case BASE_VRAM:
128 value = ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2];
129 break;
130 case BASE_OAM:
131 break;
132 case BASE_CART0:
133 case BASE_CART0_EX:
134 case BASE_CART1:
135 case BASE_CART1_EX:
136 case BASE_CART2:
137 case BASE_CART2_EX:
138 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
139 value = gbaMemory->rom[(address & (SIZE_CART0 - 1)) >> 2];
140 }
141 break;
142 case BASE_CART_SRAM:
143 break;
144 default:
145 break;
146 }
147
148 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
149 int rotate = (address & 3) << 3;
150 return (value >> rotate) | (value << (32 - rotate));
151}
152
153int16_t GBALoad16(struct ARMMemory* memory, uint32_t address) {
154 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
155
156 switch (address & ~OFFSET_MASK) {
157 case BASE_BIOS:
158 break;
159 case BASE_WORKING_RAM:
160 return ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
161 case BASE_WORKING_IRAM:
162 return ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
163 case BASE_IO:
164 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
165 case BASE_PALETTE_RAM:
166 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
167 case BASE_VRAM:
168 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
169 case BASE_OAM:
170 break;
171 case BASE_CART0:
172 case BASE_CART0_EX:
173 case BASE_CART1:
174 case BASE_CART1_EX:
175 case BASE_CART2:
176 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
177 return ((int16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
178 }
179 case BASE_CART2_EX:
180 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
181 return GBASavedataReadEEPROM(&gbaMemory->savedata);
182 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
183 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
184 }
185 case BASE_CART_SRAM:
186 break;
187 default:
188 break;
189 }
190
191 return 0;
192}
193
194uint16_t GBALoadU16(struct ARMMemory* memory, uint32_t address) {
195 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
196
197 switch (address & ~OFFSET_MASK) {
198 case BASE_BIOS:
199 break;
200 case BASE_WORKING_RAM:
201 return ((uint16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1];
202 case BASE_WORKING_IRAM:
203 return ((uint16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1];
204 case BASE_IO:
205 return GBAIORead(gbaMemory->p, address & (SIZE_IO - 1));
206 case BASE_PALETTE_RAM:
207 return gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1];
208 case BASE_VRAM:
209 return gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1];
210 case BASE_OAM:
211 break;
212 case BASE_CART0:
213 case BASE_CART0_EX:
214 case BASE_CART1:
215 case BASE_CART1_EX:
216 case BASE_CART2:
217 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
218 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
219 }
220 case BASE_CART2_EX:
221 if (gbaMemory->savedata.type == SAVEDATA_EEPROM) {
222 return GBASavedataReadEEPROM(&gbaMemory->savedata);
223 } else if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
224 return ((uint16_t*) gbaMemory->rom)[(address & (SIZE_CART0 - 1)) >> 1];
225 }
226 case BASE_CART_SRAM:
227 break;
228 default:
229 break;
230 }
231
232 return 0;
233}
234
235int8_t GBALoad8(struct ARMMemory* memory, uint32_t address) {
236 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
237
238 switch (address & ~OFFSET_MASK) {
239 case BASE_BIOS:
240 break;
241 case BASE_WORKING_RAM:
242 return ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
243 case BASE_WORKING_IRAM:
244 return ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
245 case BASE_IO:
246 break;
247 case BASE_PALETTE_RAM:
248 break;
249 case BASE_VRAM:
250 break;
251 case BASE_OAM:
252 break;
253 case BASE_CART0:
254 case BASE_CART0_EX:
255 case BASE_CART1:
256 case BASE_CART1_EX:
257 case BASE_CART2:
258 case BASE_CART2_EX:
259 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
260 return ((int8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
261 }
262 case BASE_CART_SRAM:
263 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
264 GBASavedataInitSRAM(&gbaMemory->savedata);
265 }
266 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
267 default:
268 break;
269 }
270
271 return 0;
272}
273
274uint8_t GBALoadU8(struct ARMMemory* memory, uint32_t address) {
275 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
276
277 switch (address & ~OFFSET_MASK) {
278 case BASE_BIOS:
279 break;
280 case BASE_WORKING_RAM:
281 return ((uint8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)];
282 break;
283 case BASE_WORKING_IRAM:
284 return ((uint8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
285 break;
286 case BASE_IO:
287 return (GBAIORead(gbaMemory->p, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
288 case BASE_PALETTE_RAM:
289 break;
290 case BASE_VRAM:
291 break;
292 case BASE_OAM:
293 break;
294 case BASE_CART0:
295 case BASE_CART0_EX:
296 case BASE_CART1:
297 case BASE_CART1_EX:
298 case BASE_CART2:
299 case BASE_CART2_EX:
300 if ((address & (SIZE_CART0 - 1)) < gbaMemory->romSize) {
301 return ((uint8_t*) gbaMemory->rom)[address & (SIZE_CART0 - 1)];
302 }
303 case BASE_CART_SRAM:
304 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
305 GBASavedataInitSRAM(&gbaMemory->savedata);
306 }
307 return gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)];
308 default:
309 break;
310 }
311
312 return 0;
313}
314
315void GBAStore32(struct ARMMemory* memory, uint32_t address, int32_t value) {
316 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
317
318 switch (address & ~OFFSET_MASK) {
319 case BASE_WORKING_RAM:
320 gbaMemory->wram[(address & (SIZE_WORKING_RAM - 1)) >> 2] = value;
321 break;
322 case BASE_WORKING_IRAM:
323 gbaMemory->iwram[(address & (SIZE_WORKING_IRAM - 1)) >> 2] = value;
324 break;
325 case BASE_IO:
326 GBAIOWrite32(gbaMemory->p, address & (SIZE_IO - 1), value);
327 break;
328 case BASE_PALETTE_RAM:
329 ((int32_t*) gbaMemory->p->video.palette)[(address & (SIZE_PALETTE_RAM - 1)) >> 2] = value;
330 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
331 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
332 break;
333 case BASE_VRAM:
334 if ((address & OFFSET_MASK) < SIZE_VRAM - 2) {
335 ((int32_t*) gbaMemory->p->video.vram)[(address & 0x0001FFFF) >> 2] = value;
336 }
337 break;
338 case BASE_OAM:
339 ((int32_t*) gbaMemory->p->video.oam.raw)[(address & (SIZE_OAM - 1)) >> 2] = value;
340 break;
341 case BASE_CART0:
342 break;
343 case BASE_CART_SRAM:
344 break;
345 default:
346 break;
347 }
348}
349
350void GBAStore16(struct ARMMemory* memory, uint32_t address, int16_t value) {
351 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
352
353 switch (address & ~OFFSET_MASK) {
354 case BASE_WORKING_RAM:
355 ((int16_t*) gbaMemory->wram)[(address & (SIZE_WORKING_RAM - 1)) >> 1] = value;
356 break;
357 case BASE_WORKING_IRAM:
358 ((int16_t*) gbaMemory->iwram)[(address & (SIZE_WORKING_IRAM - 1)) >> 1] = value;
359 break;
360 case BASE_IO:
361 GBAIOWrite(gbaMemory->p, address & (SIZE_IO - 1), value);
362 break;
363 case BASE_PALETTE_RAM:
364 gbaMemory->p->video.palette[(address & (SIZE_PALETTE_RAM - 1)) >> 1] = value;
365 gbaMemory->p->video.renderer->writePalette(gbaMemory->p->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
366 break;
367 case BASE_VRAM:
368 if ((address & OFFSET_MASK) < SIZE_VRAM) {
369 gbaMemory->p->video.vram[(address & 0x0001FFFF) >> 1] = value;
370 }
371 break;
372 case BASE_OAM:
373 gbaMemory->p->video.oam.raw[(address & (SIZE_OAM - 1)) >> 1] = value;
374 break;
375 case BASE_CART0:
376 break;
377 case BASE_CART2_EX:
378 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
379 GBASavedataInitEEPROM(&gbaMemory->savedata);
380 }
381 GBASavedataWriteEEPROM(&gbaMemory->savedata, value, 1);
382 break;
383 case BASE_CART_SRAM:
384 break;
385 default:
386 break;
387 }
388}
389
390void GBAStore8(struct ARMMemory* memory, uint32_t address, int8_t value) {
391 struct GBAMemory* gbaMemory = (struct GBAMemory*) memory;
392
393 switch (address & ~OFFSET_MASK) {
394 case BASE_WORKING_RAM:
395 ((int8_t*) gbaMemory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
396 break;
397 case BASE_WORKING_IRAM:
398 ((int8_t*) gbaMemory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
399 break;
400 case BASE_IO:
401 break;
402 case BASE_PALETTE_RAM:
403 break;
404 case BASE_VRAM:
405 break;
406 case BASE_OAM:
407 break;
408 case BASE_CART0:
409 break;
410 case BASE_CART_SRAM:
411 if (gbaMemory->savedata.type == SAVEDATA_NONE) {
412 if (address == SAVEDATA_FLASH_BASE) {
413 GBASavedataInitFlash(&gbaMemory->savedata);
414 } else {
415 GBASavedataInitSRAM(&gbaMemory->savedata);
416 }
417 }
418 if (gbaMemory->savedata.type == SAVEDATA_FLASH512 || gbaMemory->savedata.type == SAVEDATA_FLASH1M) {
419 GBASavedataWriteFlash(&gbaMemory->savedata, value);
420 } else if (gbaMemory->savedata.type == SAVEDATA_SRAM) {
421 gbaMemory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
422 }
423 break;
424 default:
425 break;
426 }
427}
428
429void GBAAdjustWaitstates(struct GBAMemory* memory, uint16_t parameters) {
430 int sram = parameters & 0x0003;
431 int ws0 = (parameters & 0x000C) >> 2;
432 int ws0seq = (parameters & 0x0010) >> 4;
433 int ws1 = (parameters & 0x0060) >> 5;
434 int ws1seq = (parameters & 0x0080) >> 7;
435 int ws2 = (parameters & 0x0300) >> 8;
436 int ws2seq = (parameters & 0x0400) >> 10;
437 int prefetch = parameters & 0x4000;
438
439 memory->waitstates16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
440 memory->waitstatesSeq16[REGION_CART_SRAM] = GBA_ROM_WAITSTATES[sram];
441 memory->waitstates32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
442 memory->waitstatesSeq32[REGION_CART_SRAM] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
443
444 memory->waitstates16[REGION_CART0] = memory->waitstates16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
445 memory->waitstates16[REGION_CART1] = memory->waitstates16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
446 memory->waitstates16[REGION_CART2] = memory->waitstates16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
447
448 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
449 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
450 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
451
452 memory->waitstates32[REGION_CART0] = memory->waitstates32[REGION_CART0_EX] = memory->waitstates16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
453 memory->waitstates32[REGION_CART1] = memory->waitstates32[REGION_CART1_EX] = memory->waitstates16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
454 memory->waitstates32[REGION_CART2] = memory->waitstates32[REGION_CART2_EX] = memory->waitstates16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
455
456 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0 + 1] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
457 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1 + 1] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
458 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2 + 1] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
459
460 memory->d.activePrefetchCycles32 = memory->waitstates32[memory->activeRegion];
461 memory->d.activePrefetchCycles16 = memory->waitstates16[memory->activeRegion];
462}
463
464int32_t GBAMemoryProcessEvents(struct GBAMemory* memory, int32_t cycles) {
465 struct GBADMA* dma;
466 int32_t test = INT_MAX;
467
468 dma = &memory->dma[0];
469 dma->nextIRQ -= cycles;
470 if (dma->enable && dma->doIrq && dma->nextIRQ) {
471 if (dma->nextIRQ <= 0) {
472 dma->nextIRQ = INT_MAX;
473 GBARaiseIRQ(memory->p, IRQ_DMA0);
474 } else if (dma->nextIRQ < test) {
475 test = dma->nextIRQ;
476 }
477 }
478
479 dma = &memory->dma[1];
480 dma->nextIRQ -= cycles;
481 if (dma->enable && dma->doIrq && dma->nextIRQ) {
482 if (dma->nextIRQ <= 0) {
483 dma->nextIRQ = INT_MAX;
484 GBARaiseIRQ(memory->p, IRQ_DMA1);
485 } else if (dma->nextIRQ < test) {
486 test = dma->nextIRQ;
487 }
488 }
489
490 dma = &memory->dma[2];
491 dma->nextIRQ -= cycles;
492 if (dma->enable && dma->doIrq && dma->nextIRQ) {
493 if (dma->nextIRQ <= 0) {
494 dma->nextIRQ = INT_MAX;
495 GBARaiseIRQ(memory->p, IRQ_DMA2);
496 } else if (dma->nextIRQ < test) {
497 test = dma->nextIRQ;
498 }
499 }
500
501 dma = &memory->dma[3];
502 dma->nextIRQ -= cycles;
503 if (dma->enable && dma->doIrq && dma->nextIRQ) {
504 if (dma->nextIRQ <= 0) {
505 dma->nextIRQ = INT_MAX;
506 GBARaiseIRQ(memory->p, IRQ_DMA3);
507 } else if (dma->nextIRQ < test) {
508 test = dma->nextIRQ;
509 }
510 }
511
512 return test;
513}
514
515void GBAMemoryWriteDMASAD(struct GBAMemory* memory, int dma, uint32_t address) {
516 memory->dma[dma].source = address & 0xFFFFFFFE;
517}
518
519void GBAMemoryWriteDMADAD(struct GBAMemory* memory, int dma, uint32_t address) {
520 memory->dma[dma].dest = address & 0xFFFFFFFE;
521}
522
523void GBAMemoryWriteDMACNT_LO(struct GBAMemory* memory, int dma, uint16_t count) {
524 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
525}
526
527uint16_t GBAMemoryWriteDMACNT_HI(struct GBAMemory* memory, int dma, uint16_t control) {
528 struct GBADMA* currentDma = &memory->dma[dma];
529 int wasEnabled = currentDma->enable;
530 currentDma->packed = control;
531 currentDma->nextIRQ = 0;
532
533 if (currentDma->drq) {
534 GBALog(GBA_LOG_STUB, "DRQ not implemented");
535 }
536
537 if (!wasEnabled && currentDma->enable) {
538 currentDma->nextSource = currentDma->source;
539 currentDma->nextDest = currentDma->dest;
540 currentDma->nextCount = currentDma->count;
541 GBAMemoryScheduleDMA(memory, dma, currentDma);
542 }
543 // If the DMA has already occurred, this value might have changed since the function started
544 return currentDma->packed;
545};
546
547void GBAMemoryScheduleDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
548 switch (info->timing) {
549 case DMA_TIMING_NOW:
550 GBAMemoryServiceDMA(memory, number, info);
551 break;
552 case DMA_TIMING_HBLANK:
553 // Handled implicitly
554 break;
555 case DMA_TIMING_VBLANK:
556 // Handled implicitly
557 break;
558 case DMA_TIMING_CUSTOM:
559 switch (number) {
560 case 0:
561 GBALog(GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
562 break;
563 case 1:
564 case 2:
565 //this.cpu.irq.audio.scheduleFIFODma(number, info);
566 break;
567 case 3:
568 //this.cpu.irq.video.scheduleVCaptureDma(dma, info);
569 break;
570 }
571 }
572}
573
574void GBAMemoryRunHblankDMAs(struct GBAMemory* memory) {
575 struct GBADMA* dma;
576 int i;
577 for (i = 0; i < 4; ++i) {
578 dma = &memory->dma[i];
579 if (dma->enable && dma->timing == DMA_TIMING_HBLANK) {
580 GBAMemoryServiceDMA(memory, i, dma);
581 }
582 }
583}
584
585void GBAMemoryRunVblankDMAs(struct GBAMemory* memory) {
586 struct GBADMA* dma;
587 int i;
588 for (i = 0; i < 4; ++i) {
589 dma = &memory->dma[i];
590 if (dma->enable && dma->timing == DMA_TIMING_VBLANK) {
591 GBAMemoryServiceDMA(memory, i, dma);
592 }
593 }
594}
595
596void GBAMemoryServiceDMA(struct GBAMemory* memory, int number, struct GBADMA* info) {
597 if (!info->enable) {
598 // There was a DMA scheduled that got canceled
599 return;
600 }
601
602 uint32_t width = info->width ? 4 : 2;
603 int sourceOffset = DMA_OFFSET[info->srcControl] * width;
604 int destOffset = DMA_OFFSET[info->dstControl] * width;
605 int32_t wordsRemaining = info->nextCount;
606 uint32_t source = info->nextSource;
607 uint32_t dest = info->nextDest;
608 uint32_t sourceRegion = source >> BASE_OFFSET;
609 uint32_t destRegion = dest >> BASE_OFFSET;
610
611 if (width == 4) {
612 int32_t word;
613 source &= 0xFFFFFFFC;
614 dest &= 0xFFFFFFFC;
615 while (wordsRemaining--) {
616 word = GBALoad32(&memory->d, source);
617 GBAStore32(&memory->d, dest, word);
618 source += sourceOffset;
619 dest += destOffset;
620 }
621 } else {
622 uint16_t word;
623 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
624 while (wordsRemaining--) {
625 word = GBASavedataReadEEPROM(&memory->savedata);
626 GBAStore16(&memory->d, dest, word);
627 source += sourceOffset;
628 dest += destOffset;
629 }
630 } else if (destRegion == REGION_CART2_EX) {
631 if (memory->savedata.type != SAVEDATA_EEPROM) {
632 GBASavedataInitEEPROM(&memory->savedata);
633 }
634 while (wordsRemaining) {
635 word = GBALoadU16(&memory->d, source);
636 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
637 source += sourceOffset;
638 dest += destOffset;
639 --wordsRemaining;
640 }
641 } else {
642 while (wordsRemaining--) {
643 word = GBALoadU16(&memory->d, source);
644 GBAStore16(&memory->d, dest, word);
645 source += sourceOffset;
646 dest += destOffset;
647 }
648 }
649 }
650
651 if (info->doIrq) {
652 info->nextIRQ = memory->p->cpu.cycles + 2;
653 info->nextIRQ += (width == 4 ? memory->waitstates32[sourceRegion] + memory->waitstates32[destRegion]
654 : memory->waitstates16[sourceRegion] + memory->waitstates16[destRegion]);
655 info->nextIRQ += (info->count - 1) * (width == 4 ? memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion]
656 : memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion]);
657 }
658
659 info->nextSource = source;
660 info->nextDest = dest;
661 info->nextCount = wordsRemaining;
662
663 if (!info->repeat) {
664 info->enable = 0;
665
666 // Clear the enable bit in memory
667 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
668 } else {
669 info->nextCount = info->count;
670 if (info->dstControl == DMA_INCREMENT_RELOAD) {
671 info->nextDest = info->dest;
672 }
673 GBAMemoryScheduleDMA(memory, number, info);
674 }
675}