src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/sm83/sm83.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/crc32.h>
13#include <mgba-util/vfs.h>
14
15const uint32_t GB_LOGO_HASH = 0x46195417;
16
17mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
18
19static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
20 UNUSED(gb);
21 UNUSED(address);
22 UNUSED(value);
23
24 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
25}
26
27static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
30static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
31static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
32static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
33static void _GBMMM01(struct GB*, uint16_t address, uint8_t value);
34static void _GBHuC1(struct GB*, uint16_t address, uint8_t value);
35static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
36static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
37static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value);
38static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value);
39static void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value);
40
41static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address);
42static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address);
43static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
44static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value);
45
46static uint8_t _GBTAMA5Read(struct GBMemory*, uint16_t address);
47static uint8_t _GBPKJDRead(struct GBMemory*, uint16_t address);
48
49static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
50static void _GBPocketCamCapture(struct GBMemory*);
51
52void GBMBCSwitchBank(struct GB* gb, int bank) {
53 size_t bankStart = bank * GB_SIZE_CART_BANK0;
54 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
55 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
56 bankStart &= (gb->memory.romSize - 1);
57 bank = bankStart / GB_SIZE_CART_BANK0;
58 }
59 gb->memory.romBank = &gb->memory.rom[bankStart];
60 gb->memory.currentBank = bank;
61 if (gb->cpu->pc < GB_BASE_VRAM) {
62 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
63 }
64}
65
66void GBMBCSwitchBank0(struct GB* gb, int bank) {
67 size_t bankStart = bank * GB_SIZE_CART_BANK0;
68 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
69 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
70 bankStart &= (gb->memory.romSize - 1);
71 }
72 gb->memory.romBase = &gb->memory.rom[bankStart];
73 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
74 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
75 }
76}
77
78void GBMBCSwitchHalfBank(struct GB* gb, int half, int bank) {
79 size_t bankStart = bank * GB_SIZE_CART_HALFBANK;
80 if (bankStart + GB_SIZE_CART_HALFBANK > gb->memory.romSize) {
81 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
82 bankStart &= (gb->memory.romSize - 1);
83 bank = bankStart / GB_SIZE_CART_HALFBANK;
84 if (!bank) {
85 ++bank;
86 }
87 }
88 if (!half) {
89 gb->memory.romBank = &gb->memory.rom[bankStart];
90 gb->memory.currentBank = bank;
91 } else {
92 gb->memory.mbcState.mbc6.romBank1 = &gb->memory.rom[bankStart];
93 gb->memory.mbcState.mbc6.currentBank1 = bank;
94 }
95 if (gb->cpu->pc < GB_BASE_VRAM) {
96 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
97 }
98}
99
100static bool _isMulticart(const uint8_t* mem) {
101 bool success;
102 struct VFile* vf;
103
104 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
105 success = GBIsROM(vf);
106 vf->close(vf);
107
108 if (!success) {
109 return false;
110 }
111
112 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
113 success = GBIsROM(vf);
114 vf->close(vf);
115
116 if (!success) {
117 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x30], 1024);
118 success = GBIsROM(vf);
119 vf->close(vf);
120 }
121
122 return success;
123}
124
125static bool _isWisdomTree(const uint8_t* mem, size_t size) {
126 size_t i;
127 for (i = 0x134; i < 0x14C; i += 4) {
128 if (*(uint32_t*) &mem[i] != 0) {
129 return false;
130 }
131 }
132 for (i = 0xF0; i < 0x100; i += 4) {
133 if (*(uint32_t*) &mem[i] != 0) {
134 return false;
135 }
136 }
137 if (mem[0x14D] != 0xE7) {
138 return false;
139 }
140 for (i = 0x300; i < size - 11; ++i) {
141 if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) {
142 return true;
143 }
144 }
145 return false;
146}
147
148void GBMBCSwitchSramBank(struct GB* gb, int bank) {
149 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
150 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
151 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
152 bankStart &= (gb->sramSize - 1);
153 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
154 }
155 gb->memory.sramBank = &gb->memory.sram[bankStart];
156 gb->memory.sramCurrentBank = bank;
157}
158
159void GBMBCSwitchSramHalfBank(struct GB* gb, int half, int bank) {
160 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM_HALFBANK;
161 if (bankStart + GB_SIZE_EXTERNAL_RAM_HALFBANK > gb->sramSize) {
162 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
163 bankStart &= (gb->sramSize - 1);
164 bank = bankStart / GB_SIZE_EXTERNAL_RAM_HALFBANK;
165 }
166 if (!half) {
167 gb->memory.sramBank = &gb->memory.sram[bankStart];
168 gb->memory.sramCurrentBank = bank;
169 } else {
170 gb->memory.mbcState.mbc6.sramBank1 = &gb->memory.sram[bankStart];
171 gb->memory.mbcState.mbc6.currentSramBank1 = bank;
172 }
173}
174
175void GBMBCInit(struct GB* gb) {
176 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
177 if (gb->memory.rom) {
178 if (gb->memory.romSize >= 0x8000) {
179 const struct GBCartridge* cartFooter = (const struct GBCartridge*) &gb->memory.rom[gb->memory.romSize - 0x7F00];
180 if (doCrc32(cartFooter->logo, sizeof(cartFooter->logo)) == GB_LOGO_HASH && cartFooter->type >= 0x0B && cartFooter->type <= 0x0D) {
181 cart = cartFooter;
182 }
183 }
184 switch (cart->ramSize) {
185 case 0:
186 gb->sramSize = 0;
187 break;
188 case 1:
189 gb->sramSize = 0x800;
190 break;
191 default:
192 case 2:
193 gb->sramSize = 0x2000;
194 break;
195 case 3:
196 gb->sramSize = 0x8000;
197 break;
198 case 4:
199 gb->sramSize = 0x20000;
200 break;
201 case 5:
202 gb->sramSize = 0x10000;
203 break;
204 }
205
206 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
207 switch (cart->type) {
208 case 0:
209 if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) {
210 gb->memory.mbcType = GB_UNL_WISDOM_TREE;
211 break;
212 }
213 // Fall through
214 case 8:
215 case 9:
216 gb->memory.mbcType = GB_MBC_NONE;
217 break;
218 case 1:
219 case 2:
220 case 3:
221 gb->memory.mbcType = GB_MBC1;
222 break;
223 case 5:
224 case 6:
225 gb->memory.mbcType = GB_MBC2;
226 break;
227 case 0x0B:
228 case 0x0C:
229 case 0x0D:
230 gb->memory.mbcType = GB_MMM01;
231 break;
232 case 0x0F:
233 case 0x10:
234 gb->memory.mbcType = GB_MBC3_RTC;
235 break;
236 case 0x11:
237 case 0x12:
238 case 0x13:
239 gb->memory.mbcType = GB_MBC3;
240 break;
241 default:
242 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
243 // Fall through
244 case 0x19:
245 case 0x1A:
246 case 0x1B:
247 gb->memory.mbcType = GB_MBC5;
248 break;
249 case 0x1C:
250 case 0x1D:
251 case 0x1E:
252 gb->memory.mbcType = GB_MBC5_RUMBLE;
253 break;
254 case 0x20:
255 gb->memory.mbcType = GB_MBC6;
256 break;
257 case 0x22:
258 gb->memory.mbcType = GB_MBC7;
259 break;
260 case 0xFC:
261 gb->memory.mbcType = GB_POCKETCAM;
262 break;
263 case 0xFD:
264 gb->memory.mbcType = GB_TAMA5;
265 break;
266 case 0xFE:
267 gb->memory.mbcType = GB_HuC3;
268 break;
269 case 0xFF:
270 gb->memory.mbcType = GB_HuC1;
271 break;
272 }
273 }
274 } else {
275 gb->memory.mbcType = GB_MBC_NONE;
276 }
277 gb->memory.mbcRead = NULL;
278 gb->memory.directSramAccess = true;
279 switch (gb->memory.mbcType) {
280 case GB_MBC_NONE:
281 gb->memory.mbcWrite = _GBMBCNone;
282 break;
283 case GB_MBC1:
284 gb->memory.mbcWrite = _GBMBC1;
285 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
286 gb->memory.mbcState.mbc1.multicartStride = 4;
287 } else {
288 gb->memory.mbcState.mbc1.multicartStride = 5;
289 }
290 break;
291 case GB_MBC2:
292 gb->memory.mbcWrite = _GBMBC2;
293 gb->memory.mbcRead = _GBMBC2Read;
294 gb->memory.directSramAccess = false;
295 gb->sramSize = 0x100;
296 break;
297 case GB_MBC3:
298 gb->memory.mbcWrite = _GBMBC3;
299 break;
300 default:
301 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
302 // Fall through
303 case GB_MBC5:
304 gb->memory.mbcWrite = _GBMBC5;
305 break;
306 case GB_MBC6:
307 gb->memory.mbcWrite = _GBMBC6;
308 gb->memory.mbcRead = _GBMBC6Read;
309 gb->memory.directSramAccess = false;
310 break;
311 case GB_MBC7:
312 gb->memory.mbcWrite = _GBMBC7;
313 gb->memory.mbcRead = _GBMBC7Read;
314 gb->sramSize = 0x100;
315 break;
316 case GB_MMM01:
317 gb->memory.mbcWrite = _GBMMM01;
318 break;
319 case GB_HuC1:
320 gb->memory.mbcWrite = _GBHuC1;
321 break;
322 case GB_HuC3:
323 gb->memory.mbcWrite = _GBHuC3;
324 break;
325 case GB_TAMA5:
326 mLOG(GB_MBC, WARN, "unimplemented MBC: TAMA5");
327 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
328 gb->memory.mbcWrite = _GBTAMA5;
329 gb->memory.mbcRead = _GBTAMA5Read;
330 gb->sramSize = 0x20;
331 break;
332 case GB_MBC3_RTC:
333 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
334 gb->memory.mbcWrite = _GBMBC3;
335 break;
336 case GB_MBC5_RUMBLE:
337 gb->memory.mbcWrite = _GBMBC5;
338 break;
339 case GB_POCKETCAM:
340 gb->memory.mbcWrite = _GBPocketCam;
341 gb->memory.mbcRead = _GBPocketCamRead;
342 if (gb->memory.cam && gb->memory.cam->startRequestImage) {
343 gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY);
344 }
345 break;
346 case GB_UNL_WISDOM_TREE:
347 gb->memory.mbcWrite = _GBWisdomTree;
348 break;
349 case GB_UNL_PKJD:
350 gb->memory.mbcWrite = _GBPKJD;
351 gb->memory.mbcRead = _GBPKJDRead;
352 break;
353 }
354
355 gb->memory.currentBank = 1;
356 gb->memory.sramCurrentBank = 0;
357 gb->memory.sramAccess = false;
358 gb->memory.rtcAccess = false;
359 gb->memory.activeRtcReg = 0;
360 gb->memory.rtcLatched = false;
361 gb->memory.rtcLastLatch = 0;
362 if (gb->memory.rtc) {
363 if (gb->memory.rtc->sample) {
364 gb->memory.rtc->sample(gb->memory.rtc);
365 }
366 gb->memory.rtcLastLatch = gb->memory.rtc->unixTime(gb->memory.rtc);
367 } else {
368 gb->memory.rtcLastLatch = time(0);
369 }
370 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
371
372 GBResizeSram(gb, gb->sramSize);
373
374 if (gb->memory.mbcType == GB_MBC3_RTC) {
375 GBMBCRTCRead(gb);
376 }
377}
378
379static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
380 time_t t;
381 if (rtc) {
382 if (rtc->sample) {
383 rtc->sample(rtc);
384 }
385 t = rtc->unixTime(rtc);
386 } else {
387 t = time(0);
388 }
389 time_t currentLatch = t;
390 t -= *rtcLastLatch;
391 *rtcLastLatch = currentLatch;
392
393 int64_t diff;
394 diff = rtcRegs[0] + t % 60;
395 if (diff < 0) {
396 diff += 60;
397 t -= 60;
398 }
399 rtcRegs[0] = diff % 60;
400 t /= 60;
401 t += diff / 60;
402
403 diff = rtcRegs[1] + t % 60;
404 if (diff < 0) {
405 diff += 60;
406 t -= 60;
407 }
408 rtcRegs[1] = diff % 60;
409 t /= 60;
410 t += diff / 60;
411
412 diff = rtcRegs[2] + t % 24;
413 if (diff < 0) {
414 diff += 24;
415 t -= 24;
416 }
417 rtcRegs[2] = diff % 24;
418 t /= 24;
419 t += diff / 24;
420
421 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
422 rtcRegs[3] = diff;
423 rtcRegs[4] &= 0xFE;
424 rtcRegs[4] |= (diff >> 8) & 1;
425 if (diff & 0x200) {
426 rtcRegs[4] |= 0x80;
427 }
428}
429
430static void _GBMBC1Update(struct GB* gb) {
431 struct GBMBC1State* state = &gb->memory.mbcState.mbc1;
432 int bank = state->bankLo;
433 bank &= (1 << state->multicartStride) - 1;
434 bank |= state->bankHi << state->multicartStride;
435 if (state->mode) {
436 GBMBCSwitchBank0(gb, state->bankHi << state->multicartStride);
437 GBMBCSwitchSramBank(gb, state->bankHi & 3);
438 } else {
439 GBMBCSwitchBank0(gb, 0);
440 GBMBCSwitchSramBank(gb, 0);
441 }
442 if (!(state->bankLo & 0x1F)) {
443 ++state->bankLo;
444 ++bank;
445 }
446 GBMBCSwitchBank(gb, bank);
447}
448
449void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
450 struct GBMemory* memory = &gb->memory;
451 int bank = value & 0x1F;
452 switch (address >> 13) {
453 case 0x0:
454 switch (value & 0xF) {
455 case 0:
456 memory->sramAccess = false;
457 break;
458 case 0xA:
459 memory->sramAccess = true;
460 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
461 break;
462 default:
463 // TODO
464 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
465 break;
466 }
467 break;
468 case 0x1:
469 memory->mbcState.mbc1.bankLo = bank;
470 _GBMBC1Update(gb);
471 break;
472 case 0x2:
473 bank &= 3;
474 memory->mbcState.mbc1.bankHi = bank;
475 _GBMBC1Update(gb);
476 break;
477 case 0x3:
478 memory->mbcState.mbc1.mode = value & 1;
479 _GBMBC1Update(gb);
480 break;
481 default:
482 // TODO
483 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
484 break;
485 }
486}
487
488void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
489 struct GBMemory* memory = &gb->memory;
490 int shift = (address & 1) * 4;
491 int bank = value & 0xF;
492 switch ((address & 0xC100) >> 8) {
493 case 0x0:
494 switch (value & 0x0F) {
495 case 0:
496 memory->sramAccess = false;
497 break;
498 case 0xA:
499 memory->sramAccess = true;
500 break;
501 default:
502 // TODO
503 mLOG(GB_MBC, STUB, "MBC2 unknown value %02X", value);
504 break;
505 }
506 break;
507 case 0x1:
508 if (!bank) {
509 ++bank;
510 }
511 GBMBCSwitchBank(gb, bank);
512 break;
513 case 0x80:
514 case 0x81:
515 case 0x82:
516 case 0x83:
517 if (!memory->sramAccess) {
518 return;
519 }
520 address &= 0x1FF;
521 memory->sramBank[(address >> 1)] &= 0xF0 >> shift;
522 memory->sramBank[(address >> 1)] |= (value & 0xF) << shift;
523 break;
524 default:
525 // TODO
526 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
527 break;
528 }
529}
530
531static uint8_t _GBMBC2Read(struct GBMemory* memory, uint16_t address) {
532 if (!memory->sramAccess) {
533 return 0xFF;
534 }
535 address &= 0x1FF;
536 int shift = (address & 1) * 4;
537 return (memory->sramBank[(address >> 1)] >> shift) | 0xF0;
538}
539
540void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
541 struct GBMemory* memory = &gb->memory;
542 int bank = value;
543 switch (address >> 13) {
544 case 0x0:
545 switch (value) {
546 case 0:
547 memory->sramAccess = false;
548 break;
549 case 0xA:
550 memory->sramAccess = true;
551 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
552 break;
553 default:
554 // TODO
555 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
556 break;
557 }
558 break;
559 case 0x1:
560 if (gb->memory.romSize < GB_SIZE_CART_BANK0 * 0x80) {
561 bank &= 0x7F;
562 }
563 if (!bank) {
564 ++bank;
565 }
566 GBMBCSwitchBank(gb, bank);
567 break;
568 case 0x2:
569 if (value < 8) {
570 GBMBCSwitchSramBank(gb, value);
571 memory->rtcAccess = false;
572 } else if (value <= 0xC) {
573 memory->activeRtcReg = value - 8;
574 memory->rtcAccess = true;
575 }
576 break;
577 case 0x3:
578 if (memory->rtcLatched && value == 0) {
579 memory->rtcLatched = false;
580 } else if (!memory->rtcLatched && value == 1) {
581 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
582 memory->rtcLatched = true;
583 }
584 break;
585 }
586}
587
588void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
589 struct GBMemory* memory = &gb->memory;
590 int bank;
591 switch (address >> 12) {
592 case 0x0:
593 case 0x1:
594 switch (value) {
595 case 0:
596 memory->sramAccess = false;
597 break;
598 case 0xA:
599 memory->sramAccess = true;
600 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
601 break;
602 default:
603 // TODO
604 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
605 break;
606 }
607 break;
608 case 0x2:
609 bank = (memory->currentBank & 0x100) | value;
610 GBMBCSwitchBank(gb, bank);
611 break;
612 case 0x3:
613 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
614 GBMBCSwitchBank(gb, bank);
615 break;
616 case 0x4:
617 case 0x5:
618 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
619 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
620 value &= ~8;
621 }
622 GBMBCSwitchSramBank(gb, value & 0xF);
623 break;
624 default:
625 // TODO
626 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
627 break;
628 }
629}
630
631void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
632 struct GBMemory* memory = &gb->memory;
633 int bank = value;
634 switch (address >> 10) {
635 case 0:
636 switch (value) {
637 case 0:
638 memory->sramAccess = false;
639 break;
640 case 0xA:
641 memory->sramAccess = true;
642 break;
643 default:
644 // TODO
645 mLOG(GB_MBC, STUB, "MBC6 unknown value %02X", value);
646 break;
647 }
648 break;
649 case 0x1:
650 GBMBCSwitchSramHalfBank(gb, 0, bank);
651 break;
652 case 0x2:
653 GBMBCSwitchSramHalfBank(gb, 1, bank);
654 break;
655 case 0x8:
656 case 0x9:
657 GBMBCSwitchHalfBank(gb, 0, bank);
658 break;
659 case 0xC:
660 case 0xD:
661 GBMBCSwitchHalfBank(gb, 1, bank);
662 break;
663 case 0x28:
664 case 0x29:
665 case 0x2A:
666 case 0x2B:
667 if (memory->sramAccess) {
668 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
669 }
670 break;
671 case 0x2C:
672 case 0x2D:
673 case 0x2E:
674 case 0x2F:
675 if (memory->sramAccess) {
676 memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)] = value;
677 }
678 break;
679 default:
680 mLOG(GB_MBC, STUB, "MBC6 unknown address: %04X:%02X", address, value);
681 break;
682 }
683}
684
685uint8_t _GBMBC6Read(struct GBMemory* memory, uint16_t address) {
686 if (!memory->sramAccess) {
687 return 0xFF;
688 }
689 switch (address >> 12) {
690 case 0xA:
691 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
692 case 0xB:
693 return memory->mbcState.mbc6.sramBank1[address & (GB_SIZE_EXTERNAL_RAM_HALFBANK - 1)];
694 }
695 return 0xFF;
696}
697
698void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
699 int bank = value & 0x7F;
700 switch (address >> 13) {
701 case 0x0:
702 switch (value) {
703 default:
704 case 0:
705 gb->memory.mbcState.mbc7.access = 0;
706 break;
707 case 0xA:
708 gb->memory.mbcState.mbc7.access |= 1;
709 break;
710 }
711 break;
712 case 0x1:
713 GBMBCSwitchBank(gb, bank);
714 break;
715 case 0x2:
716 if (value == 0x40) {
717 gb->memory.mbcState.mbc7.access |= 2;
718 } else {
719 gb->memory.mbcState.mbc7.access &= ~2;
720 }
721 break;
722 case 0x5:
723 _GBMBC7Write(&gb->memory, address, value);
724 break;
725 default:
726 // TODO
727 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
728 break;
729 }
730}
731
732uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
733 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
734 if (mbc7->access != 3) {
735 return 0xFF;
736 }
737 switch (address & 0xF0) {
738 case 0x20:
739 if (memory->rotation && memory->rotation->readTiltX) {
740 int32_t x = -memory->rotation->readTiltX(memory->rotation);
741 x >>= 21;
742 x += 0x81D0;
743 return x;
744 }
745 return 0xFF;
746 case 0x30:
747 if (memory->rotation && memory->rotation->readTiltX) {
748 int32_t x = -memory->rotation->readTiltX(memory->rotation);
749 x >>= 21;
750 x += 0x81D0;
751 return x >> 8;
752 }
753 return 7;
754 case 0x40:
755 if (memory->rotation && memory->rotation->readTiltY) {
756 int32_t y = -memory->rotation->readTiltY(memory->rotation);
757 y >>= 21;
758 y += 0x81D0;
759 return y;
760 }
761 return 0xFF;
762 case 0x50:
763 if (memory->rotation && memory->rotation->readTiltY) {
764 int32_t y = -memory->rotation->readTiltY(memory->rotation);
765 y >>= 21;
766 y += 0x81D0;
767 return y >> 8;
768 }
769 return 7;
770 case 0x60:
771 return 0;
772 case 0x80:
773 return mbc7->eeprom;
774 default:
775 return 0xFF;
776 }
777}
778
779static void _GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
780 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
781 if (mbc7->access != 3) {
782 return;
783 }
784 switch (address & 0xF0) {
785 case 0x00:
786 mbc7->latch = (value & 0x55) == 0x55;
787 return;
788 case 0x10:
789 mbc7->latch |= (value & 0xAA);
790 if (mbc7->latch == 0xAB && memory->rotation && memory->rotation->sample) {
791 memory->rotation->sample(memory->rotation);
792 }
793 mbc7->latch = 0;
794 return;
795 default:
796 mLOG(GB_MBC, STUB, "MBC7 unknown register: %04X:%02X", address, value);
797 return;
798 case 0x80:
799 break;
800 }
801 GBMBC7Field old = memory->mbcState.mbc7.eeprom;
802 value = GBMBC7FieldFillDO(value); // Hi-Z
803 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
804 mbc7->state = GBMBC7_STATE_IDLE;
805 }
806 if (!GBMBC7FieldIsCLK(old) && GBMBC7FieldIsCLK(value)) {
807 if (mbc7->state == GBMBC7_STATE_READ_COMMAND || mbc7->state == GBMBC7_STATE_EEPROM_WRITE || mbc7->state == GBMBC7_STATE_EEPROM_WRAL) {
808 mbc7->sr <<= 1;
809 mbc7->sr |= GBMBC7FieldGetDI(value);
810 ++mbc7->srBits;
811 }
812 switch (mbc7->state) {
813 case GBMBC7_STATE_IDLE:
814 if (GBMBC7FieldIsDI(value)) {
815 mbc7->state = GBMBC7_STATE_READ_COMMAND;
816 mbc7->srBits = 0;
817 mbc7->sr = 0;
818 }
819 break;
820 case GBMBC7_STATE_READ_COMMAND:
821 if (mbc7->srBits == 10) {
822 mbc7->state = 0x10 | (mbc7->sr >> 6);
823 if (mbc7->state & 0xC) {
824 mbc7->state &= ~0x3;
825 }
826 mbc7->srBits = 0;
827 mbc7->address = mbc7->sr & 0x7F;
828 }
829 break;
830 case GBMBC7_STATE_DO:
831 value = GBMBC7FieldSetDO(value, mbc7->sr >> 15);
832 mbc7->sr <<= 1;
833 --mbc7->srBits;
834 if (!mbc7->srBits) {
835 mbc7->state = GBMBC7_STATE_IDLE;
836 }
837 break;
838 default:
839 break;
840 }
841 switch (mbc7->state) {
842 case GBMBC7_STATE_EEPROM_EWEN:
843 mbc7->writable = true;
844 mbc7->state = GBMBC7_STATE_IDLE;
845 break;
846 case GBMBC7_STATE_EEPROM_EWDS:
847 mbc7->writable = false;
848 mbc7->state = GBMBC7_STATE_IDLE;
849 break;
850 case GBMBC7_STATE_EEPROM_WRITE:
851 if (mbc7->srBits == 16) {
852 if (mbc7->writable) {
853 memory->sram[mbc7->address * 2] = mbc7->sr >> 8;
854 memory->sram[mbc7->address * 2 + 1] = mbc7->sr;
855 }
856 mbc7->state = GBMBC7_STATE_IDLE;
857 }
858 break;
859 case GBMBC7_STATE_EEPROM_ERASE:
860 if (mbc7->writable) {
861 memory->sram[mbc7->address * 2] = 0xFF;
862 memory->sram[mbc7->address * 2 + 1] = 0xFF;
863 }
864 mbc7->state = GBMBC7_STATE_IDLE;
865 break;
866 case GBMBC7_STATE_EEPROM_READ:
867 mbc7->srBits = 16;
868 mbc7->sr = memory->sram[mbc7->address * 2] << 8;
869 mbc7->sr |= memory->sram[mbc7->address * 2 + 1];
870 mbc7->state = GBMBC7_STATE_DO;
871 value = GBMBC7FieldClearDO(value);
872 break;
873 case GBMBC7_STATE_EEPROM_WRAL:
874 if (mbc7->srBits == 16) {
875 if (mbc7->writable) {
876 int i;
877 for (i = 0; i < 128; ++i) {
878 memory->sram[i * 2] = mbc7->sr >> 8;
879 memory->sram[i * 2 + 1] = mbc7->sr;
880 }
881 }
882 mbc7->state = GBMBC7_STATE_IDLE;
883 }
884 break;
885 case GBMBC7_STATE_EEPROM_ERAL:
886 if (mbc7->writable) {
887 int i;
888 for (i = 0; i < 128; ++i) {
889 memory->sram[i * 2] = 0xFF;
890 memory->sram[i * 2 + 1] = 0xFF;
891 }
892 }
893 mbc7->state = GBMBC7_STATE_IDLE;
894 break;
895 default:
896 break;
897 }
898 } else if (GBMBC7FieldIsCS(value) && GBMBC7FieldIsCLK(old) && !GBMBC7FieldIsCLK(value)) {
899 value = GBMBC7FieldSetDO(value, GBMBC7FieldGetDO(old));
900 }
901 mbc7->eeprom = value;
902}
903
904void _GBMMM01(struct GB* gb, uint16_t address, uint8_t value) {
905 struct GBMemory* memory = &gb->memory;
906 if (!memory->mbcState.mmm01.locked) {
907 switch (address >> 13) {
908 case 0x0:
909 memory->mbcState.mmm01.locked = true;
910 GBMBCSwitchBank0(gb, memory->mbcState.mmm01.currentBank0);
911 break;
912 case 0x1:
913 memory->mbcState.mmm01.currentBank0 &= ~0x7F;
914 memory->mbcState.mmm01.currentBank0 |= value & 0x7F;
915 break;
916 case 0x2:
917 memory->mbcState.mmm01.currentBank0 &= ~0x180;
918 memory->mbcState.mmm01.currentBank0 |= (value & 0x30) << 3;
919 break;
920 default:
921 // TODO
922 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
923 break;
924 }
925 return;
926 }
927 switch (address >> 13) {
928 case 0x0:
929 switch (value) {
930 case 0xA:
931 memory->sramAccess = true;
932 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
933 break;
934 default:
935 memory->sramAccess = false;
936 break;
937 }
938 break;
939 case 0x1:
940 GBMBCSwitchBank(gb, value + memory->mbcState.mmm01.currentBank0);
941 break;
942 case 0x2:
943 GBMBCSwitchSramBank(gb, value);
944 break;
945 default:
946 // TODO
947 mLOG(GB_MBC, STUB, "MMM01 unknown address: %04X:%02X", address, value);
948 break;
949 }
950}
951
952void _GBHuC1(struct GB* gb, uint16_t address, uint8_t value) {
953 struct GBMemory* memory = &gb->memory;
954 int bank = value & 0x3F;
955 switch (address >> 13) {
956 case 0x0:
957 switch (value) {
958 case 0xE:
959 memory->sramAccess = false;
960 break;
961 default:
962 memory->sramAccess = true;
963 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
964 break;
965 }
966 break;
967 case 0x1:
968 GBMBCSwitchBank(gb, bank);
969 break;
970 case 0x2:
971 GBMBCSwitchSramBank(gb, value);
972 break;
973 default:
974 // TODO
975 mLOG(GB_MBC, STUB, "HuC-1 unknown address: %04X:%02X", address, value);
976 break;
977 }
978}
979
980void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
981 struct GBMemory* memory = &gb->memory;
982 int bank = value & 0x3F;
983 if (address & 0x1FFF) {
984 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
985 }
986
987 switch (address >> 13) {
988 case 0x0:
989 switch (value) {
990 case 0xA:
991 memory->sramAccess = true;
992 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
993 break;
994 default:
995 memory->sramAccess = false;
996 break;
997 }
998 break;
999 case 0x1:
1000 GBMBCSwitchBank(gb, bank);
1001 break;
1002 case 0x2:
1003 GBMBCSwitchSramBank(gb, bank);
1004 break;
1005 default:
1006 // TODO
1007 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
1008 break;
1009 }
1010}
1011
1012void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
1013 struct GBMemory* memory = &gb->memory;
1014 int bank = value & 0x3F;
1015 switch (address >> 13) {
1016 case 0x0:
1017 switch (value) {
1018 case 0:
1019 memory->sramAccess = false;
1020 break;
1021 case 0xA:
1022 memory->sramAccess = true;
1023 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
1024 break;
1025 default:
1026 // TODO
1027 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
1028 break;
1029 }
1030 break;
1031 case 0x1:
1032 GBMBCSwitchBank(gb, bank);
1033 break;
1034 case 0x2:
1035 if (value < 0x10) {
1036 GBMBCSwitchSramBank(gb, value);
1037 memory->mbcState.pocketCam.registersActive = false;
1038 } else {
1039 memory->mbcState.pocketCam.registersActive = true;
1040 }
1041 break;
1042 case 0x5:
1043 address &= 0x7F;
1044 if (address == 0 && value & 1) {
1045 value &= 6; // TODO: Timing
1046 _GBPocketCamCapture(memory);
1047 }
1048 if (address < sizeof(memory->mbcState.pocketCam.registers)) {
1049 memory->mbcState.pocketCam.registers[address] = value;
1050 }
1051 break;
1052 default:
1053 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
1054 break;
1055 }
1056}
1057
1058uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
1059 if (memory->mbcState.pocketCam.registersActive) {
1060 if ((address & 0x7F) == 0) {
1061 return memory->mbcState.pocketCam.registers[0];
1062 }
1063 return 0;
1064 }
1065 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1066}
1067
1068void _GBPocketCamCapture(struct GBMemory* memory) {
1069 if (!memory->cam) {
1070 return;
1071 }
1072 const void* image = NULL;
1073 size_t stride;
1074 enum mColorFormat format;
1075 memory->cam->requestImage(memory->cam, &image, &stride, &format);
1076 if (!image) {
1077 return;
1078 }
1079 memset(&memory->sram[0x100], 0, GBCAM_HEIGHT * GBCAM_WIDTH / 4);
1080 struct GBPocketCamState* pocketCam = &memory->mbcState.pocketCam;
1081 size_t x, y;
1082 for (y = 0; y < GBCAM_HEIGHT; ++y) {
1083 for (x = 0; x < GBCAM_WIDTH; ++x) {
1084 uint32_t gray;
1085 uint32_t color;
1086 switch (format) {
1087 case mCOLOR_XBGR8:
1088 case mCOLOR_XRGB8:
1089 case mCOLOR_ARGB8:
1090 case mCOLOR_ABGR8:
1091 color = ((const uint32_t*) image)[y * stride + x];
1092 gray = (color & 0xFF) + ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF);
1093 break;
1094 case mCOLOR_BGRX8:
1095 case mCOLOR_RGBX8:
1096 case mCOLOR_RGBA8:
1097 case mCOLOR_BGRA8:
1098 color = ((const uint32_t*) image)[y * stride + x];
1099 gray = ((color >> 8) & 0xFF) + ((color >> 16) & 0xFF) + ((color >> 24) & 0xFF);
1100 break;
1101 case mCOLOR_BGR5:
1102 case mCOLOR_RGB5:
1103 case mCOLOR_ARGB5:
1104 case mCOLOR_ABGR5:
1105 color = ((const uint16_t*) image)[y * stride + x];
1106 gray = ((color << 3) & 0xF8) + ((color >> 2) & 0xF8) + ((color >> 7) & 0xF8);
1107 break;
1108 case mCOLOR_BGR565:
1109 case mCOLOR_RGB565:
1110 color = ((const uint16_t*) image)[y * stride + x];
1111 gray = ((color << 3) & 0xF8) + ((color >> 3) & 0xFC) + ((color >> 8) & 0xF8);
1112 break;
1113 case mCOLOR_BGRA5:
1114 case mCOLOR_RGBA5:
1115 color = ((const uint16_t*) image)[y * stride + x];
1116 gray = ((color << 2) & 0xF8) + ((color >> 3) & 0xF8) + ((color >> 8) & 0xF8);
1117 break;
1118 default:
1119 mLOG(GB_MBC, WARN, "Unsupported pixel format: %X", format);
1120 return;
1121 }
1122 uint16_t exposure = (pocketCam->registers[2] << 8) | (pocketCam->registers[3]);
1123 gray = (gray + 1) * exposure / 0x300;
1124 // TODO: Additional processing
1125 int matrixEntry = 3 * ((x & 3) + 4 * (y & 3));
1126 if (gray < pocketCam->registers[matrixEntry + 6]) {
1127 gray = 0x101;
1128 } else if (gray < pocketCam->registers[matrixEntry + 7]) {
1129 gray = 0x100;
1130 } else if (gray < pocketCam->registers[matrixEntry + 8]) {
1131 gray = 0x001;
1132 } else {
1133 gray = 0;
1134 }
1135 int coord = (((x >> 3) & 0xF) * 8 + (y & 0x7)) * 2 + (y & ~0x7) * 0x20;
1136 uint16_t existing;
1137 LOAD_16LE(existing, coord + 0x100, memory->sram);
1138 existing |= gray << (7 - (x & 7));
1139 STORE_16LE(existing, coord + 0x100, memory->sram);
1140 }
1141 }
1142}
1143
1144void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value) {
1145 struct GBMemory* memory = &gb->memory;
1146 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1147 switch (address >> 13) {
1148 case 0x5:
1149 if (address & 1) {
1150 tama5->reg = value;
1151 } else {
1152 value &= 0xF;
1153 if (tama5->reg < GBTAMA5_MAX) {
1154 tama5->registers[tama5->reg] = value;
1155 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1156 uint8_t out = (tama5->registers[GBTAMA5_WRITE_HI] << 4) | tama5->registers[GBTAMA5_WRITE_LO];
1157 switch (tama5->reg) {
1158 case GBTAMA5_BANK_LO:
1159 case GBTAMA5_BANK_HI:
1160 GBMBCSwitchBank(gb, tama5->registers[GBTAMA5_BANK_LO] | (tama5->registers[GBTAMA5_BANK_HI] << 4));
1161 break;
1162 case GBTAMA5_WRITE_LO:
1163 case GBTAMA5_WRITE_HI:
1164 case GBTAMA5_CS:
1165 break;
1166 case GBTAMA5_ADDR_LO:
1167 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1168 case 0x0: // RAM write
1169 memory->sram[address] = out;
1170 break;
1171 case 0x1: // RAM read
1172 break;
1173 default:
1174 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %X-%02X:%02X", tama5->registers[GBTAMA5_CS] >> 1, address, out);
1175 }
1176 break;
1177 default:
1178 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X:%X", tama5->reg, value);
1179 break;
1180 }
1181 } else {
1182 mLOG(GB_MBC, STUB, "TAMA5 unknown write: %02X", tama5->reg);
1183 }
1184 }
1185 break;
1186 default:
1187 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X:%02X", address, value);
1188 }
1189}
1190
1191uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) {
1192 struct GBTAMA5State* tama5 = &memory->mbcState.tama5;
1193 if ((address & 0x1FFF) > 1) {
1194 mLOG(GB_MBC, STUB, "TAMA5 unknown address: %04X", address);
1195 }
1196 if (address & 1) {
1197 return 0xFF;
1198 } else {
1199 uint8_t value = 0xF0;
1200 uint8_t address = ((tama5->registers[GBTAMA5_CS] << 4) & 0x10) | tama5->registers[GBTAMA5_ADDR_LO];
1201 switch (tama5->reg) {
1202 case GBTAMA5_ACTIVE:
1203 return 0xF1;
1204 case GBTAMA5_READ_LO:
1205 case GBTAMA5_READ_HI:
1206 switch (tama5->registers[GBTAMA5_CS] >> 1) {
1207 case 1:
1208 value = memory->sram[address];
1209 break;
1210 default:
1211 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1212 break;
1213 }
1214 if (tama5->reg == GBTAMA5_READ_HI) {
1215 value >>= 4;
1216 }
1217 value |= 0xF0;
1218 return value;
1219 default:
1220 mLOG(GB_MBC, STUB, "TAMA5 unknown read: %02X", tama5->reg);
1221 return 0xF1;
1222 }
1223 }
1224}
1225
1226void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) {
1227 UNUSED(value);
1228 int bank = address & 0x3F;
1229 switch (address >> 14) {
1230 case 0x0:
1231 GBMBCSwitchBank0(gb, bank * 2);
1232 GBMBCSwitchBank(gb, bank * 2 + 1);
1233 break;
1234 default:
1235 // TODO
1236 mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value);
1237 break;
1238 }
1239}
1240
1241void _GBPKJD(struct GB* gb, uint16_t address, uint8_t value) {
1242 struct GBMemory* memory = &gb->memory;
1243 switch (address >> 13) {
1244 case 0x2:
1245 if (value < 8) {
1246 memory->directSramAccess = true;
1247 memory->activeRtcReg = 0;
1248 } else if (value >= 0xD && value <= 0xF) {
1249 memory->directSramAccess = false;
1250 memory->rtcAccess = false;
1251 memory->activeRtcReg = value - 8;
1252 }
1253 break;
1254 case 0x5:
1255 if (!memory->sramAccess) {
1256 return;
1257 }
1258 switch (memory->activeRtcReg) {
1259 case 0:
1260 memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)] = value;
1261 break;
1262 case 5:
1263 case 6:
1264 memory->mbcState.pkjd.reg[memory->activeRtcReg - 5] = value;
1265 break;
1266 case 7:
1267 switch (value) {
1268 case 0x11:
1269 memory->mbcState.pkjd.reg[0]--;
1270 break;
1271 case 0x12:
1272 memory->mbcState.pkjd.reg[1]--;
1273 break;
1274 case 0x41:
1275 memory->mbcState.pkjd.reg[0] += memory->mbcState.pkjd.reg[1];
1276 break;
1277 case 0x42:
1278 memory->mbcState.pkjd.reg[1] += memory->mbcState.pkjd.reg[0];
1279 break;
1280 case 0x51:
1281 memory->mbcState.pkjd.reg[0]++;
1282 break;
1283 case 0x52:
1284 memory->mbcState.pkjd.reg[1]--;
1285 break;
1286 }
1287 break;
1288 }
1289 return;
1290 }
1291 _GBMBC3(gb, address, value);
1292}
1293
1294static uint8_t _GBPKJDRead(struct GBMemory* memory, uint16_t address) {
1295 if (!memory->sramAccess) {
1296 return 0xFF;
1297 }
1298 switch (memory->activeRtcReg) {
1299 case 0:
1300 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
1301 case 5:
1302 case 6:
1303 return memory->mbcState.pkjd.reg[memory->activeRtcReg - 5];
1304 default:
1305 return 0;
1306 }
1307}
1308
1309void GBMBCRTCRead(struct GB* gb) {
1310 struct GBMBCRTCSaveBuffer rtcBuffer;
1311 struct VFile* vf = gb->sramVf;
1312 if (!vf) {
1313 return;
1314 }
1315 vf->seek(vf, gb->sramSize, SEEK_SET);
1316 if (vf->read(vf, &rtcBuffer, sizeof(rtcBuffer)) < (ssize_t) sizeof(rtcBuffer) - 4) {
1317 return;
1318 }
1319
1320 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1321 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1322 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1323 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1324 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1325 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1326}
1327
1328void GBMBCRTCWrite(struct GB* gb) {
1329 struct VFile* vf = gb->sramVf;
1330 if (!vf) {
1331 return;
1332 }
1333
1334 uint8_t rtcRegs[5];
1335 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
1336 time_t rtcLastLatch = gb->memory.rtcLastLatch;
1337 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
1338
1339 struct GBMBCRTCSaveBuffer rtcBuffer;
1340 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
1341 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
1342 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
1343 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
1344 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
1345 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
1346 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
1347 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
1348 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
1349 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
1350 STORE_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
1351
1352 if ((size_t) vf->size(vf) < gb->sramSize + sizeof(rtcBuffer)) {
1353 // Writing past the end of the file can invalidate the file mapping
1354 vf->unmap(vf, gb->memory.sram, gb->sramSize);
1355 gb->memory.sram = NULL;
1356 }
1357 vf->seek(vf, gb->sramSize, SEEK_SET);
1358 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
1359 if (!gb->memory.sram) {
1360 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
1361 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
1362 }
1363}