src/gba/memory.c (view raw)
1/* Copyright (c) 2013-2015 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include "memory.h"
7
8#include "macros.h"
9
10#include "decoder.h"
11#include "gba/hardware.h"
12#include "gba/io.h"
13#include "gba/serialize.h"
14#include "gba/hle-bios.h"
15#include "util/memory.h"
16
17#define IDLE_LOOP_THRESHOLD 10000
18
19static uint32_t _popcount32(unsigned bits);
20static void _pristineCow(struct GBA* gba);
21static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
22
23static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
24static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
25
26static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
27static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
28static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
29static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
30static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
31static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
32static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
33
34void GBAMemoryInit(struct GBA* gba) {
35 struct ARMCore* cpu = gba->cpu;
36 cpu->memory.load32 = GBALoad32;
37 cpu->memory.load16 = GBALoad16;
38 cpu->memory.load8 = GBALoad8;
39 cpu->memory.loadMultiple = GBALoadMultiple;
40 cpu->memory.store32 = GBAStore32;
41 cpu->memory.store16 = GBAStore16;
42 cpu->memory.store8 = GBAStore8;
43 cpu->memory.storeMultiple = GBAStoreMultiple;
44
45 gba->memory.bios = (uint32_t*) hleBios;
46 gba->memory.fullBios = 0;
47 gba->memory.wram = 0;
48 gba->memory.iwram = 0;
49 gba->memory.rom = 0;
50 gba->memory.hw.p = gba;
51
52 int i;
53 for (i = 0; i < 16; ++i) {
54 gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
55 gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
56 gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
57 gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
58 gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
59 gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
60 gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
61 gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
62 }
63 for (; i < 256; ++i) {
64 gba->memory.waitstatesNonseq16[i] = 0;
65 gba->memory.waitstatesSeq16[i] = 0;
66 gba->memory.waitstatesNonseq32[i] = 0;
67 gba->memory.waitstatesSeq32[i] = 0;
68 }
69
70 gba->memory.activeRegion = -1;
71 cpu->memory.activeRegion = 0;
72 cpu->memory.activeMask = 0;
73 cpu->memory.setActiveRegion = GBASetActiveRegion;
74 cpu->memory.activeSeqCycles32 = 0;
75 cpu->memory.activeSeqCycles16 = 0;
76 cpu->memory.activeNonseqCycles32 = 0;
77 cpu->memory.activeNonseqCycles16 = 0;
78 cpu->memory.activeUncachedCycles32 = 0;
79 cpu->memory.activeUncachedCycles16 = 0;
80 gba->memory.biosPrefetch = 0;
81}
82
83void GBAMemoryDeinit(struct GBA* gba) {
84 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
85 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
86 if (gba->memory.rom) {
87 mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
88 }
89 GBASavedataDeinit(&gba->memory.savedata);
90}
91
92void GBAMemoryReset(struct GBA* gba) {
93 if (gba->memory.wram) {
94 mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
95 }
96 gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
97
98 if (gba->memory.iwram) {
99 mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
100 }
101 gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
102
103 memset(gba->memory.io, 0, sizeof(gba->memory.io));
104 memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
105 int i;
106 for (i = 0; i < 4; ++i) {
107 gba->memory.dma[i].count = 0x4000;
108 gba->memory.dma[i].nextEvent = INT_MAX;
109 }
110 gba->memory.dma[3].count = 0x10000;
111 gba->memory.activeDMA = -1;
112 gba->memory.nextDMA = INT_MAX;
113 gba->memory.eventDiff = 0;
114
115 if (!gba->memory.wram || !gba->memory.iwram) {
116 GBAMemoryDeinit(gba);
117 GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
118 }
119}
120
121static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
122 struct ARMInstructionInfo info;
123 uint32_t nextAddress = address;
124 memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
125 if (cpu->executionMode == MODE_THUMB) {
126 while (true) {
127 uint16_t opcode;
128 LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
129 ARMDecodeThumb(opcode, &info);
130 switch (info.branchType) {
131 case ARM_BRANCH_NONE:
132 if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
133 if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
134 gba->idleDetectionStep = -1;
135 return;
136 }
137 uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
138 uint32_t offset = 0;
139 if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
140 offset = info.memory.offset.immediate;
141 } else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
142 int reg = info.memory.offset.reg;
143 if (gba->cachedRegisters[reg]) {
144 gba->idleDetectionStep = -1;
145 return;
146 }
147 offset = gba->cachedRegisters[reg];
148 }
149 if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
150 loadAddress -= offset;
151 } else {
152 loadAddress += offset;
153 }
154 if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
155 gba->idleDetectionStep = -1;
156 return;
157 }
158 if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
159 gba->taintedRegisters[info.op1.reg] = true;
160 } else {
161 switch (info.memory.width) {
162 case 1:
163 gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
164 break;
165 case 2:
166 gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
167 break;
168 case 4:
169 gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
170 break;
171 }
172 }
173 } else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
174 gba->taintedRegisters[info.op1.reg] = true;
175 }
176 nextAddress += WORD_SIZE_THUMB;
177 break;
178 case ARM_BRANCH:
179 if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
180 gba->idleLoop = address;
181 gba->idleOptimization = IDLE_LOOP_REMOVE;
182 }
183 gba->idleDetectionStep = -1;
184 return;
185 default:
186 gba->idleDetectionStep = -1;
187 return;
188 }
189 }
190 } else {
191 gba->idleDetectionStep = -1;
192 }
193}
194
195static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
196 struct GBA* gba = (struct GBA*) cpu->master;
197 struct GBAMemory* memory = &gba->memory;
198
199 int newRegion = address >> BASE_OFFSET;
200 if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
201 if (address == gba->idleLoop) {
202 if (gba->haltPending) {
203 gba->haltPending = false;
204 GBAHalt(gba);
205 } else {
206 gba->haltPending = true;
207 }
208 } else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
209 if (address == gba->lastJump) {
210 switch (gba->idleDetectionStep) {
211 case 0:
212 memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
213 ++gba->idleDetectionStep;
214 break;
215 case 1:
216 if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
217 gba->idleDetectionStep = -1;
218 ++gba->idleDetectionFailures;
219 if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
220 gba->idleOptimization = IDLE_LOOP_IGNORE;
221 }
222 break;
223 }
224 _analyzeForIdleLoop(gba, cpu, address);
225 break;
226 }
227 } else {
228 gba->idleDetectionStep = 0;
229 }
230 }
231 }
232
233 gba->lastJump = address;
234 if (newRegion == memory->activeRegion) {
235 return;
236 }
237
238 if (memory->activeRegion == REGION_BIOS) {
239 memory->biosPrefetch = cpu->prefetch[1];
240 }
241 memory->activeRegion = newRegion;
242 switch (address & ~OFFSET_MASK) {
243 case BASE_BIOS:
244 cpu->memory.activeRegion = memory->bios;
245 cpu->memory.activeMask = SIZE_BIOS - 1;
246 break;
247 case BASE_WORKING_RAM:
248 cpu->memory.activeRegion = memory->wram;
249 cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
250 break;
251 case BASE_WORKING_IRAM:
252 cpu->memory.activeRegion = memory->iwram;
253 cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
254 break;
255 case BASE_VRAM:
256 cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
257 cpu->memory.activeMask = 0x0000FFFF;
258 break;
259 case BASE_CART0:
260 case BASE_CART0_EX:
261 case BASE_CART1:
262 case BASE_CART1_EX:
263 case BASE_CART2:
264 case BASE_CART2_EX:
265 cpu->memory.activeRegion = memory->rom;
266 cpu->memory.activeMask = SIZE_CART0 - 1;
267 break;
268 default:
269 cpu->memory.activeRegion = _deadbeef;
270 cpu->memory.activeMask = 0;
271 GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
272 break;
273 }
274 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
275 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
276 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
277 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
278 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
279 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
280}
281
282#define LOAD_BAD \
283 if (gba->performingDMA) { \
284 value = gba->bus; \
285 } else { \
286 value = cpu->prefetch[1]; \
287 if (cpu->executionMode == MODE_THUMB) { \
288 /* http://ngemu.com/threads/gba-open-bus.170809/ */ \
289 switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
290 case REGION_BIOS: \
291 case REGION_OAM: \
292 /* This isn't right half the time, but we don't have $+6 handy */ \
293 value <<= 16; \
294 value |= cpu->prefetch[0]; \
295 break; \
296 case REGION_WORKING_IRAM: \
297 /* This doesn't handle prefetch clobbering */ \
298 if (cpu->gprs[ARM_PC] & 2) { \
299 value |= cpu->prefetch[0] << 16; \
300 } else { \
301 value <<= 16; \
302 value |= cpu->prefetch[0]; \
303 } \
304 default: \
305 value |= value << 16; \
306 } \
307 } \
308 }
309
310#define LOAD_BIOS \
311 if (address < SIZE_BIOS) { \
312 if (memory->activeRegion == REGION_BIOS) { \
313 LOAD_32(value, address, memory->bios); \
314 } else { \
315 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
316 value = memory->biosPrefetch; \
317 } \
318 } else { \
319 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
320 LOAD_BAD; \
321 }
322
323#define LOAD_WORKING_RAM \
324 LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
325 wait += waitstatesRegion[REGION_WORKING_RAM];
326
327#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
328#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
329
330#define LOAD_PALETTE_RAM \
331 LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
332 ++wait;
333
334#define LOAD_VRAM \
335 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
336 LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
337 } else { \
338 LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
339 } \
340 ++wait;
341
342#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
343
344#define LOAD_CART \
345 wait += waitstatesRegion[address >> BASE_OFFSET]; \
346 if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
347 LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
348 } else { \
349 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
350 value = (address >> 1) & 0xFFFF; \
351 value |= ((address + 2) >> 1) << 16; \
352 }
353
354#define LOAD_SRAM \
355 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
356 value = GBALoad8(cpu, address, 0); \
357 value |= value << 8; \
358 value |= value << 16;
359
360uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
361 struct GBA* gba = (struct GBA*) cpu->master;
362 struct GBAMemory* memory = &gba->memory;
363 uint32_t value = 0;
364 int wait = 0;
365 char* waitstatesRegion = memory->waitstatesNonseq32;
366
367 switch (address >> BASE_OFFSET) {
368 case REGION_BIOS:
369 LOAD_BIOS;
370 break;
371 case REGION_WORKING_RAM:
372 LOAD_WORKING_RAM;
373 break;
374 case REGION_WORKING_IRAM:
375 LOAD_WORKING_IRAM;
376 break;
377 case REGION_IO:
378 LOAD_IO;
379 break;
380 case REGION_PALETTE_RAM:
381 LOAD_PALETTE_RAM;
382 break;
383 case REGION_VRAM:
384 LOAD_VRAM;
385 break;
386 case REGION_OAM:
387 LOAD_OAM;
388 break;
389 case REGION_CART0:
390 case REGION_CART0_EX:
391 case REGION_CART1:
392 case REGION_CART1_EX:
393 case REGION_CART2:
394 case REGION_CART2_EX:
395 LOAD_CART;
396 break;
397 case REGION_CART_SRAM:
398 case REGION_CART_SRAM_MIRROR:
399 LOAD_SRAM;
400 break;
401 default:
402 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
403 LOAD_BAD;
404 break;
405 }
406
407 if (cycleCounter) {
408 *cycleCounter += 1 + wait;
409 }
410 // Unaligned 32-bit loads are "rotated" so they make some semblance of sense
411 int rotate = (address & 3) << 3;
412 return ROR(value, rotate);
413}
414
415uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
416 struct GBA* gba = (struct GBA*) cpu->master;
417 struct GBAMemory* memory = &gba->memory;
418 uint32_t value = 0;
419 int wait = 0;
420
421 switch (address >> BASE_OFFSET) {
422 case REGION_BIOS:
423 if (address < SIZE_BIOS) {
424 if (memory->activeRegion == REGION_BIOS) {
425 LOAD_16(value, address, memory->bios);
426 } else {
427 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
428 LOAD_16(value, address & 2, &memory->biosPrefetch);
429 }
430 } else {
431 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
432 LOAD_BAD;
433 uint32_t v2 = value;
434 LOAD_16(value, address & 2, &v2);
435 }
436 break;
437 case REGION_WORKING_RAM:
438 LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
439 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
440 break;
441 case REGION_WORKING_IRAM:
442 LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
443 break;
444 case REGION_IO:
445 value = GBAIORead(gba, address & (SIZE_IO - 1));
446 break;
447 case REGION_PALETTE_RAM:
448 LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
449 break;
450 case REGION_VRAM:
451 if ((address & 0x0001FFFF) < SIZE_VRAM) {
452 LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
453 } else {
454 LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
455 }
456 break;
457 case REGION_OAM:
458 LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
459 break;
460 case REGION_CART0:
461 case REGION_CART0_EX:
462 case REGION_CART1:
463 case REGION_CART1_EX:
464 case REGION_CART2:
465 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
466 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
467 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
468 } else {
469 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
470 value = (address >> 1) & 0xFFFF; \
471 }
472 break;
473 case REGION_CART2_EX:
474 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
475 if (memory->savedata.type == SAVEDATA_EEPROM) {
476 value = GBASavedataReadEEPROM(&memory->savedata);
477 } else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
478 LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
479 } else {
480 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
481 value = (address >> 1) & 0xFFFF; \
482 }
483 break;
484 case REGION_CART_SRAM:
485 case REGION_CART_SRAM_MIRROR:
486 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
487 value = GBALoad8(cpu, address, 0);
488 value |= value << 8;
489 break;
490 default:
491 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
492 LOAD_BAD;
493 uint32_t v2 = value;
494 LOAD_16(value, address & 2, &v2);
495 break;
496 }
497
498 if (cycleCounter) {
499 *cycleCounter += 1 + wait;
500 }
501 // Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
502 int rotate = (address & 1) << 3;
503 return ROR(value, rotate);
504}
505
506uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
507 struct GBA* gba = (struct GBA*) cpu->master;
508 struct GBAMemory* memory = &gba->memory;
509 uint32_t value = 0;
510 int wait = 0;
511
512 switch (address >> BASE_OFFSET) {
513 case REGION_BIOS:
514 if (address < SIZE_BIOS) {
515 if (memory->activeRegion == REGION_BIOS) {
516 value = ((uint8_t*) memory->bios)[address];
517 } else {
518 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
519 value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
520 }
521 } else {
522 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
523 LOAD_BAD;
524 value = ((uint8_t*) &value)[address & 3];
525 }
526 break;
527 case REGION_WORKING_RAM:
528 value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
529 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
530 break;
531 case REGION_WORKING_IRAM:
532 value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
533 break;
534 case REGION_IO:
535 value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
536 break;
537 case REGION_PALETTE_RAM:
538 value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
539 break;
540 case REGION_VRAM:
541 if ((address & 0x0001FFFF) < SIZE_VRAM) {
542 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
543 } else {
544 value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
545 }
546 break;
547 case REGION_OAM:
548 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
549 break;
550 case REGION_CART0:
551 case REGION_CART0_EX:
552 case REGION_CART1:
553 case REGION_CART1_EX:
554 case REGION_CART2:
555 case REGION_CART2_EX:
556 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
557 if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
558 value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
559 } else {
560 GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
561 value = (address >> 1) & 0xFF; \
562 }
563 break;
564 case REGION_CART_SRAM:
565 case REGION_CART_SRAM_MIRROR:
566 wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
567 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
568 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
569 GBASavedataInitSRAM(&memory->savedata);
570 }
571 if (memory->savedata.type == SAVEDATA_SRAM) {
572 value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
573 } else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
574 value = GBASavedataReadFlash(&memory->savedata, address);
575 } else if (memory->hw.devices & HW_TILT) {
576 value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
577 } else {
578 GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
579 value = 0xFF;
580 }
581 value &= 0xFF;
582 break;
583 default:
584 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
585 LOAD_BAD;
586 value = ((uint8_t*) &value)[address & 3];
587 break;
588 }
589
590 if (cycleCounter) {
591 *cycleCounter += 1 + wait;
592 }
593 return value;
594}
595
596#define STORE_WORKING_RAM \
597 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
598 wait += waitstatesRegion[REGION_WORKING_RAM];
599
600#define STORE_WORKING_IRAM \
601 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
602
603#define STORE_IO \
604 GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
605
606#define STORE_PALETTE_RAM \
607 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
608 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
609 ++wait; \
610 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
611
612#define STORE_VRAM \
613 if ((address & 0x0001FFFF) < SIZE_VRAM) { \
614 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
615 } else { \
616 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
617 } \
618 ++wait;
619
620#define STORE_OAM \
621 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
622 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
623 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
624
625#define STORE_CART \
626 wait += waitstatesRegion[address >> BASE_OFFSET]; \
627 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
628
629#define STORE_SRAM \
630 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
631
632#define STORE_BAD \
633 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
634
635void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
636 struct GBA* gba = (struct GBA*) cpu->master;
637 struct GBAMemory* memory = &gba->memory;
638 int wait = 0;
639 char* waitstatesRegion = memory->waitstatesNonseq32;
640
641 switch (address >> BASE_OFFSET) {
642 case REGION_WORKING_RAM:
643 STORE_WORKING_RAM;
644 break;
645 case REGION_WORKING_IRAM:
646 STORE_WORKING_IRAM
647 break;
648 case REGION_IO:
649 STORE_IO;
650 break;
651 case REGION_PALETTE_RAM:
652 STORE_PALETTE_RAM;
653 break;
654 case REGION_VRAM:
655 STORE_VRAM;
656 break;
657 case REGION_OAM:
658 STORE_OAM;
659 break;
660 case REGION_CART0:
661 case REGION_CART0_EX:
662 case REGION_CART1:
663 case REGION_CART1_EX:
664 case REGION_CART2:
665 case REGION_CART2_EX:
666 STORE_CART;
667 break;
668 case REGION_CART_SRAM:
669 case REGION_CART_SRAM_MIRROR:
670 STORE_SRAM;
671 break;
672 default:
673 STORE_BAD;
674 break;
675 }
676
677 if (cycleCounter) {
678 *cycleCounter += 1 + wait;
679 }
680}
681
682void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
683 struct GBA* gba = (struct GBA*) cpu->master;
684 struct GBAMemory* memory = &gba->memory;
685 int wait = 0;
686
687 switch (address >> BASE_OFFSET) {
688 case REGION_WORKING_RAM:
689 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
690 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
691 break;
692 case REGION_WORKING_IRAM:
693 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
694 break;
695 case REGION_IO:
696 GBAIOWrite(gba, address & (SIZE_IO - 1), value);
697 break;
698 case REGION_PALETTE_RAM:
699 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
700 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
701 break;
702 case REGION_VRAM:
703 if ((address & 0x0001FFFF) < SIZE_VRAM) {
704 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
705 } else {
706 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
707 }
708 break;
709 case REGION_OAM:
710 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
711 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
712 break;
713 case REGION_CART0:
714 if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
715 uint32_t reg = address & 0xFFFFFF;
716 GBAHardwareGPIOWrite(&memory->hw, reg, value);
717 } else {
718 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
719 }
720 break;
721 case REGION_CART2_EX:
722 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
723 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
724 GBASavedataInitEEPROM(&memory->savedata);
725 }
726 GBASavedataWriteEEPROM(&memory->savedata, value, 1);
727 break;
728 case REGION_CART_SRAM:
729 case REGION_CART_SRAM_MIRROR:
730 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
731 break;
732 default:
733 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
734 break;
735 }
736
737 if (cycleCounter) {
738 *cycleCounter += 1 + wait;
739 }
740}
741
742void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
743 struct GBA* gba = (struct GBA*) cpu->master;
744 struct GBAMemory* memory = &gba->memory;
745 int wait = 0;
746
747 switch (address >> BASE_OFFSET) {
748 case REGION_WORKING_RAM:
749 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
750 wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
751 break;
752 case REGION_WORKING_IRAM:
753 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
754 break;
755 case REGION_IO:
756 GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
757 break;
758 case REGION_PALETTE_RAM:
759 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
760 break;
761 case REGION_VRAM:
762 if (address >= 0x06018000) {
763 // TODO: check BG mode
764 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
765 break;
766 }
767 ((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
768 ((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
769 break;
770 case REGION_OAM:
771 GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
772 break;
773 case REGION_CART0:
774 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
775 break;
776 case REGION_CART_SRAM:
777 case REGION_CART_SRAM_MIRROR:
778 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
779 if (address == SAVEDATA_FLASH_BASE) {
780 GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
781 GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
782 } else {
783 GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
784 GBASavedataInitSRAM(&memory->savedata);
785 }
786 }
787 if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
788 GBASavedataWriteFlash(&memory->savedata, address, value);
789 } else if (memory->savedata.type == SAVEDATA_SRAM) {
790 memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
791 } else if (memory->hw.devices & HW_TILT) {
792 GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
793 } else {
794 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
795 }
796 wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
797 break;
798 default:
799 GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
800 break;
801 }
802
803 if (cycleCounter) {
804 *cycleCounter += 1 + wait;
805 }
806}
807
808void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
809 struct GBA* gba = (struct GBA*) cpu->master;
810 struct GBAMemory* memory = &gba->memory;
811 int32_t oldValue = -1;
812
813 switch (address >> BASE_OFFSET) {
814 case REGION_WORKING_RAM:
815 LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
816 STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
817 break;
818 case REGION_WORKING_IRAM:
819 LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
820 STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
821 break;
822 case REGION_IO:
823 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
824 break;
825 case REGION_PALETTE_RAM:
826 LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
827 STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
828 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
829 gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
830 break;
831 case REGION_VRAM:
832 if ((address & 0x0001FFFF) < SIZE_VRAM) {
833 LOAD_32(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
834 STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
835 } else {
836 LOAD_32(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
837 STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
838 }
839 break;
840 case REGION_OAM:
841 LOAD_32(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
842 STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
843 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
844 gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 1)) + 2) >> 1);
845 break;
846 case REGION_CART0:
847 case REGION_CART0_EX:
848 case REGION_CART1:
849 case REGION_CART1_EX:
850 case REGION_CART2:
851 case REGION_CART2_EX:
852 _pristineCow(gba);
853 if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
854 gba->memory.romSize = (address & (SIZE_CART0 - 4)) + 4;
855 }
856 LOAD_32(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
857 STORE_32(value, address & (SIZE_CART0 - 1), gba->memory.rom);
858 break;
859 case REGION_CART_SRAM:
860 case REGION_CART_SRAM_MIRROR:
861 if (memory->savedata.type == SAVEDATA_SRAM) {
862 LOAD_32(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
863 STORE_32(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
864 } else {
865 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
866 }
867 break;
868 default:
869 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
870 break;
871 }
872 if (old) {
873 *old = oldValue;
874 }
875}
876
877void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
878 struct GBA* gba = (struct GBA*) cpu->master;
879 struct GBAMemory* memory = &gba->memory;
880 int16_t oldValue = -1;
881
882 switch (address >> BASE_OFFSET) {
883 case REGION_WORKING_RAM:
884 LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
885 STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
886 break;
887 case REGION_WORKING_IRAM:
888 LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
889 STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
890 break;
891 case REGION_IO:
892 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
893 break;
894 case REGION_PALETTE_RAM:
895 LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
896 STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
897 gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
898 break;
899 case REGION_VRAM:
900 if ((address & 0x0001FFFF) < SIZE_VRAM) {
901 LOAD_16(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
902 STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
903 } else {
904 LOAD_16(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
905 STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
906 }
907 break;
908 case REGION_OAM:
909 LOAD_16(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
910 STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
911 gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
912 break;
913 case REGION_CART0:
914 case REGION_CART0_EX:
915 case REGION_CART1:
916 case REGION_CART1_EX:
917 case REGION_CART2:
918 case REGION_CART2_EX:
919 _pristineCow(gba);
920 if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
921 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
922 }
923 LOAD_16(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
924 STORE_16(value, address & (SIZE_CART0 - 1), gba->memory.rom);
925 break;
926 case REGION_CART_SRAM:
927 case REGION_CART_SRAM_MIRROR:
928 if (memory->savedata.type == SAVEDATA_SRAM) {
929 LOAD_16(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
930 STORE_16(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
931 } else {
932 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
933 }
934 break;
935 default:
936 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
937 break;
938 }
939 if (old) {
940 *old = oldValue;
941 }
942}
943
944void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old) {
945 struct GBA* gba = (struct GBA*) cpu->master;
946 struct GBAMemory* memory = &gba->memory;
947 int8_t oldValue = -1;
948
949 switch (address >> BASE_OFFSET) {
950 case REGION_WORKING_RAM:
951 oldValue = ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
952 ((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
953 break;
954 case REGION_WORKING_IRAM:
955 oldValue = ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
956 ((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
957 break;
958 case REGION_IO:
959 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
960 break;
961 case REGION_PALETTE_RAM:
962 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
963 break;
964 case REGION_VRAM:
965 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
966 break;
967 case REGION_OAM:
968 GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch8: 0x%08X", address);
969 break;
970 case REGION_CART0:
971 case REGION_CART0_EX:
972 case REGION_CART1:
973 case REGION_CART1_EX:
974 case REGION_CART2:
975 case REGION_CART2_EX:
976 _pristineCow(gba);
977 if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
978 gba->memory.romSize = (address & (SIZE_CART0 - 2)) + 2;
979 }
980 oldValue = ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
981 ((int8_t*) memory->rom)[address & (SIZE_CART0 - 1)] = value;
982 break;
983 case REGION_CART_SRAM:
984 case REGION_CART_SRAM_MIRROR:
985 if (memory->savedata.type == SAVEDATA_SRAM) {
986 oldValue = ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)];
987 ((int8_t*) memory->savedata.data)[address & (SIZE_CART_SRAM - 1)] = value;
988 } else {
989 GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
990 }
991 break;
992 default:
993 GBALog(gba, GBA_LOG_WARN, "Bad memory Patch8: 0x%08X", address);
994 break;
995 }
996 if (old) {
997 *old = oldValue;
998 }
999}
1000
1001#define LDM_LOOP(LDM) \
1002 for (i = 0; i < 16; i += 4) { \
1003 if (UNLIKELY(mask & (1 << i))) { \
1004 LDM; \
1005 waitstatesRegion = memory->waitstatesSeq32; \
1006 cpu->gprs[i] = value; \
1007 ++wait; \
1008 address += 4; \
1009 } \
1010 if (UNLIKELY(mask & (2 << i))) { \
1011 LDM; \
1012 waitstatesRegion = memory->waitstatesSeq32; \
1013 cpu->gprs[i + 1] = value; \
1014 ++wait; \
1015 address += 4; \
1016 } \
1017 if (UNLIKELY(mask & (4 << i))) { \
1018 LDM; \
1019 waitstatesRegion = memory->waitstatesSeq32; \
1020 cpu->gprs[i + 2] = value; \
1021 ++wait; \
1022 address += 4; \
1023 } \
1024 if (UNLIKELY(mask & (8 << i))) { \
1025 LDM; \
1026 waitstatesRegion = memory->waitstatesSeq32; \
1027 cpu->gprs[i + 3] = value; \
1028 ++wait; \
1029 address += 4; \
1030 } \
1031 }
1032
1033uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1034 struct GBA* gba = (struct GBA*) cpu->master;
1035 struct GBAMemory* memory = &gba->memory;
1036 uint32_t value;
1037 int wait = 0;
1038 char* waitstatesRegion = memory->waitstatesNonseq32;
1039
1040 int i;
1041 int offset = 4;
1042 int popcount = 0;
1043 if (direction & LSM_D) {
1044 offset = -4;
1045 popcount = _popcount32(mask);
1046 address -= (popcount << 2) - 4;
1047 }
1048
1049 if (direction & LSM_B) {
1050 address += offset;
1051 }
1052
1053 uint32_t addressMisalign = address & 0x3;
1054 address &= 0xFFFFFFFC;
1055
1056 switch (address >> BASE_OFFSET) {
1057 case REGION_BIOS:
1058 LDM_LOOP(LOAD_BIOS);
1059 break;
1060 case REGION_WORKING_RAM:
1061 LDM_LOOP(LOAD_WORKING_RAM);
1062 break;
1063 case REGION_WORKING_IRAM:
1064 LDM_LOOP(LOAD_WORKING_IRAM);
1065 break;
1066 case REGION_IO:
1067 LDM_LOOP(LOAD_IO);
1068 break;
1069 case REGION_PALETTE_RAM:
1070 LDM_LOOP(LOAD_PALETTE_RAM);
1071 break;
1072 case REGION_VRAM:
1073 LDM_LOOP(LOAD_VRAM);
1074 break;
1075 case REGION_OAM:
1076 LDM_LOOP(LOAD_OAM);
1077 break;
1078 case REGION_CART0:
1079 case REGION_CART0_EX:
1080 case REGION_CART1:
1081 case REGION_CART1_EX:
1082 case REGION_CART2:
1083 case REGION_CART2_EX:
1084 LDM_LOOP(LOAD_CART);
1085 break;
1086 case REGION_CART_SRAM:
1087 case REGION_CART_SRAM_MIRROR:
1088 LDM_LOOP(LOAD_SRAM);
1089 break;
1090 default:
1091 LDM_LOOP(LOAD_BAD);
1092 break;
1093 }
1094
1095 if (cycleCounter) {
1096 *cycleCounter += wait;
1097 }
1098
1099 if (direction & LSM_B) {
1100 address -= offset;
1101 }
1102
1103 if (direction & LSM_D) {
1104 address -= (popcount << 2) + 4;
1105 }
1106
1107 return address | addressMisalign;
1108}
1109
1110#define STM_LOOP(STM) \
1111 for (i = 0; i < 16; i += 4) { \
1112 if (UNLIKELY(mask & (1 << i))) { \
1113 value = cpu->gprs[i]; \
1114 STM; \
1115 waitstatesRegion = memory->waitstatesSeq32; \
1116 ++wait; \
1117 address += 4; \
1118 } \
1119 if (UNLIKELY(mask & (2 << i))) { \
1120 value = cpu->gprs[i + 1]; \
1121 STM; \
1122 waitstatesRegion = memory->waitstatesSeq32; \
1123 ++wait; \
1124 address += 4; \
1125 } \
1126 if (UNLIKELY(mask & (4 << i))) { \
1127 value = cpu->gprs[i + 2]; \
1128 STM; \
1129 waitstatesRegion = memory->waitstatesSeq32; \
1130 ++wait; \
1131 address += 4; \
1132 } \
1133 if (UNLIKELY(mask & (8 << i))) { \
1134 value = cpu->gprs[i + 3]; \
1135 STM; \
1136 waitstatesRegion = memory->waitstatesSeq32; \
1137 ++wait; \
1138 address += 4; \
1139 } \
1140 }
1141
1142uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1143 struct GBA* gba = (struct GBA*) cpu->master;
1144 struct GBAMemory* memory = &gba->memory;
1145 uint32_t value;
1146 int wait = 0;
1147 char* waitstatesRegion = memory->waitstatesNonseq32;
1148
1149 int i;
1150 int offset = 4;
1151 int popcount = 0;
1152 if (direction & LSM_D) {
1153 offset = -4;
1154 popcount = _popcount32(mask);
1155 address -= (popcount << 2) - 4;
1156 }
1157
1158 if (direction & LSM_B) {
1159 address += offset;
1160 }
1161
1162 uint32_t addressMisalign = address & 0x3;
1163 address &= 0xFFFFFFFC;
1164
1165 switch (address >> BASE_OFFSET) {
1166 case REGION_WORKING_RAM:
1167 STM_LOOP(STORE_WORKING_RAM);
1168 break;
1169 case REGION_WORKING_IRAM:
1170 STM_LOOP(STORE_WORKING_IRAM);
1171 break;
1172 case REGION_IO:
1173 STM_LOOP(STORE_IO);
1174 break;
1175 case REGION_PALETTE_RAM:
1176 STM_LOOP(STORE_PALETTE_RAM);
1177 break;
1178 case REGION_VRAM:
1179 STM_LOOP(STORE_VRAM);
1180 break;
1181 case REGION_OAM:
1182 STM_LOOP(STORE_OAM);
1183 break;
1184 case REGION_CART0:
1185 case REGION_CART0_EX:
1186 case REGION_CART1:
1187 case REGION_CART1_EX:
1188 case REGION_CART2:
1189 case REGION_CART2_EX:
1190 STM_LOOP(STORE_CART);
1191 break;
1192 case REGION_CART_SRAM:
1193 case REGION_CART_SRAM_MIRROR:
1194 STM_LOOP(STORE_SRAM);
1195 break;
1196 default:
1197 STM_LOOP(STORE_BAD);
1198 break;
1199 }
1200
1201 if (cycleCounter) {
1202 *cycleCounter += wait;
1203 }
1204
1205 if (direction & LSM_B) {
1206 address -= offset;
1207 }
1208
1209 if (direction & LSM_D) {
1210 address -= (popcount << 2) + 4;
1211 }
1212
1213 return address | addressMisalign;
1214}
1215
1216void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1217 struct GBAMemory* memory = &gba->memory;
1218 struct ARMCore* cpu = gba->cpu;
1219 int sram = parameters & 0x0003;
1220 int ws0 = (parameters & 0x000C) >> 2;
1221 int ws0seq = (parameters & 0x0010) >> 4;
1222 int ws1 = (parameters & 0x0060) >> 5;
1223 int ws1seq = (parameters & 0x0080) >> 7;
1224 int ws2 = (parameters & 0x0300) >> 8;
1225 int ws2seq = (parameters & 0x0400) >> 10;
1226 int prefetch = parameters & 0x4000;
1227
1228 memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1229 memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1230 memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1231 memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1232
1233 memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1234 memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1235 memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1236
1237 memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1238 memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1239 memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1240
1241 memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1242 memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1243 memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1244
1245 memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1246 memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1247 memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1248
1249 if (!prefetch) {
1250 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1251 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1252 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1253
1254 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1255 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1256 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1257
1258 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1259 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1260 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1261
1262 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1263 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1264 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1265 } else {
1266 memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1267 memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1268 memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1269
1270 memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1271 memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1272 memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1273
1274 memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1275 memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1276 memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1277
1278 memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1279 memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1280 memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1281 }
1282
1283 cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1284 cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1285
1286 cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1287 cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1288
1289 cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1290 cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1291}
1292
1293void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1294 struct GBAMemory* memory = &gba->memory;
1295 memory->dma[dma].source = address & 0x0FFFFFFE;
1296}
1297
1298void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1299 struct GBAMemory* memory = &gba->memory;
1300 memory->dma[dma].dest = address & 0x0FFFFFFE;
1301}
1302
1303void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1304 struct GBAMemory* memory = &gba->memory;
1305 memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1306}
1307
1308uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1309 struct GBAMemory* memory = &gba->memory;
1310 struct GBADMA* currentDma = &memory->dma[dma];
1311 int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1312 int oldTiming = GBADMARegisterGetTiming(currentDma->reg);
1313 int newTiming = GBADMARegisterGetTiming(control);
1314 // This is probably a huge hack...verify what this does on hardware
1315 if (oldTiming && oldTiming != DMA_TIMING_CUSTOM && oldTiming != newTiming) {
1316 wasEnabled = false;
1317 }
1318 currentDma->reg = control;
1319
1320 if (GBADMARegisterIsDRQ(currentDma->reg)) {
1321 GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1322 }
1323
1324 if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1325 currentDma->nextSource = currentDma->source;
1326 currentDma->nextDest = currentDma->dest;
1327 currentDma->nextCount = currentDma->count;
1328 GBAMemoryScheduleDMA(gba, dma, currentDma);
1329 }
1330 // If the DMA has already occurred, this value might have changed since the function started
1331 return currentDma->reg;
1332};
1333
1334void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1335 struct ARMCore* cpu = gba->cpu;
1336 switch (GBADMARegisterGetTiming(info->reg)) {
1337 case DMA_TIMING_NOW:
1338 info->nextEvent = cpu->cycles;
1339 GBAMemoryUpdateDMAs(gba, 0);
1340 break;
1341 case DMA_TIMING_HBLANK:
1342 // Handled implicitly
1343 info->nextEvent = INT_MAX;
1344 break;
1345 case DMA_TIMING_VBLANK:
1346 // Handled implicitly
1347 info->nextEvent = INT_MAX;
1348 break;
1349 case DMA_TIMING_CUSTOM:
1350 info->nextEvent = INT_MAX;
1351 switch (number) {
1352 case 0:
1353 GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1354 break;
1355 case 1:
1356 case 2:
1357 GBAAudioScheduleFifoDma(&gba->audio, number, info);
1358 break;
1359 case 3:
1360 // GBAVideoScheduleVCaptureDma(dma, info);
1361 break;
1362 }
1363 }
1364}
1365
1366void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1367 struct GBAMemory* memory = &gba->memory;
1368 struct GBADMA* dma;
1369 int i;
1370 for (i = 0; i < 4; ++i) {
1371 dma = &memory->dma[i];
1372 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1373 dma->nextEvent = cycles;
1374 }
1375 }
1376 GBAMemoryUpdateDMAs(gba, 0);
1377}
1378
1379void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1380 struct GBAMemory* memory = &gba->memory;
1381 struct GBADMA* dma;
1382 int i;
1383 for (i = 0; i < 4; ++i) {
1384 dma = &memory->dma[i];
1385 if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1386 dma->nextEvent = cycles;
1387 }
1388 }
1389 GBAMemoryUpdateDMAs(gba, 0);
1390}
1391
1392int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1393 struct GBAMemory* memory = &gba->memory;
1394 if (memory->nextDMA == INT_MAX) {
1395 return INT_MAX;
1396 }
1397 memory->nextDMA -= cycles;
1398 memory->eventDiff += cycles;
1399 if (memory->nextDMA <= 0) {
1400 struct GBADMA* dma = &memory->dma[memory->activeDMA];
1401 GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1402 GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1403 memory->eventDiff = 0;
1404 }
1405 return memory->nextDMA;
1406}
1407
1408void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1409 int i;
1410 struct GBAMemory* memory = &gba->memory;
1411 struct ARMCore* cpu = gba->cpu;
1412 memory->activeDMA = -1;
1413 memory->nextDMA = INT_MAX;
1414 for (i = 3; i >= 0; --i) {
1415 struct GBADMA* dma = &memory->dma[i];
1416 if (dma->nextEvent != INT_MAX) {
1417 dma->nextEvent -= cycles;
1418 if (GBADMARegisterIsEnable(dma->reg)) {
1419 memory->activeDMA = i;
1420 memory->nextDMA = dma->nextEvent;
1421 }
1422 }
1423 }
1424 if (memory->nextDMA < cpu->nextEvent) {
1425 cpu->nextEvent = memory->nextDMA;
1426 }
1427}
1428
1429void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1430 struct GBAMemory* memory = &gba->memory;
1431 struct ARMCore* cpu = gba->cpu;
1432 uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1433 int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1434 int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1435 int32_t wordsRemaining = info->nextCount;
1436 uint32_t source = info->nextSource;
1437 uint32_t dest = info->nextDest;
1438 uint32_t sourceRegion = source >> BASE_OFFSET;
1439 uint32_t destRegion = dest >> BASE_OFFSET;
1440 int32_t cycles = 2;
1441
1442 if (source == info->source) {
1443 // TODO: support 4 cycles for ROM access
1444 cycles += 2;
1445 if (width == 4) {
1446 cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1447 source &= 0xFFFFFFFC;
1448 dest &= 0xFFFFFFFC;
1449 } else {
1450 cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1451 }
1452 } else {
1453 if (width == 4) {
1454 cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1455 } else {
1456 cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1457 }
1458 }
1459
1460 gba->performingDMA = true;
1461 int32_t word;
1462 if (width == 4) {
1463 word = cpu->memory.load32(cpu, source, 0);
1464 gba->bus = word;
1465 cpu->memory.store32(cpu, dest, word, 0);
1466 source += sourceOffset;
1467 dest += destOffset;
1468 --wordsRemaining;
1469 } else {
1470 if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1471 word = GBASavedataReadEEPROM(&memory->savedata);
1472 gba->bus = word | (word << 16);
1473 cpu->memory.store16(cpu, dest, word, 0);
1474 source += sourceOffset;
1475 dest += destOffset;
1476 --wordsRemaining;
1477 } else if (destRegion == REGION_CART2_EX) {
1478 if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1479 GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1480 GBASavedataInitEEPROM(&memory->savedata);
1481 }
1482 word = cpu->memory.load16(cpu, source, 0);
1483 gba->bus = word | (word << 16);
1484 GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1485 source += sourceOffset;
1486 dest += destOffset;
1487 --wordsRemaining;
1488 } else {
1489 word = cpu->memory.load16(cpu, source, 0);
1490 gba->bus = word | (word << 16);
1491 cpu->memory.store16(cpu, dest, word, 0);
1492 source += sourceOffset;
1493 dest += destOffset;
1494 --wordsRemaining;
1495 }
1496 }
1497 gba->performingDMA = false;
1498
1499 if (!wordsRemaining) {
1500 if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1501 info->reg = GBADMARegisterClearEnable(info->reg);
1502 info->nextEvent = INT_MAX;
1503
1504 // Clear the enable bit in memory
1505 memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1506 } else {
1507 info->nextCount = info->count;
1508 if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1509 info->nextDest = info->dest;
1510 }
1511 GBAMemoryScheduleDMA(gba, number, info);
1512 }
1513 if (GBADMARegisterIsDoIRQ(info->reg)) {
1514 GBARaiseIRQ(gba, IRQ_DMA0 + number);
1515 }
1516 } else {
1517 info->nextDest = dest;
1518 info->nextCount = wordsRemaining;
1519 }
1520 info->nextSource = source;
1521
1522 if (info->nextEvent != INT_MAX) {
1523 info->nextEvent += cycles;
1524 }
1525 cpu->cycles += cycles;
1526}
1527
1528void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1529 memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1530 memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1531}
1532
1533void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1534 memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1535 memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1536}
1537
1538uint32_t _popcount32(unsigned bits) {
1539 bits = bits - ((bits >> 1) & 0x55555555);
1540 bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1541 return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1542}
1543
1544void _pristineCow(struct GBA* gba) {
1545 if (gba->memory.rom != gba->pristineRom) {
1546 return;
1547 }
1548 gba->memory.rom = anonymousMemoryMap(SIZE_CART0);
1549 memcpy(gba->memory.rom, gba->pristineRom, gba->memory.romSize);
1550 memset(((uint8_t*) gba->memory.rom) + gba->memory.romSize, 0xFF, SIZE_CART0 - gba->memory.romSize);
1551}