1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_CART_HALFBANK1 = 0x4000,
 26	GB_BASE_CART_HALFBANK2 = 0x6000,
 27	GB_BASE_VRAM = 0x8000,
 28	GB_BASE_EXTERNAL_RAM = 0xA000,
 29	GB_BASE_EXTERNAL_RAM_HALFBANK0 = 0xA000,
 30	GB_BASE_EXTERNAL_RAM_HALFBANK1 = 0xB000,
 31	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 32	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 33	GB_BASE_OAM = 0xFE00,
 34	GB_BASE_UNUSABLE = 0xFEA0,
 35	GB_BASE_IO = 0xFF00,
 36	GB_BASE_HRAM = 0xFF80,
 37	GB_BASE_IE = 0xFFFF
 38};
 39
 40enum {
 41	GB_REGION_CART_BANK0 = 0x0,
 42	GB_REGION_CART_BANK1 = 0x4,
 43	GB_REGION_VRAM = 0x8,
 44	GB_REGION_EXTERNAL_RAM = 0xA,
 45	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 46	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 47	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 48	GB_REGION_OTHER = 0xF,
 49};
 50
 51enum {
 52	GB_SIZE_CART_BANK0 = 0x4000,
 53	GB_SIZE_CART_HALFBANK = 0x2000,
 54	GB_SIZE_CART_MAX = 0x800000,
 55	GB_SIZE_VRAM = 0x4000,
 56	GB_SIZE_VRAM_BANK0 = 0x2000,
 57	GB_SIZE_EXTERNAL_RAM = 0x2000,
 58	GB_SIZE_EXTERNAL_RAM_HALFBANK = 0x1000,
 59	GB_SIZE_WORKING_RAM = 0x8000,
 60	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 61	GB_SIZE_OAM = 0xA0,
 62	GB_SIZE_IO = 0x80,
 63	GB_SIZE_HRAM = 0x7F,
 64
 65	GB_SIZE_MBC6_FLASH = 0x100000,
 66};
 67
 68enum {
 69	GB_SRAM_DIRT_NEW = 1,
 70	GB_SRAM_DIRT_SEEN = 2
 71};
 72
 73struct GBMemory;
 74typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
 75typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
 76
 77DECL_BITFIELD(GBMBC7Field, uint8_t);
 78DECL_BIT(GBMBC7Field, CS, 7);
 79DECL_BIT(GBMBC7Field, CLK, 6);
 80DECL_BIT(GBMBC7Field, DI, 1);
 81DECL_BIT(GBMBC7Field, DO, 0);
 82
 83enum GBMBC7MachineState {
 84	GBMBC7_STATE_IDLE = 0,
 85	GBMBC7_STATE_READ_COMMAND = 1,
 86	GBMBC7_STATE_DO = 2,
 87
 88	GBMBC7_STATE_EEPROM_EWDS = 0x10,
 89	GBMBC7_STATE_EEPROM_WRAL = 0x11,
 90	GBMBC7_STATE_EEPROM_ERAL = 0x12,
 91	GBMBC7_STATE_EEPROM_EWEN = 0x13,
 92	GBMBC7_STATE_EEPROM_WRITE = 0x14,
 93	GBMBC7_STATE_EEPROM_READ = 0x18,
 94	GBMBC7_STATE_EEPROM_ERASE = 0x1C,
 95};
 96
 97enum GBTAMA5Register {
 98	GBTAMA5_BANK_LO = 0x0,
 99	GBTAMA5_BANK_HI = 0x1,
100	GBTAMA5_WRITE_LO = 0x4,
101	GBTAMA5_WRITE_HI = 0x5,
102	GBTAMA5_CS = 0x6,
103	GBTAMA5_ADDR_LO = 0x7,
104	GBTAMA5_MAX = 0x8,
105	GBTAMA5_ACTIVE = 0xA,
106	GBTAMA5_READ_LO = 0xC,
107	GBTAMA5_READ_HI = 0xD,
108};
109
110struct GBMBC1State {
111	int mode;
112	int multicartStride;
113	uint8_t bankLo;
114	uint8_t bankHi;
115};
116
117struct GBMBC6State {
118	int currentBank1;
119	uint8_t* romBank1;
120	bool sramAccess;
121	int currentSramBank1;
122	uint8_t* sramBank1;
123	bool flashBank0;
124	bool flashBank1;
125};
126
127struct GBMBC7State {
128	enum GBMBC7MachineState state;
129	uint16_t sr;
130	uint8_t address;
131	bool writable;
132	int srBits;
133	uint8_t access;
134	uint8_t latch;
135	GBMBC7Field eeprom;
136};
137
138struct GBMMM01State {
139	bool locked;
140	int currentBank0;
141};
142
143struct GBPocketCamState {
144	bool registersActive;
145	uint8_t registers[0x36];
146};
147
148struct GBTAMA5State {
149	uint8_t reg;
150	uint8_t registers[GBTAMA5_MAX];
151};
152
153struct GBPKJDState {
154	uint8_t reg[2];
155};
156
157struct GBBBDState {
158	int dataSwapMode;
159	int bankSwapMode;
160};
161
162union GBMBCState {
163	struct GBMBC1State mbc1;
164	struct GBMBC6State mbc6;
165	struct GBMBC7State mbc7;
166	struct GBMMM01State mmm01;
167	struct GBPocketCamState pocketCam;
168	struct GBTAMA5State tama5;
169	struct GBPKJDState pkjd;
170	struct GBBBDState bbd;
171};
172
173struct mRotationSource;
174struct GBMemory {
175	uint8_t* rom;
176	uint8_t* romBase;
177	uint8_t* romBank;
178	enum GBMemoryBankControllerType mbcType;
179	GBMemoryBankControllerWrite mbcWrite;
180	GBMemoryBankControllerRead mbcRead;
181	union GBMBCState mbcState;
182	int currentBank;
183	int currentBank0;
184
185	uint8_t* wram;
186	uint8_t* wramBank;
187	int wramCurrentBank;
188
189	bool sramAccess;
190	bool directSramAccess;
191	uint8_t* sram;
192	uint8_t* sramBank;
193	int sramCurrentBank;
194
195	uint8_t io[GB_SIZE_IO];
196	bool ime;
197	uint8_t ie;
198
199	uint8_t hram[GB_SIZE_HRAM];
200
201	uint16_t dmaSource;
202	uint16_t dmaDest;
203	int dmaRemaining;
204
205	uint16_t hdmaSource;
206	uint16_t hdmaDest;
207	int hdmaRemaining;
208	bool isHdma;
209
210	struct mTimingEvent dmaEvent;
211	struct mTimingEvent hdmaEvent;
212
213	size_t romSize;
214
215	bool rtcAccess;
216	int activeRtcReg;
217	bool rtcLatched;
218	uint8_t rtcRegs[5];
219	time_t rtcLastLatch;
220	struct mRTCSource* rtc;
221	struct mRotationSource* rotation;
222	struct mRumble* rumble;
223	struct mImageSource* cam;
224};
225
226struct SM83Core;
227void GBMemoryInit(struct GB* gb);
228void GBMemoryDeinit(struct GB* gb);
229
230void GBMemoryReset(struct GB* gb);
231void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
232
233uint8_t GBLoad8(struct SM83Core* cpu, uint16_t address);
234void GBStore8(struct SM83Core* cpu, uint16_t address, int8_t value);
235
236int GBCurrentSegment(struct SM83Core* cpu, uint16_t address);
237
238uint8_t GBView8(struct SM83Core* cpu, uint16_t address, int segment);
239
240void GBMemoryDMA(struct GB* gb, uint16_t base);
241uint8_t GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
242
243void GBPatch8(struct SM83Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
244
245struct GBSerializedState;
246void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
247void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
248
249CXX_GUARD_END
250
251#endif