src/arm/isa-arm.c (view raw)
1/* Copyright (c) 2013-2014 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/arm/isa-arm.h>
7
8#include <mgba/internal/arm/arm.h>
9#include <mgba/internal/arm/emitter-arm.h>
10#include <mgba/internal/arm/isa-inlines.h>
11
12#define PSR_USER_MASK 0xF0000000
13#define PSR_PRIV_MASK 0x000000CF
14#define PSR_STATE_MASK 0x00000020
15
16// Addressing mode 1
17static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
18 int rm = opcode & 0x0000000F;
19 if (opcode & 0x00000010) {
20 int rs = (opcode >> 8) & 0x0000000F;
21 ++cpu->cycles;
22 int32_t shiftVal = cpu->gprs[rm];
23 if (rm == ARM_PC) {
24 shiftVal += 4;
25 }
26 int shift = cpu->gprs[rs] & 0xFF;
27 if (!shift) {
28 cpu->shifterOperand = shiftVal;
29 cpu->shifterCarryOut = cpu->cpsr.c;
30 } else if (shift < 32) {
31 cpu->shifterOperand = shiftVal << shift;
32 cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
33 } else if (shift == 32) {
34 cpu->shifterOperand = 0;
35 cpu->shifterCarryOut = shiftVal & 1;
36 } else {
37 cpu->shifterOperand = 0;
38 cpu->shifterCarryOut = 0;
39 }
40 } else {
41 int immediate = (opcode & 0x00000F80) >> 7;
42 if (!immediate) {
43 cpu->shifterOperand = cpu->gprs[rm];
44 cpu->shifterCarryOut = cpu->cpsr.c;
45 } else {
46 cpu->shifterOperand = cpu->gprs[rm] << immediate;
47 cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
48 }
49 }
50}
51
52static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
53 int rm = opcode & 0x0000000F;
54 if (opcode & 0x00000010) {
55 int rs = (opcode >> 8) & 0x0000000F;
56 ++cpu->cycles;
57 uint32_t shiftVal = cpu->gprs[rm];
58 if (rm == ARM_PC) {
59 shiftVal += 4;
60 }
61 int shift = cpu->gprs[rs] & 0xFF;
62 if (!shift) {
63 cpu->shifterOperand = shiftVal;
64 cpu->shifterCarryOut = cpu->cpsr.c;
65 } else if (shift < 32) {
66 cpu->shifterOperand = shiftVal >> shift;
67 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
68 } else if (shift == 32) {
69 cpu->shifterOperand = 0;
70 cpu->shifterCarryOut = shiftVal >> 31;
71 } else {
72 cpu->shifterOperand = 0;
73 cpu->shifterCarryOut = 0;
74 }
75 } else {
76 int immediate = (opcode & 0x00000F80) >> 7;
77 if (immediate) {
78 cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
79 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
80 } else {
81 cpu->shifterOperand = 0;
82 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
83 }
84 }
85}
86
87static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
88 int rm = opcode & 0x0000000F;
89 if (opcode & 0x00000010) {
90 int rs = (opcode >> 8) & 0x0000000F;
91 ++cpu->cycles;
92 int shiftVal = cpu->gprs[rm];
93 if (rm == ARM_PC) {
94 shiftVal += 4;
95 }
96 int shift = cpu->gprs[rs] & 0xFF;
97 if (!shift) {
98 cpu->shifterOperand = shiftVal;
99 cpu->shifterCarryOut = cpu->cpsr.c;
100 } else if (shift < 32) {
101 cpu->shifterOperand = shiftVal >> shift;
102 cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
103 } else if (cpu->gprs[rm] >> 31) {
104 cpu->shifterOperand = 0xFFFFFFFF;
105 cpu->shifterCarryOut = 1;
106 } else {
107 cpu->shifterOperand = 0;
108 cpu->shifterCarryOut = 0;
109 }
110 } else {
111 int immediate = (opcode & 0x00000F80) >> 7;
112 if (immediate) {
113 cpu->shifterOperand = cpu->gprs[rm] >> immediate;
114 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
115 } else {
116 cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
117 cpu->shifterOperand = cpu->shifterCarryOut;
118 }
119 }
120}
121
122static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
123 int rm = opcode & 0x0000000F;
124 if (opcode & 0x00000010) {
125 int rs = (opcode >> 8) & 0x0000000F;
126 ++cpu->cycles;
127 int shiftVal = cpu->gprs[rm];
128 if (rm == ARM_PC) {
129 shiftVal += 4;
130 }
131 int shift = cpu->gprs[rs] & 0xFF;
132 int rotate = shift & 0x1F;
133 if (!shift) {
134 cpu->shifterOperand = shiftVal;
135 cpu->shifterCarryOut = cpu->cpsr.c;
136 } else if (rotate) {
137 cpu->shifterOperand = ROR(shiftVal, rotate);
138 cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
139 } else {
140 cpu->shifterOperand = shiftVal;
141 cpu->shifterCarryOut = ARM_SIGN(shiftVal);
142 }
143 } else {
144 int immediate = (opcode & 0x00000F80) >> 7;
145 if (immediate) {
146 cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
147 cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
148 } else {
149 // RRX
150 cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
151 cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
152 }
153 }
154}
155
156static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
157 int rotate = (opcode & 0x00000F00) >> 7;
158 int immediate = opcode & 0x000000FF;
159 if (!rotate) {
160 cpu->shifterOperand = immediate;
161 cpu->shifterCarryOut = cpu->cpsr.c;
162 } else {
163 cpu->shifterOperand = ROR(immediate, rotate);
164 cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
165 }
166}
167
168// Instruction definitions
169// Beware pre-processor antics
170
171ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
172 cpu->cpsr.flags = 0;
173 cpu->cpsr.n = ARM_SIGN(d);
174 cpu->cpsr.z = !d;
175 cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
176 cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
177}
178
179ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
180 cpu->cpsr.flags = 0;
181 cpu->cpsr.n = ARM_SIGN(d);
182 cpu->cpsr.z = !d;
183 cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
184 cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
185}
186
187ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
188 cpu->cpsr.n = ARM_SIGN(d);
189 cpu->cpsr.z = !d; \
190 cpu->cpsr.c = cpu->shifterCarryOut; \
191}
192
193#define ARM_ADDITION_S(M, N, D) \
194 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
195 cpu->cpsr = cpu->spsr; \
196 _ARMReadCPSR(cpu); \
197 } else { \
198 _additionS(cpu, M, N, D); \
199 }
200
201#define ARM_SUBTRACTION_S(M, N, D) \
202 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
203 cpu->cpsr = cpu->spsr; \
204 _ARMReadCPSR(cpu); \
205 } else { \
206 _subtractionS(cpu, M, N, D); \
207 }
208
209#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
210 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
211 cpu->cpsr = cpu->spsr; \
212 _ARMReadCPSR(cpu); \
213 } else { \
214 cpu->cpsr.n = ARM_SIGN(D); \
215 cpu->cpsr.z = !(D); \
216 cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
217 cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
218 }
219
220#define ARM_NEUTRAL_S(M, N, D) \
221 if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
222 cpu->cpsr = cpu->spsr; \
223 _ARMReadCPSR(cpu); \
224 } else { \
225 _neutralS(cpu, D); \
226 }
227
228#define ARM_NEUTRAL_HI_S(DLO, DHI) \
229 cpu->cpsr.n = ARM_SIGN(DHI); \
230 cpu->cpsr.z = !((DHI) | (DLO));
231
232#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
233#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
234#define ADDR_MODE_2_ADDRESS (address)
235#define ADDR_MODE_2_RN (cpu->gprs[rn])
236#define ADDR_MODE_2_RM (cpu->gprs[rm])
237#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
238#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
239#define ADDR_MODE_2_WRITEBACK(ADDR) \
240 cpu->gprs[rn] = ADDR; \
241 if (UNLIKELY(rn == ARM_PC)) { \
242 currentCycles += ARMWritePC(cpu); \
243 }
244
245#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
246#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
247#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
248#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
249
250#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
251#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
252#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
253#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
254
255#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
256#define ADDR_MODE_3_RN ADDR_MODE_2_RN
257#define ADDR_MODE_3_RM ADDR_MODE_2_RM
258#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
259#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
260#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
261
262#define ADDR_MODE_4_WRITEBACK_LDM \
263 if (!((1 << rn) & rs)) { \
264 cpu->gprs[rn] = address; \
265 }
266
267#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
268
269#define ARM_LOAD_POST_BODY \
270 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
271 if (rd == ARM_PC) { \
272 currentCycles += ARMWritePC(cpu); \
273 }
274
275#define ARM_STORE_POST_BODY \
276 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
277
278#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
279 static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
280 int currentCycles = ARM_PREFETCH_CYCLES; \
281 BODY; \
282 cpu->cycles += currentCycles; \
283 }
284
285#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
286 DEFINE_INSTRUCTION_ARM(NAME, \
287 SHIFTER(cpu, opcode); \
288 int rd = (opcode >> 12) & 0xF; \
289 int rn = (opcode >> 16) & 0xF; \
290 int32_t n = cpu->gprs[rn]; \
291 if (UNLIKELY(rn == ARM_PC && (opcode & 0x02000010) == 0x00000010)) { \
292 n += WORD_SIZE_ARM; \
293 } \
294 BODY; \
295 S_BODY; \
296 if (rd == ARM_PC) { \
297 if (cpu->executionMode == MODE_ARM) { \
298 currentCycles += ARMWritePC(cpu); \
299 } else { \
300 currentCycles += ThumbWritePC(cpu); \
301 } \
302 })
303
304#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
305 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
306 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
307 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
308 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
309 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
310 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
311 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
312 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
313 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
314 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
315
316#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
317 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
318 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
319 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
320 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
321 DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
322
323#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
324 DEFINE_INSTRUCTION_ARM(NAME, \
325 int rd = (opcode >> 16) & 0xF; \
326 int rs = (opcode >> 8) & 0xF; \
327 int rm = opcode & 0xF; \
328 if (rd != ARM_PC) { \
329 ARM_WAIT_MUL(cpu->gprs[rs], 0); \
330 BODY; \
331 S_BODY; \
332 } \
333 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
334
335#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
336 DEFINE_INSTRUCTION_ARM(NAME, \
337 int rd = (opcode >> 12) & 0xF; \
338 int rdHi = (opcode >> 16) & 0xF; \
339 int rs = (opcode >> 8) & 0xF; \
340 int rm = opcode & 0xF; \
341 if (rdHi != ARM_PC && rd != ARM_PC) { \
342 ARM_WAIT_MUL(cpu->gprs[rs], WAIT); \
343 BODY; \
344 S_BODY; \
345 } \
346 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
347
348#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
349 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
350 DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
351
352#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
353 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
354 DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
355
356#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
357 DEFINE_INSTRUCTION_ARM(NAME, \
358 uint32_t address; \
359 int rn = (opcode >> 16) & 0xF; \
360 int rd = (opcode >> 12) & 0xF; \
361 int32_t d = cpu->gprs[rd]; \
362 if (UNLIKELY(rd == ARM_PC)) { \
363 d += WORD_SIZE_ARM; \
364 } \
365 int rm = opcode & 0xF; \
366 UNUSED(rm); \
367 address = ADDRESS; \
368 ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
369 BODY; \
370 ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
371
372#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
373 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
374 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
375 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
376 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
377 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
378 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
379
380#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
381 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
382 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
383 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
384 DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
385 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
386 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
387 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
388 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
389 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
390 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
391
392#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) \
393 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
394 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
395 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
396 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
397 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
398 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
399 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
400 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
401 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
402 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
403 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
404 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
405
406#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
407 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
408 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
409
410#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
411 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
412 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
413 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
414 DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
415 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
416 DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
417
418#define ARM_MS_PRE_store \
419 enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
420 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
421
422#define ARM_MS_PRE_load \
423 enum PrivilegeMode privilegeMode; \
424 if (!(rs & 0x8000)) { \
425 privilegeMode = cpu->privilegeMode; \
426 ARMSetPrivilegeMode(cpu, MODE_SYSTEM); \
427 }
428
429#define ARM_MS_POST_store ARMSetPrivilegeMode(cpu, privilegeMode);
430
431#define ARM_MS_POST_load \
432 if (!(rs & 0x8000)) { \
433 ARMSetPrivilegeMode(cpu, privilegeMode); \
434 } else if (_ARMModeHasSPSR(cpu->cpsr.priv)) { \
435 cpu->cpsr = cpu->spsr; \
436 _ARMReadCPSR(cpu); \
437 }
438
439#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
440 DEFINE_INSTRUCTION_ARM(NAME, \
441 int rn = (opcode >> 16) & 0xF; \
442 int rs = opcode & 0x0000FFFF; \
443 uint32_t address = cpu->gprs[rn]; \
444 S_PRE; \
445 address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
446 WRITEBACK; \
447 S_POST; \
448 POST_BODY;)
449
450
451#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, POST_BODY) \
452 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
453 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
454 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
455 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
456 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
457 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
458 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
459 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
460 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
461 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DA, POST_BODY) \
462 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
463 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, DB, POST_BODY) \
464 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
465 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IA, POST_BODY) \
466 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY) \
467 DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE_ ## LS, ARM_MS_POST_ ## LS, IB, POST_BODY)
468
469// Begin ALU definitions
470
471DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
472 cpu->gprs[rd] = n + cpu->shifterOperand;)
473
474DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
475 cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
476
477DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
478 cpu->gprs[rd] = n & cpu->shifterOperand;)
479
480DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
481 cpu->gprs[rd] = n & ~cpu->shifterOperand;)
482
483DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(n, cpu->shifterOperand, aluOut),
484 int32_t aluOut = n + cpu->shifterOperand;)
485
486DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(n, cpu->shifterOperand, aluOut),
487 int32_t aluOut = n - cpu->shifterOperand;)
488
489DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
490 cpu->gprs[rd] = n ^ cpu->shifterOperand;)
491
492DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
493 cpu->gprs[rd] = cpu->shifterOperand;)
494
495DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
496 cpu->gprs[rd] = ~cpu->shifterOperand;)
497
498DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
499 cpu->gprs[rd] = n | cpu->shifterOperand;)
500
501DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
502 cpu->gprs[rd] = cpu->shifterOperand - n;)
503
504DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
505 cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
506
507DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
508 cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
509
510DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
511 cpu->gprs[rd] = n - cpu->shifterOperand;)
512
513DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
514 int32_t aluOut = n ^ cpu->shifterOperand;)
515
516DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
517 int32_t aluOut = n & cpu->shifterOperand;)
518
519// End ALU definitions
520
521// Begin multiply definitions
522
523DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 1)
524DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
525
526DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
527 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]) + ((uint32_t) cpu->gprs[rd]);
528 int32_t dHi = cpu->gprs[rdHi] + (d >> 32);
529 cpu->gprs[rd] = d;
530 cpu->gprs[rdHi] = dHi;,
531 ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 2)
532
533DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
534 int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
535 cpu->gprs[rd] = d;
536 cpu->gprs[rdHi] = d >> 32;,
537 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 1)
538
539DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
540 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]) + ((uint32_t) cpu->gprs[rd]);
541 uint32_t dHi = ((uint32_t) cpu->gprs[rdHi]) + (d >> 32);
542 cpu->gprs[rd] = d;
543 cpu->gprs[rdHi] = dHi;,
544 ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 2)
545
546DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
547 uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
548 cpu->gprs[rd] = d;
549 cpu->gprs[rdHi] = d >> 32;,
550 ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 1)
551
552// End multiply definitions
553
554// Begin load/store definitions
555
556DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
557DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
558DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
559DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
560DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
561DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
562DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
563DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, d, ¤tCycles); ARM_STORE_POST_BODY;)
564
565DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
566 enum PrivilegeMode priv = cpu->privilegeMode;
567 ARMSetPrivilegeMode(cpu, MODE_USER);
568 int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
569 ARMSetPrivilegeMode(cpu, priv);
570 cpu->gprs[rd] = r;
571 ARM_LOAD_POST_BODY;)
572
573DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
574 enum PrivilegeMode priv = cpu->privilegeMode;
575 ARMSetPrivilegeMode(cpu, MODE_USER);
576 int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
577 ARMSetPrivilegeMode(cpu, priv);
578 cpu->gprs[rd] = r;
579 ARM_LOAD_POST_BODY;)
580
581DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
582 enum PrivilegeMode priv = cpu->privilegeMode;
583 int32_t r = cpu->gprs[rd];
584 ARMSetPrivilegeMode(cpu, MODE_USER);
585 cpu->memory.store8(cpu, address, r, ¤tCycles);
586 ARMSetPrivilegeMode(cpu, priv);
587 ARM_STORE_POST_BODY;)
588
589DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
590 enum PrivilegeMode priv = cpu->privilegeMode;
591 int32_t r = cpu->gprs[rd];
592 ARMSetPrivilegeMode(cpu, MODE_USER);
593 cpu->memory.store32(cpu, address, r, ¤tCycles);
594 ARMSetPrivilegeMode(cpu, priv);
595 ARM_STORE_POST_BODY;)
596
597DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
598 load,
599 currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
600 if ((rs & 0x8000) || !rs) {
601 if (cpu->executionMode == MODE_THUMB) {
602 currentCycles += ThumbWritePC(cpu);
603 } else {
604 currentCycles += ARMWritePC(cpu);
605 }
606 })
607
608DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
609 store,
610 ARM_STORE_POST_BODY;)
611
612DEFINE_INSTRUCTION_ARM(SWP,
613 int rm = opcode & 0xF;
614 int rd = (opcode >> 12) & 0xF;
615 int rn = (opcode >> 16) & 0xF;
616 int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
617 cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
618 cpu->gprs[rd] = d;)
619
620DEFINE_INSTRUCTION_ARM(SWPB,
621 int rm = opcode & 0xF;
622 int rd = (opcode >> 12) & 0xF;
623 int rn = (opcode >> 16) & 0xF;
624 int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
625 cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
626 cpu->gprs[rd] = d;)
627
628// End load/store definitions
629
630// Begin branch definitions
631
632DEFINE_INSTRUCTION_ARM(B,
633 int32_t offset = opcode << 8;
634 offset >>= 6;
635 cpu->gprs[ARM_PC] += offset;
636 currentCycles += ARMWritePC(cpu);)
637
638DEFINE_INSTRUCTION_ARM(BL,
639 int32_t immediate = (opcode & 0x00FFFFFF) << 8;
640 cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - WORD_SIZE_ARM;
641 cpu->gprs[ARM_PC] += immediate >> 6;
642 currentCycles += ARMWritePC(cpu);)
643
644DEFINE_INSTRUCTION_ARM(BX,
645 int rm = opcode & 0x0000000F;
646 _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
647 cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
648 if (cpu->executionMode == MODE_THUMB) {
649 currentCycles += ThumbWritePC(cpu);
650 } else {
651 currentCycles += ARMWritePC(cpu);
652 })
653
654// End branch definitions
655
656// Begin coprocessor definitions
657
658DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
659DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
660DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
661DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
662DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
663
664// Begin miscellaneous definitions
665
666DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
667DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
668
669DEFINE_INSTRUCTION_ARM(MSR,
670 int c = opcode & 0x00010000;
671 int f = opcode & 0x00080000;
672 int32_t operand = cpu->gprs[opcode & 0x0000000F];
673 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
674 if (mask & PSR_USER_MASK) {
675 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
676 }
677 if (mask & PSR_STATE_MASK) {
678 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
679 }
680 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
681 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
682 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
683 }
684 _ARMReadCPSR(cpu);
685 if (cpu->executionMode == MODE_THUMB) {
686 cpu->prefetch[0] = 0x46C0; // nop
687 cpu->prefetch[1] &= 0xFFFF;
688 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
689 } else {
690 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
691 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
692 })
693
694DEFINE_INSTRUCTION_ARM(MSRR,
695 int c = opcode & 0x00010000;
696 int f = opcode & 0x00080000;
697 int32_t operand = cpu->gprs[opcode & 0x0000000F];
698 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
699 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
700 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
701
702DEFINE_INSTRUCTION_ARM(MRS, \
703 int rd = (opcode >> 12) & 0xF; \
704 cpu->gprs[rd] = cpu->cpsr.packed;)
705
706DEFINE_INSTRUCTION_ARM(MRSR, \
707 int rd = (opcode >> 12) & 0xF; \
708 cpu->gprs[rd] = cpu->spsr.packed;)
709
710DEFINE_INSTRUCTION_ARM(MSRI,
711 int c = opcode & 0x00010000;
712 int f = opcode & 0x00080000;
713 int rotate = (opcode & 0x00000F00) >> 7;
714 int32_t operand = ROR(opcode & 0x000000FF, rotate);
715 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
716 if (mask & PSR_USER_MASK) {
717 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
718 }
719 if (mask & PSR_STATE_MASK) {
720 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
721 }
722 if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
723 ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
724 cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
725 }
726 _ARMReadCPSR(cpu);
727 if (cpu->executionMode == MODE_THUMB) {
728 cpu->prefetch[0] = 0x46C0; // nop
729 cpu->prefetch[1] &= 0xFFFF;
730 cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;
731 } else {
732 LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - WORD_SIZE_ARM) & cpu->memory.activeMask, cpu->memory.activeRegion);
733 LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
734 })
735
736DEFINE_INSTRUCTION_ARM(MSRRI,
737 int c = opcode & 0x00010000;
738 int f = opcode & 0x00080000;
739 int rotate = (opcode & 0x00000F00) >> 7;
740 int32_t operand = ROR(opcode & 0x000000FF, rotate);
741 int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
742 mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
743 cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
744
745DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
746
747const ARMInstruction _armTable[0x1000] = {
748 DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
749};