1/* Copyright (c) 2013-2014 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef ISA_INLINES_H
  7#define ISA_INLINES_H
  8
  9#include "macros.h"
 10
 11#include "arm.h"
 12
 13#define ARM_COND_EQ (cpu->cpsr.z)
 14#define ARM_COND_NE (!cpu->cpsr.z)
 15#define ARM_COND_CS (cpu->cpsr.c)
 16#define ARM_COND_CC (!cpu->cpsr.c)
 17#define ARM_COND_MI (cpu->cpsr.n)
 18#define ARM_COND_PL (!cpu->cpsr.n)
 19#define ARM_COND_VS (cpu->cpsr.v)
 20#define ARM_COND_VC (!cpu->cpsr.v)
 21#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
 22#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
 23#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
 24#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
 25#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
 26#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
 27#define ARM_COND_AL 1
 28
 29#define ARM_SIGN(I) ((I) >> 31)
 30#define ARM_SXT_8(I) (((int8_t) (I) << 24) >> 24)
 31#define ARM_SXT_16(I) (((int16_t) (I) << 16) >> 16)
 32
 33#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
 34#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
 35#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))) && (ARM_SIGN((N) ^ (D))))
 36#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
 37
 38#define ARM_WAIT_MUL(R)                                                   \
 39	{                                                                     \
 40		int32_t wait;                                                     \
 41		if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) {        \
 42			wait = 1;                                                     \
 43		} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
 44			wait = 2;                                                     \
 45		} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
 46			wait = 3;                                                     \
 47		} else {                                                          \
 48			wait = 4;                                                     \
 49		}                                                                 \
 50		currentCycles += cpu->memory.stall(cpu, wait);                    \
 51	}
 52
 53#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
 54#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
 55
 56#define ARM_WRITE_PC                                                                                 \
 57	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM);                                        \
 58	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);                                             \
 59	LOAD_32(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 60	cpu->gprs[ARM_PC] += WORD_SIZE_ARM;                                                              \
 61	LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 62	currentCycles += 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
 63
 64#define THUMB_WRITE_PC                                                                               \
 65	cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB);                                      \
 66	cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);                                             \
 67	LOAD_16(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 68	cpu->gprs[ARM_PC] += WORD_SIZE_THUMB;                                                            \
 69	LOAD_16(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion); \
 70	currentCycles += 2 + cpu->memory.activeNonseqCycles16 + cpu->memory.activeSeqCycles16;
 71
 72static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 73	return mode != MODE_SYSTEM && mode != MODE_USER;
 74}
 75
 76static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
 77	if (executionMode == cpu->executionMode) {
 78		return;
 79	}
 80
 81	cpu->executionMode = executionMode;
 82	switch (executionMode) {
 83	case MODE_ARM:
 84		cpu->cpsr.t = 0;
 85		break;
 86	case MODE_THUMB:
 87		cpu->cpsr.t = 1;
 88	}
 89	cpu->nextEvent = cpu->cycles;
 90}
 91
 92static inline void _ARMReadCPSR(struct ARMCore* cpu) {
 93	_ARMSetMode(cpu, cpu->cpsr.t);
 94	ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
 95	cpu->irqh.readCPSR(cpu);
 96}
 97
 98static inline uint32_t _ARMPCAddress(struct ARMCore* cpu) {
 99	int instructionLength;
100	enum ExecutionMode mode = cpu->cpsr.t;
101	if (mode == MODE_ARM) {
102		instructionLength = WORD_SIZE_ARM;
103	} else {
104		instructionLength = WORD_SIZE_THUMB;
105	}
106	return cpu->gprs[ARM_PC] - instructionLength * 2;
107}
108
109#endif