1/* Copyright (c) 2013-2016 Jeffrey Pfau
  2 *
  3 * This Source Code Form is subject to the terms of the Mozilla Public
  4 * License, v. 2.0. If a copy of the MPL was not distributed with this
  5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
  6#ifndef GB_MEMORY_H
  7#define GB_MEMORY_H
  8
  9#include <mgba-util/common.h>
 10
 11CXX_GUARD_START
 12
 13#include <mgba/core/log.h>
 14#include <mgba/core/timing.h>
 15#include <mgba/gb/interface.h>
 16
 17mLOG_DECLARE_CATEGORY(GB_MBC);
 18mLOG_DECLARE_CATEGORY(GB_MEM);
 19
 20struct GB;
 21
 22enum {
 23	GB_BASE_CART_BANK0 = 0x0000,
 24	GB_BASE_CART_BANK1 = 0x4000,
 25	GB_BASE_VRAM = 0x8000,
 26	GB_BASE_EXTERNAL_RAM = 0xA000,
 27	GB_BASE_WORKING_RAM_BANK0 = 0xC000,
 28	GB_BASE_WORKING_RAM_BANK1 = 0xD000,
 29	GB_BASE_OAM = 0xFE00,
 30	GB_BASE_UNUSABLE = 0xFEA0,
 31	GB_BASE_IO = 0xFF00,
 32	GB_BASE_HRAM = 0xFF80,
 33	GB_BASE_IE = 0xFFFF
 34};
 35
 36enum {
 37	GB_REGION_CART_BANK0 = 0x0,
 38	GB_REGION_CART_BANK1 = 0x4,
 39	GB_REGION_VRAM = 0x8,
 40	GB_REGION_EXTERNAL_RAM = 0xA,
 41	GB_REGION_WORKING_RAM_BANK0 = 0xC,
 42	GB_REGION_WORKING_RAM_BANK1 = 0xD,
 43	GB_REGION_WORKING_RAM_BANK1_MIRROR = 0xE,
 44	GB_REGION_OTHER = 0xF,
 45};
 46
 47enum {
 48	GB_SIZE_CART_BANK0 = 0x4000,
 49	GB_SIZE_CART_MAX = 0x800000,
 50	GB_SIZE_VRAM = 0x4000,
 51	GB_SIZE_VRAM_BANK0 = 0x2000,
 52	GB_SIZE_EXTERNAL_RAM = 0x2000,
 53	GB_SIZE_WORKING_RAM = 0x8000,
 54	GB_SIZE_WORKING_RAM_BANK0 = 0x1000,
 55	GB_SIZE_OAM = 0xA0,
 56	GB_SIZE_IO = 0x80,
 57	GB_SIZE_HRAM = 0x7F,
 58};
 59
 60enum {
 61	GB_SRAM_DIRT_NEW = 1,
 62	GB_SRAM_DIRT_SEEN = 2
 63};
 64
 65struct GBMemory;
 66typedef void (*GBMemoryBankControllerWrite)(struct GB*, uint16_t address, uint8_t value);
 67typedef uint8_t (*GBMemoryBankControllerRead)(struct GBMemory*, uint16_t address);
 68
 69DECL_BITFIELD(GBMBC7Field, uint8_t);
 70DECL_BIT(GBMBC7Field, SK, 6);
 71DECL_BIT(GBMBC7Field, CS, 7);
 72DECL_BIT(GBMBC7Field, IO, 1);
 73
 74enum GBMBC7MachineState {
 75	GBMBC7_STATE_NULL = -1,
 76	GBMBC7_STATE_IDLE = 0,
 77	GBMBC7_STATE_READ_COMMAND = 1,
 78	GBMBC7_STATE_READ_ADDRESS = 2,
 79	GBMBC7_STATE_COMMAND_0 = 3,
 80	GBMBC7_STATE_COMMAND_SR_WRITE = 4,
 81	GBMBC7_STATE_COMMAND_SR_READ = 5,
 82	GBMBC7_STATE_COMMAND_SR_FILL = 6,
 83	GBMBC7_STATE_READ = 7,
 84	GBMBC7_STATE_WRITE = 8,
 85};
 86
 87struct GBMBC1State {
 88	int mode;
 89	int multicartStride;
 90};
 91
 92struct GBMBC7State {
 93	enum GBMBC7MachineState state;
 94	uint32_t sr;
 95	uint8_t address;
 96	bool writable;
 97	int srBits;
 98	int command;
 99	GBMBC7Field field;
100};
101
102struct GBPocketCamState {
103	bool registersActive;
104};
105
106union GBMBCState {
107	struct GBMBC1State mbc1;
108	struct GBMBC7State mbc7;
109	struct GBPocketCamState pocketCam;
110};
111
112struct mRotationSource;
113struct GBMemory {
114	uint8_t* rom;
115	uint8_t* romBase;
116	uint8_t* romBank;
117	enum GBMemoryBankControllerType mbcType;
118	GBMemoryBankControllerWrite mbcWrite;
119	GBMemoryBankControllerRead mbcRead;
120	union GBMBCState mbcState;
121	int currentBank;
122
123	uint8_t* wram;
124	uint8_t* wramBank;
125	int wramCurrentBank;
126
127	bool sramAccess;
128	uint8_t* sram;
129	uint8_t* sramBank;
130	int sramCurrentBank;
131
132	uint8_t io[GB_SIZE_IO];
133	bool ime;
134	uint8_t ie;
135
136	uint8_t hram[GB_SIZE_HRAM];
137
138	uint16_t dmaSource;
139	uint16_t dmaDest;
140	int dmaRemaining;
141
142	uint16_t hdmaSource;
143	uint16_t hdmaDest;
144	int hdmaRemaining;
145	bool isHdma;
146
147	struct mTimingEvent dmaEvent;
148	struct mTimingEvent hdmaEvent;
149
150	size_t romSize;
151
152	bool rtcAccess;
153	int activeRtcReg;
154	bool rtcLatched;
155	uint8_t rtcRegs[5];
156	time_t rtcLastLatch;
157	struct mRTCSource* rtc;
158	struct mRotationSource* rotation;
159	struct mRumble* rumble;
160};
161
162struct LR35902Core;
163void GBMemoryInit(struct GB* gb);
164void GBMemoryDeinit(struct GB* gb);
165
166void GBMemoryReset(struct GB* gb);
167void GBMemorySwitchWramBank(struct GBMemory* memory, int bank);
168
169uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address);
170void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value);
171
172int GBCurrentSegment(struct LR35902Core* cpu, uint16_t address);
173
174uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment);
175
176void GBMemoryDMA(struct GB* gb, uint16_t base);
177void GBMemoryWriteHDMA5(struct GB* gb, uint8_t value);
178
179void GBPatch8(struct LR35902Core* cpu, uint16_t address, int8_t value, int8_t* old, int segment);
180
181struct GBSerializedState;
182void GBMemorySerialize(const struct GB* gb, struct GBSerializedState* state);
183void GBMemoryDeserialize(struct GB* gb, const struct GBSerializedState* state);
184
185CXX_GUARD_END
186
187#endif