src/gb/mbc.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/gb/mbc.h>
7
8#include <mgba/core/interface.h>
9#include <mgba/internal/lr35902/lr35902.h>
10#include <mgba/internal/gb/gb.h>
11#include <mgba/internal/gb/memory.h>
12#include <mgba-util/vfs.h>
13
14mLOG_DEFINE_CATEGORY(GB_MBC, "GB MBC", "gb.mbc");
15
16static void _GBMBCNone(struct GB* gb, uint16_t address, uint8_t value) {
17 UNUSED(gb);
18 UNUSED(address);
19 UNUSED(value);
20
21 mLOG(GB_MBC, GAME_ERROR, "Wrote to invalid MBC");
22}
23
24static void _GBMBC1(struct GB*, uint16_t address, uint8_t value);
25static void _GBMBC2(struct GB*, uint16_t address, uint8_t value);
26static void _GBMBC3(struct GB*, uint16_t address, uint8_t value);
27static void _GBMBC5(struct GB*, uint16_t address, uint8_t value);
28static void _GBMBC6(struct GB*, uint16_t address, uint8_t value);
29static void _GBMBC7(struct GB*, uint16_t address, uint8_t value);
30static void _GBHuC3(struct GB*, uint16_t address, uint8_t value);
31static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value);
32
33static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
34static uint8_t _GBPocketCamRead(struct GBMemory*, uint16_t address);
35
36void GBMBCSwitchBank(struct GB* gb, int bank) {
37 size_t bankStart = bank * GB_SIZE_CART_BANK0;
38 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
39 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
40 bankStart &= (gb->memory.romSize - 1);
41 bank = bankStart / GB_SIZE_CART_BANK0;
42 if (!bank) {
43 ++bank;
44 }
45 }
46 gb->memory.romBank = &gb->memory.rom[bankStart];
47 gb->memory.currentBank = bank;
48 if (gb->cpu->pc < GB_BASE_VRAM) {
49 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
50 }
51}
52
53static void _switchBank0(struct GB* gb, int bank) {
54 size_t bankStart = bank * GB_SIZE_CART_BANK0 << gb->memory.mbcState.mbc1.multicartStride;
55 if (bankStart + GB_SIZE_CART_BANK0 > gb->memory.romSize) {
56 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid ROM bank: %0X", bank);
57 bankStart &= (gb->memory.romSize - 1);
58 }
59 gb->memory.romBase = &gb->memory.rom[bankStart];
60 if (gb->cpu->pc < GB_SIZE_CART_BANK0) {
61 gb->cpu->memory.setActiveRegion(gb->cpu, gb->cpu->pc);
62 }
63}
64
65static bool _isMulticart(const uint8_t* mem) {
66 bool success = true;
67 struct VFile* vf;
68
69 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x10], 1024);
70 success = success && GBIsROM(vf);
71 vf->close(vf);
72
73 vf = VFileFromConstMemory(&mem[GB_SIZE_CART_BANK0 * 0x20], 1024);
74 success = success && GBIsROM(vf);
75 vf->close(vf);
76
77 return success;
78}
79
80void GBMBCSwitchSramBank(struct GB* gb, int bank) {
81 size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM;
82 if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) {
83 mLOG(GB_MBC, GAME_ERROR, "Attempting to switch to an invalid RAM bank: %0X", bank);
84 bankStart &= (gb->sramSize - 1);
85 bank = bankStart / GB_SIZE_EXTERNAL_RAM;
86 }
87 gb->memory.sramBank = &gb->memory.sram[bankStart];
88 gb->memory.sramCurrentBank = bank;
89}
90
91void GBMBCInit(struct GB* gb) {
92 const struct GBCartridge* cart = (const struct GBCartridge*) &gb->memory.rom[0x100];
93 if (gb->memory.rom) {
94 switch (cart->ramSize) {
95 case 0:
96 gb->sramSize = 0;
97 break;
98 case 1:
99 gb->sramSize = 0x800;
100 break;
101 default:
102 case 2:
103 gb->sramSize = 0x2000;
104 break;
105 case 3:
106 gb->sramSize = 0x8000;
107 break;
108 }
109
110 if (gb->memory.mbcType == GB_MBC_AUTODETECT) {
111 switch (cart->type) {
112 case 0:
113 case 8:
114 case 9:
115 gb->memory.mbcType = GB_MBC_NONE;
116 break;
117 case 1:
118 case 2:
119 case 3:
120 gb->memory.mbcType = GB_MBC1;
121 if (gb->memory.romSize >= GB_SIZE_CART_BANK0 * 0x31 && _isMulticart(gb->memory.rom)) {
122 gb->memory.mbcState.mbc1.multicartStride = 4;
123 } else {
124 gb->memory.mbcState.mbc1.multicartStride = 5;
125 }
126 break;
127 case 5:
128 case 6:
129 gb->memory.mbcType = GB_MBC2;
130 break;
131 case 0x0F:
132 case 0x10:
133 gb->memory.mbcType = GB_MBC3_RTC;
134 break;
135 case 0x11:
136 case 0x12:
137 case 0x13:
138 gb->memory.mbcType = GB_MBC3;
139 break;
140 default:
141 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
142 // Fall through
143 case 0x19:
144 case 0x1A:
145 case 0x1B:
146 gb->memory.mbcType = GB_MBC5;
147 break;
148 case 0x1C:
149 case 0x1D:
150 case 0x1E:
151 gb->memory.mbcType = GB_MBC5_RUMBLE;
152 break;
153 case 0x20:
154 gb->memory.mbcType = GB_MBC6;
155 break;
156 case 0x22:
157 gb->memory.mbcType = GB_MBC7;
158 break;
159 case 0xFC:
160 gb->memory.mbcType = GB_POCKETCAM;
161 break;
162 case 0xFD:
163 gb->memory.mbcType = GB_HuC1;
164 break;
165 case 0xFE:
166 gb->memory.mbcType = GB_HuC3;
167 break;
168 }
169 }
170 } else {
171 gb->memory.mbcType = GB_MBC_NONE;
172 }
173 gb->memory.mbcRead = NULL;
174 switch (gb->memory.mbcType) {
175 case GB_MBC_NONE:
176 gb->memory.mbcWrite = _GBMBCNone;
177 break;
178 case GB_MBC1:
179 gb->memory.mbcWrite = _GBMBC1;
180 break;
181 case GB_MBC2:
182 gb->memory.mbcWrite = _GBMBC2;
183 gb->sramSize = 0x200;
184 break;
185 case GB_MBC3:
186 gb->memory.mbcWrite = _GBMBC3;
187 break;
188 default:
189 mLOG(GB_MBC, WARN, "Unknown MBC type: %02X", cart->type);
190 // Fall through
191 case GB_MBC5:
192 gb->memory.mbcWrite = _GBMBC5;
193 break;
194 case GB_MBC6:
195 mLOG(GB_MBC, WARN, "unimplemented MBC: MBC6");
196 gb->memory.mbcWrite = _GBMBC6;
197 break;
198 case GB_MBC7:
199 gb->memory.mbcWrite = _GBMBC7;
200 gb->memory.mbcRead = _GBMBC7Read;
201 gb->sramSize = GB_SIZE_EXTERNAL_RAM;
202 break;
203 case GB_MMM01:
204 mLOG(GB_MBC, WARN, "unimplemented MBC: MMM01");
205 gb->memory.mbcWrite = _GBMBC1;
206 break;
207 case GB_HuC1:
208 mLOG(GB_MBC, WARN, "unimplemented MBC: HuC-1");
209 gb->memory.mbcWrite = _GBMBC1;
210 break;
211 case GB_HuC3:
212 gb->memory.mbcWrite = _GBHuC3;
213 break;
214 case GB_MBC3_RTC:
215 memset(gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
216 gb->memory.mbcWrite = _GBMBC3;
217 break;
218 case GB_MBC5_RUMBLE:
219 gb->memory.mbcWrite = _GBMBC5;
220 break;
221 case GB_POCKETCAM:
222 gb->memory.mbcWrite = _GBPocketCam;
223 gb->memory.mbcRead = _GBPocketCamRead;
224 break;
225 }
226
227 gb->memory.currentBank = 1;
228 gb->memory.sramCurrentBank = 0;
229 gb->memory.sramAccess = false;
230 gb->memory.rtcAccess = false;
231 gb->memory.activeRtcReg = 0;
232 gb->memory.rtcLatched = false;
233 memset(&gb->memory.rtcRegs, 0, sizeof(gb->memory.rtcRegs));
234
235 GBResizeSram(gb, gb->sramSize);
236
237 if (gb->memory.mbcType == GB_MBC3_RTC) {
238 GBMBCRTCRead(gb);
239 }
240}
241
242static void _latchRtc(struct mRTCSource* rtc, uint8_t* rtcRegs, time_t* rtcLastLatch) {
243 time_t t;
244 if (rtc) {
245 if (rtc->sample) {
246 rtc->sample(rtc);
247 }
248 t = rtc->unixTime(rtc);
249 } else {
250 t = time(0);
251 }
252 time_t currentLatch = t;
253 t -= *rtcLastLatch;
254 *rtcLastLatch = currentLatch;
255
256 int64_t diff;
257 diff = rtcRegs[0] + t % 60;
258 if (diff < 0) {
259 diff += 60;
260 t -= 60;
261 }
262 rtcRegs[0] = diff % 60;
263 t /= 60;
264 t += diff / 60;
265
266 diff = rtcRegs[1] + t % 60;
267 if (diff < 0) {
268 diff += 60;
269 t -= 60;
270 }
271 rtcRegs[1] = diff % 60;
272 t /= 60;
273 t += diff / 60;
274
275 diff = rtcRegs[2] + t % 24;
276 if (diff < 0) {
277 diff += 24;
278 t -= 24;
279 }
280 rtcRegs[2] = diff % 24;
281 t /= 24;
282 t += diff / 24;
283
284 diff = rtcRegs[3] + ((rtcRegs[4] & 1) << 8) + (t & 0x1FF);
285 rtcRegs[3] = diff;
286 rtcRegs[4] &= 0xFE;
287 rtcRegs[4] |= (diff >> 8) & 1;
288 if (diff & 0x200) {
289 rtcRegs[4] |= 0x80;
290 }
291}
292
293void _GBMBC1(struct GB* gb, uint16_t address, uint8_t value) {
294 struct GBMemory* memory = &gb->memory;
295 int bank = value & 0x1F;
296 int stride = 1 << memory->mbcState.mbc1.multicartStride;
297 switch (address >> 13) {
298 case 0x0:
299 switch (value) {
300 case 0:
301 memory->sramAccess = false;
302 break;
303 case 0xA:
304 memory->sramAccess = true;
305 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
306 break;
307 default:
308 // TODO
309 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
310 break;
311 }
312 break;
313 case 0x1:
314 if (!bank) {
315 ++bank;
316 }
317 bank &= stride - 1;
318 GBMBCSwitchBank(gb, bank | (memory->currentBank & (3 * stride)));
319 break;
320 case 0x2:
321 bank &= 3;
322 if (memory->mbcState.mbc1.mode) {
323 _switchBank0(gb, bank);
324 GBMBCSwitchSramBank(gb, bank);
325 }
326 GBMBCSwitchBank(gb, (bank << memory->mbcState.mbc1.multicartStride) | (memory->currentBank & (stride - 1)));
327 break;
328 case 0x3:
329 memory->mbcState.mbc1.mode = value & 1;
330 if (memory->mbcState.mbc1.mode) {
331 _switchBank0(gb, memory->currentBank >> memory->mbcState.mbc1.multicartStride);
332 } else {
333 _switchBank0(gb, 0);
334 GBMBCSwitchSramBank(gb, 0);
335 }
336 break;
337 default:
338 // TODO
339 mLOG(GB_MBC, STUB, "MBC1 unknown address: %04X:%02X", address, value);
340 break;
341 }
342}
343
344void _GBMBC2(struct GB* gb, uint16_t address, uint8_t value) {
345 struct GBMemory* memory = &gb->memory;
346 int bank = value & 0xF;
347 switch (address >> 13) {
348 case 0x0:
349 switch (value) {
350 case 0:
351 memory->sramAccess = false;
352 break;
353 case 0xA:
354 memory->sramAccess = true;
355 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
356 break;
357 default:
358 // TODO
359 mLOG(GB_MBC, STUB, "MBC1 unknown value %02X", value);
360 break;
361 }
362 break;
363 case 0x1:
364 if (!bank) {
365 ++bank;
366 }
367 GBMBCSwitchBank(gb, bank);
368 break;
369 default:
370 // TODO
371 mLOG(GB_MBC, STUB, "MBC2 unknown address: %04X:%02X", address, value);
372 break;
373 }
374}
375
376void _GBMBC3(struct GB* gb, uint16_t address, uint8_t value) {
377 struct GBMemory* memory = &gb->memory;
378 int bank = value & 0x7F;
379 switch (address >> 13) {
380 case 0x0:
381 switch (value) {
382 case 0:
383 memory->sramAccess = false;
384 break;
385 case 0xA:
386 memory->sramAccess = true;
387 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
388 break;
389 default:
390 // TODO
391 mLOG(GB_MBC, STUB, "MBC3 unknown value %02X", value);
392 break;
393 }
394 break;
395 case 0x1:
396 if (!bank) {
397 ++bank;
398 }
399 GBMBCSwitchBank(gb, bank);
400 break;
401 case 0x2:
402 if (value < 4) {
403 GBMBCSwitchSramBank(gb, value);
404 memory->rtcAccess = false;
405 } else if (value >= 8 && value <= 0xC) {
406 memory->activeRtcReg = value - 8;
407 memory->rtcAccess = true;
408 }
409 break;
410 case 0x3:
411 if (memory->rtcLatched && value == 0) {
412 memory->rtcLatched = false;
413 } else if (!memory->rtcLatched && value == 1) {
414 _latchRtc(gb->memory.rtc, gb->memory.rtcRegs, &gb->memory.rtcLastLatch);
415 memory->rtcLatched = true;
416 }
417 break;
418 }
419}
420
421void _GBMBC5(struct GB* gb, uint16_t address, uint8_t value) {
422 struct GBMemory* memory = &gb->memory;
423 int bank;
424 switch (address >> 12) {
425 case 0x0:
426 case 0x1:
427 switch (value) {
428 case 0:
429 memory->sramAccess = false;
430 break;
431 case 0xA:
432 memory->sramAccess = true;
433 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
434 break;
435 default:
436 // TODO
437 mLOG(GB_MBC, STUB, "MBC5 unknown value %02X", value);
438 break;
439 }
440 break;
441 case 0x2:
442 bank = (memory->currentBank & 0x100) | value;
443 GBMBCSwitchBank(gb, bank);
444 break;
445 case 0x3:
446 bank = (memory->currentBank & 0xFF) | ((value & 1) << 8);
447 GBMBCSwitchBank(gb, bank);
448 break;
449 case 0x4:
450 case 0x5:
451 if (memory->mbcType == GB_MBC5_RUMBLE && memory->rumble) {
452 memory->rumble->setRumble(memory->rumble, (value >> 3) & 1);
453 value &= ~8;
454 }
455 GBMBCSwitchSramBank(gb, value & 0xF);
456 break;
457 default:
458 // TODO
459 mLOG(GB_MBC, STUB, "MBC5 unknown address: %04X:%02X", address, value);
460 break;
461 }
462}
463
464void _GBMBC6(struct GB* gb, uint16_t address, uint8_t value) {
465 // TODO
466 mLOG(GB_MBC, STUB, "MBC6 unimplemented");
467 UNUSED(gb);
468 UNUSED(address);
469 UNUSED(value);
470}
471
472void _GBMBC7(struct GB* gb, uint16_t address, uint8_t value) {
473 int bank = value & 0x7F;
474 switch (address >> 13) {
475 case 0x1:
476 GBMBCSwitchBank(gb, bank);
477 break;
478 case 0x2:
479 if (value < 0x10) {
480 GBMBCSwitchSramBank(gb, value);
481 }
482 break;
483 default:
484 // TODO
485 mLOG(GB_MBC, STUB, "MBC7 unknown address: %04X:%02X", address, value);
486 break;
487 }
488}
489
490uint8_t _GBMBC7Read(struct GBMemory* memory, uint16_t address) {
491 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
492 switch (address & 0xF0) {
493 case 0x00:
494 case 0x10:
495 case 0x60:
496 case 0x70:
497 return 0;
498 case 0x20:
499 if (memory->rotation && memory->rotation->readTiltX) {
500 int32_t x = -memory->rotation->readTiltX(memory->rotation);
501 x >>= 21;
502 x += 2047;
503 return x;
504 }
505 return 0xFF;
506 case 0x30:
507 if (memory->rotation && memory->rotation->readTiltX) {
508 int32_t x = -memory->rotation->readTiltX(memory->rotation);
509 x >>= 21;
510 x += 2047;
511 return x >> 8;
512 }
513 return 7;
514 case 0x40:
515 if (memory->rotation && memory->rotation->readTiltY) {
516 int32_t y = -memory->rotation->readTiltY(memory->rotation);
517 y >>= 21;
518 y += 2047;
519 return y;
520 }
521 return 0xFF;
522 case 0x50:
523 if (memory->rotation && memory->rotation->readTiltY) {
524 int32_t y = -memory->rotation->readTiltY(memory->rotation);
525 y >>= 21;
526 y += 2047;
527 return y >> 8;
528 }
529 return 7;
530 case 0x80:
531 return (mbc7->sr >> 16) & 1;
532 default:
533 return 0xFF;
534 }
535}
536
537void GBMBC7Write(struct GBMemory* memory, uint16_t address, uint8_t value) {
538 if ((address & 0xF0) != 0x80) {
539 return;
540 }
541 struct GBMBC7State* mbc7 = &memory->mbcState.mbc7;
542 GBMBC7Field old = memory->mbcState.mbc7.field;
543 mbc7->field = GBMBC7FieldClearIO(value);
544 if (!GBMBC7FieldIsCS(old) && GBMBC7FieldIsCS(value)) {
545 if (mbc7->state == GBMBC7_STATE_WRITE) {
546 if (mbc7->writable) {
547 memory->sramBank[mbc7->address * 2] = mbc7->sr >> 8;
548 memory->sramBank[mbc7->address * 2 + 1] = mbc7->sr;
549 }
550 mbc7->sr = 0x1FFFF;
551 mbc7->state = GBMBC7_STATE_NULL;
552 } else {
553 mbc7->state = GBMBC7_STATE_IDLE;
554 }
555 }
556 if (!GBMBC7FieldIsSK(old) && GBMBC7FieldIsSK(value)) {
557 if (mbc7->state > GBMBC7_STATE_IDLE && mbc7->state != GBMBC7_STATE_READ) {
558 mbc7->sr <<= 1;
559 mbc7->sr |= GBMBC7FieldGetIO(value);
560 ++mbc7->srBits;
561 }
562 switch (mbc7->state) {
563 case GBMBC7_STATE_IDLE:
564 if (GBMBC7FieldIsIO(value)) {
565 mbc7->state = GBMBC7_STATE_READ_COMMAND;
566 mbc7->srBits = 0;
567 mbc7->sr = 0;
568 }
569 break;
570 case GBMBC7_STATE_READ_COMMAND:
571 if (mbc7->srBits == 2) {
572 mbc7->state = GBMBC7_STATE_READ_ADDRESS;
573 mbc7->srBits = 0;
574 mbc7->command = mbc7->sr;
575 }
576 break;
577 case GBMBC7_STATE_READ_ADDRESS:
578 if (mbc7->srBits == 8) {
579 mbc7->state = GBMBC7_STATE_COMMAND_0 + mbc7->command;
580 mbc7->srBits = 0;
581 mbc7->address = mbc7->sr;
582 if (mbc7->state == GBMBC7_STATE_COMMAND_0) {
583 switch (mbc7->address >> 6) {
584 case 0:
585 mbc7->writable = false;
586 mbc7->state = GBMBC7_STATE_NULL;
587 break;
588 case 3:
589 mbc7->writable = true;
590 mbc7->state = GBMBC7_STATE_NULL;
591 break;
592 }
593 }
594 }
595 break;
596 case GBMBC7_STATE_COMMAND_0:
597 if (mbc7->srBits == 16) {
598 switch (mbc7->address >> 6) {
599 case 0:
600 mbc7->writable = false;
601 mbc7->state = GBMBC7_STATE_NULL;
602 break;
603 case 1:
604 mbc7->state = GBMBC7_STATE_WRITE;
605 if (mbc7->writable) {
606 int i;
607 for (i = 0; i < 256; ++i) {
608 memory->sramBank[i * 2] = mbc7->sr >> 8;
609 memory->sramBank[i * 2 + 1] = mbc7->sr;
610 }
611 }
612 break;
613 case 2:
614 mbc7->state = GBMBC7_STATE_WRITE;
615 if (mbc7->writable) {
616 int i;
617 for (i = 0; i < 256; ++i) {
618 memory->sramBank[i * 2] = 0xFF;
619 memory->sramBank[i * 2 + 1] = 0xFF;
620 }
621 }
622 break;
623 case 3:
624 mbc7->writable = true;
625 mbc7->state = GBMBC7_STATE_NULL;
626 break;
627 }
628 }
629 break;
630 case GBMBC7_STATE_COMMAND_SR_WRITE:
631 if (mbc7->srBits == 16) {
632 mbc7->srBits = 0;
633 mbc7->state = GBMBC7_STATE_WRITE;
634 }
635 break;
636 case GBMBC7_STATE_COMMAND_SR_READ:
637 if (mbc7->srBits == 1) {
638 mbc7->sr = memory->sramBank[mbc7->address * 2] << 8;
639 mbc7->sr |= memory->sramBank[mbc7->address * 2 + 1];
640 mbc7->srBits = 0;
641 mbc7->state = GBMBC7_STATE_READ;
642 }
643 break;
644 case GBMBC7_STATE_COMMAND_SR_FILL:
645 if (mbc7->srBits == 16) {
646 mbc7->sr = 0xFFFF;
647 mbc7->srBits = 0;
648 mbc7->state = GBMBC7_STATE_WRITE;
649 }
650 break;
651 default:
652 break;
653 }
654 } else if (GBMBC7FieldIsSK(old) && !GBMBC7FieldIsSK(value)) {
655 if (mbc7->state == GBMBC7_STATE_READ) {
656 mbc7->sr <<= 1;
657 ++mbc7->srBits;
658 if (mbc7->srBits == 16) {
659 mbc7->srBits = 0;
660 mbc7->state = GBMBC7_STATE_NULL;
661 }
662 }
663 }
664}
665
666void _GBHuC3(struct GB* gb, uint16_t address, uint8_t value) {
667 struct GBMemory* memory = &gb->memory;
668 int bank = value & 0x3F;
669 if (address & 0x1FFF) {
670 mLOG(GB_MBC, STUB, "HuC-3 unknown value %04X:%02X", address, value);
671 }
672
673 switch (address >> 13) {
674 case 0x0:
675 switch (value) {
676 case 0xA:
677 memory->sramAccess = true;
678 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
679 break;
680 default:
681 memory->sramAccess = false;
682 break;
683 }
684 break;
685 case 0x1:
686 GBMBCSwitchBank(gb, bank);
687 break;
688 case 0x2:
689 GBMBCSwitchSramBank(gb, bank);
690 break;
691 default:
692 // TODO
693 mLOG(GB_MBC, STUB, "HuC-3 unknown address: %04X:%02X", address, value);
694 break;
695 }
696}
697
698void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value) {
699 struct GBMemory* memory = &gb->memory;
700 int bank = value & 0x3F;
701 switch (address >> 13) {
702 case 0x0:
703 switch (value) {
704 case 0:
705 memory->sramAccess = false;
706 break;
707 case 0xA:
708 memory->sramAccess = true;
709 GBMBCSwitchSramBank(gb, memory->sramCurrentBank);
710 break;
711 default:
712 // TODO
713 mLOG(GB_MBC, STUB, "Pocket Cam unknown value %02X", value);
714 break;
715 }
716 break;
717 case 0x1:
718 GBMBCSwitchBank(gb, bank);
719 break;
720 case 0x2:
721 if (value < 0x10) {
722 GBMBCSwitchSramBank(gb, value);
723 memory->mbcState.pocketCam.registersActive = false;
724 } else {
725 memory->mbcState.pocketCam.registersActive = true;
726 }
727 break;
728 default:
729 mLOG(GB_MBC, STUB, "Pocket Cam unknown address: %04X:%02X", address, value);
730 break;
731 }
732}
733
734uint8_t _GBPocketCamRead(struct GBMemory* memory, uint16_t address) {
735 if (memory->mbcState.pocketCam.registersActive) {
736 return 0;
737 }
738 if (!memory->sramAccess) {
739 return 0xFF;
740 }
741 return memory->sramBank[address & (GB_SIZE_EXTERNAL_RAM - 1)];
742}
743
744void GBMBCRTCRead(struct GB* gb) {
745 struct GBMBCRTCSaveBuffer rtcBuffer;
746 struct VFile* vf = gb->sramVf;
747 if (!vf) {
748 return;
749 }
750 ssize_t end = vf->seek(vf, -sizeof(rtcBuffer), SEEK_END);
751 switch (end & 0x1FFF) {
752 case 0:
753 break;
754 case 0x1FFC:
755 vf->seek(vf, -sizeof(rtcBuffer) - 4, SEEK_END);
756 break;
757 default:
758 return;
759 }
760 vf->read(vf, &rtcBuffer, sizeof(rtcBuffer));
761
762 LOAD_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
763 LOAD_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
764 LOAD_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
765 LOAD_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
766 LOAD_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
767 LOAD_64LE(gb->memory.rtcLastLatch, 0, &rtcBuffer.unixTime);
768}
769
770void GBMBCRTCWrite(struct GB* gb) {
771 struct VFile* vf = gb->sramVf;
772 if (!vf) {
773 return;
774 }
775
776 uint8_t rtcRegs[5];
777 memcpy(rtcRegs, gb->memory.rtcRegs, sizeof(rtcRegs));
778 time_t rtcLastLatch = gb->memory.rtcLastLatch;
779 _latchRtc(gb->memory.rtc, rtcRegs, &rtcLastLatch);
780
781 struct GBMBCRTCSaveBuffer rtcBuffer;
782 STORE_32LE(rtcRegs[0], 0, &rtcBuffer.sec);
783 STORE_32LE(rtcRegs[1], 0, &rtcBuffer.min);
784 STORE_32LE(rtcRegs[2], 0, &rtcBuffer.hour);
785 STORE_32LE(rtcRegs[3], 0, &rtcBuffer.days);
786 STORE_32LE(rtcRegs[4], 0, &rtcBuffer.daysHi);
787 STORE_32LE(gb->memory.rtcRegs[0], 0, &rtcBuffer.latchedSec);
788 STORE_32LE(gb->memory.rtcRegs[1], 0, &rtcBuffer.latchedMin);
789 STORE_32LE(gb->memory.rtcRegs[2], 0, &rtcBuffer.latchedHour);
790 STORE_32LE(gb->memory.rtcRegs[3], 0, &rtcBuffer.latchedDays);
791 STORE_32LE(gb->memory.rtcRegs[4], 0, &rtcBuffer.latchedDaysHi);
792 STORE_64LE(rtcLastLatch, 0, &rtcBuffer.unixTime);
793
794 if (vf->size(vf) == gb->sramSize) {
795 // Writing past the end of the file can invalidate the file mapping
796 vf->unmap(vf, gb->memory.sram, gb->sramSize);
797 gb->memory.sram = NULL;
798 }
799 vf->seek(vf, gb->sramSize, SEEK_SET);
800 vf->write(vf, &rtcBuffer, sizeof(rtcBuffer));
801 if (!gb->memory.sram) {
802 gb->memory.sram = vf->map(vf, gb->sramSize, MAP_WRITE);
803 GBMBCSwitchSramBank(gb, gb->memory.sramCurrentBank);
804 }
805}