src/arm/decoder-arm.c (view raw)
1#include "decoder.h"
2
3#include "arm.h"
4#include "decoder-inlines.h"
5#include "emitter-arm.h"
6#include "isa-inlines.h"
7
8#include <stdio.h>
9#include <string.h>
10
11#define ADDR_MODE_1_SHIFT(OP) \
12 info->op3.reg = opcode & 0x0000000F; \
13 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
14 info->op3.shifterImm = (opcode >> 7) & 0x1F; \
15 info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
16 ARM_OPERAND_SHIFT_IMMEDIATE_3;
17
18#define ADDR_MODE_1_SHIFTR(OP) \
19 info->op3.reg = opcode & 0x0000000F; \
20 info->op3.shifterOp = ARM_SHIFT_ ## OP; \
21 info->op3.shifterReg = (opcode >> 8) & 0xF; \
22 ++info->iCycles; \
23 info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
24 ARM_OPERAND_SHIFT_REGISTER_3;
25
26#define ADDR_MODE_1_LSL \
27 ADDR_MODE_1_SHIFT(LSL) \
28 if (!info->op3.shifterImm) { \
29 info->operandFormat &= ~ARM_OPERAND_SHIFT_REGISTER_3; \
30 info->op3.shifterOp = ARM_SHIFT_NONE; \
31 }
32
33#define ADDR_MODE_1_LSR ADDR_MODE_1_SHIFT(LSR)
34#define ADDR_MODE_1_ASR ADDR_MODE_1_SHIFT(ASR)
35#define ADDR_MODE_1_ROR \
36 ADDR_MODE_1_SHIFT(ROR) \
37 if (!info->op3.shifterImm) { \
38 info->op3.shifterOp = ARM_SHIFT_RRX; \
39 }
40
41#define ADDR_MODE_1_LSLR ADDR_MODE_1_SHIFTR(LSL)
42#define ADDR_MODE_1_LSRR ADDR_MODE_1_SHIFTR(LSR)
43#define ADDR_MODE_1_ASRR ADDR_MODE_1_SHIFTR(ASR)
44#define ADDR_MODE_1_RORR ADDR_MODE_1_SHIFTR(ROR)
45
46#define ADDR_MODE_1_IMM \
47 int rotate = (opcode & 0x00000F00) >> 7; \
48 int immediate = opcode & 0x000000FF; \
49 info->op3.immediate = ARM_ROR(immediate, rotate); \
50 info->operandFormat |= ARM_OPERAND_IMMEDIATE_3;
51
52#define ADDR_MODE_2_SHIFT(OP) \
53 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET | ARM_MEMORY_SHIFTED_OFFSET; \
54 info->memory.offset.shifterOp = ARM_SHIFT_ ## OP; \
55 info->memory.offset.shifterImm = (opcode >> 7) & 0x1F; \
56 info->memory.offset.reg = opcode & 0x0000000F;
57
58#define ADDR_MODE_2_LSL \
59 ADDR_MODE_2_SHIFT(LSL) \
60 if (!info->memory.offset.shifterImm) { \
61 info->memory.format &= ~ARM_MEMORY_SHIFTED_OFFSET; \
62 info->memory.offset.shifterOp = ARM_SHIFT_NONE; \
63 }
64
65#define ADDR_MODE_2_LSR ADDR_MODE_2_SHIFT(LSR) \
66 if (!info->memory.offset.shifterImm) { \
67 info->memory.offset.shifterImm = 32; \
68 }
69
70#define ADDR_MODE_2_ASR ADDR_MODE_2_SHIFT(ASR) \
71 if (!info->memory.offset.shifterImm) { \
72 info->memory.offset.shifterImm = 32; \
73 }
74
75#define ADDR_MODE_2_ROR \
76 ADDR_MODE_2_SHIFT(ROR) \
77 if (!info->memory.offset.shifterImm) { \
78 info->memory.offset.shifterOp = ARM_SHIFT_RRX; \
79 }
80
81#define ADDR_MODE_2_IMM \
82 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
83 info->memory.offset.immediate = opcode & 0x00000FFF;
84
85#define ADDR_MODE_3_REG \
86 info->memory.format |= ARM_MEMORY_REGISTER_OFFSET; \
87 info->memory.offset.reg = opcode & 0x0000000F;
88
89#define ADDR_MODE_3_IMM \
90 info->memory.format |= ARM_MEMORY_IMMEDIATE_OFFSET; \
91 info->memory.offset.immediate = (opcode & 0x0000000F) | ((opcode & 0x00000F00) >> 4);
92
93#define DEFINE_DECODER_ARM(NAME, MNEMONIC, BODY) \
94 static void _ARMDecode ## NAME (uint32_t opcode, struct ARMInstructionInfo* info) { \
95 UNUSED(opcode); \
96 info->mnemonic = ARM_MN_ ## MNEMONIC; \
97 BODY; \
98 }
99
100#define DEFINE_ALU_DECODER_EX_ARM(NAME, MNEMONIC, S, SHIFTER, OTHER_AFFECTED) \
101 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
102 info->op1.reg = (opcode >> 12) & 0xF; \
103 info->op2.reg = (opcode >> 16) & 0xF; \
104 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
105 OTHER_AFFECTED | \
106 ARM_OPERAND_REGISTER_2; \
107 info->affectsCPSR = S; \
108 SHIFTER; \
109 if (info->op1.reg == ARM_PC) { \
110 info->branches = 1; \
111 })
112
113#define DEFINE_ALU_DECODER_ARM(NAME) \
114 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1) \
115 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1) \
116 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 0, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1) \
117 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1) \
118 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1) \
119 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1) \
120 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 0, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1) \
121 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1) \
122 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1) \
123 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1) \
124 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 0, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1) \
125 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1) \
126 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1) \
127 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1) \
128 DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 0, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1) \
129 DEFINE_ALU_DECODER_EX_ARM(NAME ## S_RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1) \
130 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1) \
131 DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1)
132
133#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
134 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE) \
135 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_NONE) \
136 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE) \
137 DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_NONE) \
138 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE) \
139 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_NONE) \
140 DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE) \
141 DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_NONE) \
142 DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE)
143
144#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
145 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
146 info->op1.reg = (opcode >> 16) & 0xF; \
147 info->op2.reg = opcode & 0xF; \
148 info->op3.reg = (opcode >> 8) & 0xF; \
149 info->op4.reg = (opcode >> 12) & 0xF; \
150 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
151 ARM_OPERAND_AFFECTED_1 | \
152 ARM_OPERAND_REGISTER_2 | \
153 ARM_OPERAND_REGISTER_3 | \
154 OTHER_AFFECTED; \
155 info->affectsCPSR = S; \
156 if (info->op1.reg == ARM_PC) { \
157 info->branches = 1; \
158 })
159
160#define DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S) \
161 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
162 info->op1.reg = (opcode >> 12) & 0xF; \
163 info->op2.reg = (opcode >> 16) & 0xF; \
164 info->op3.reg = opcode & 0xF; \
165 info->op4.reg = (opcode >> 8) & 0xF; \
166 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
167 ARM_OPERAND_AFFECTED_1 | \
168 ARM_OPERAND_REGISTER_2 | \
169 ARM_OPERAND_AFFECTED_2 | \
170 ARM_OPERAND_REGISTER_3 | \
171 ARM_OPERAND_REGISTER_4; \
172 info->affectsCPSR = S; \
173 if (info->op1.reg == ARM_PC) { \
174 info->branches = 1; \
175 })
176
177#define DEFINE_MULTIPLY_DECODER_ARM(NAME, OTHER_AFFECTED) \
178 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0, OTHER_AFFECTED) \
179 DEFINE_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1, OTHER_AFFECTED)
180
181#define DEFINE_LONG_MULTIPLY_DECODER_ARM(NAME) \
182 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME, NAME, 0) \
183 DEFINE_LONG_MULTIPLY_DECODER_EX_ARM(NAME ## S, NAME, 1)
184
185#define DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, ADDRESSING_MODE, ADDRESSING_DECODING, CYCLES, TYPE) \
186 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
187 info->op1.reg = (opcode >> 12) & 0xF; \
188 info->memory.baseReg = (opcode >> 16) & 0xF; \
189 info->memory.width = TYPE; \
190 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
191 ARM_OPERAND_AFFECTED_1 | /* TODO: Remove this for STR */ \
192 ARM_OPERAND_MEMORY_2; \
193 info->memory.format = ARM_MEMORY_REGISTER_BASE | ADDRESSING_MODE; \
194 ADDRESSING_DECODING; \
195 CYCLES;)
196
197#define DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
198 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
199 ARM_MEMORY_POST_INCREMENT | \
200 ARM_MEMORY_WRITEBACK | \
201 ARM_MEMORY_OFFSET_SUBTRACT, \
202 ADDRESSING_MODE, CYCLES, TYPE) \
203 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
204 ARM_MEMORY_POST_INCREMENT | \
205 ARM_MEMORY_WRITEBACK, \
206 ADDRESSING_MODE, CYCLES, TYPE) \
207 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## P, MNEMONIC, \
208 ARM_MEMORY_PRE_INCREMENT | \
209 ARM_MEMORY_OFFSET_SUBTRACT, \
210 ADDRESSING_MODE, CYCLES, TYPE) \
211 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PW, MNEMONIC, \
212 ARM_MEMORY_PRE_INCREMENT | \
213 ARM_MEMORY_WRITEBACK | \
214 ARM_MEMORY_OFFSET_SUBTRACT, \
215 ADDRESSING_MODE, CYCLES, TYPE) \
216 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PU, MNEMONIC, \
217 ARM_MEMORY_PRE_INCREMENT, \
218 ADDRESSING_MODE, CYCLES, TYPE) \
219 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## PUW, MNEMONIC, \
220 ARM_MEMORY_PRE_INCREMENT | \
221 ARM_MEMORY_WRITEBACK, \
222 ADDRESSING_MODE, CYCLES, TYPE)
223
224#define DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
225 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
226 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
227 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
228 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
229 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
230
231#define DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
232 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME, MNEMONIC, ADDR_MODE_3_REG, CYCLES, TYPE) \
233 DEFINE_LOAD_STORE_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_3_IMM, CYCLES, TYPE)
234
235#define DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME, MNEMONIC, ADDRESSING_MODE, CYCLES, TYPE) \
236 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME, MNEMONIC, \
237 ARM_MEMORY_POST_INCREMENT | \
238 ARM_MEMORY_OFFSET_SUBTRACT, \
239 ADDRESSING_MODE, CYCLES, TYPE) \
240 DEFINE_LOAD_STORE_DECODER_EX_ARM(NAME ## U, MNEMONIC, \
241 ARM_MEMORY_POST_INCREMENT, \
242 ADDRESSING_MODE, CYCLES, TYPE)
243
244#define DEFINE_LOAD_STORE_T_DECODER_ARM(NAME, MNEMONIC, CYCLES, TYPE) \
245 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSL_, MNEMONIC, ADDR_MODE_2_LSL, CYCLES, TYPE) \
246 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _LSR_, MNEMONIC, ADDR_MODE_2_LSR, CYCLES, TYPE) \
247 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ASR_, MNEMONIC, ADDR_MODE_2_ASR, CYCLES, TYPE) \
248 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## _ROR_, MNEMONIC, ADDR_MODE_2_ROR, CYCLES, TYPE) \
249 DEFINE_LOAD_STORE_T_DECODER_SET_ARM(NAME ## I, MNEMONIC, ADDR_MODE_2_IMM, CYCLES, TYPE)
250
251#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME, MNEMONIC, DIRECTION, WRITEBACK) \
252 DEFINE_DECODER_ARM(NAME, MNEMONIC, \
253 info->memory.baseReg = (opcode >> 16) & 0xF; \
254 info->op1.immediate = opcode & 0x0000FFFF; \
255 info->branches = info->op1.immediate & (1 << ARM_PC); \
256 info->operandFormat = ARM_OPERAND_MEMORY_1; \
257 info->memory.format = ARM_MEMORY_REGISTER_BASE | \
258 ARM_MEMORY_WRITEBACK | \
259 ARM_MEMORY_ ## DIRECTION;)
260
261
262#define DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(NAME) \
263 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DA, NAME, DECREMENT_AFTER, 0) \
264 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
265 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DB, NAME, DECREMENT_BEFORE, 0) \
266 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## DBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
267 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IA, NAME, INCREMENT_AFTER, 0) \
268 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
269 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, 0) \
270 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
271 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, 0) \
272 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
273 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, 0) \
274 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
275 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, 0) \
276 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
277 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, 0) \
278 DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK)
279
280#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
281 DEFINE_DECODER_ARM(NAME, SWP, \
282 info->memory.baseReg = (opcode >> 16) & 0xF; \
283 info->op1.reg = (opcode >> 12) & 0xF; \
284 info->op2.reg = opcode & 0xF; \
285 info->operandFormat = ARM_OPERAND_REGISTER_1 | \
286 ARM_OPERAND_AFFECTED_1 | \
287 ARM_OPERAND_REGISTER_2 | \
288 ARM_OPERAND_MEMORY_3; \
289 info->memory.format = ARM_MEMORY_REGISTER_BASE; \
290 info->memory.width = TYPE;)
291
292DEFINE_ALU_DECODER_ARM(ADD)
293DEFINE_ALU_DECODER_ARM(ADC)
294DEFINE_ALU_DECODER_ARM(AND)
295DEFINE_ALU_DECODER_ARM(BIC)
296DEFINE_ALU_DECODER_S_ONLY_ARM(CMN)
297DEFINE_ALU_DECODER_S_ONLY_ARM(CMP)
298DEFINE_ALU_DECODER_ARM(EOR)
299DEFINE_ALU_DECODER_ARM(MOV)
300DEFINE_ALU_DECODER_ARM(MVN)
301DEFINE_ALU_DECODER_ARM(ORR)
302DEFINE_ALU_DECODER_ARM(RSB)
303DEFINE_ALU_DECODER_ARM(RSC)
304DEFINE_ALU_DECODER_ARM(SBC)
305DEFINE_ALU_DECODER_ARM(SUB)
306DEFINE_ALU_DECODER_S_ONLY_ARM(TEQ)
307DEFINE_ALU_DECODER_S_ONLY_ARM(TST)
308
309// TOOD: Estimate cycles
310DEFINE_MULTIPLY_DECODER_ARM(MLA, ARM_OPERAND_REGISTER_4)
311DEFINE_MULTIPLY_DECODER_ARM(MUL, ARM_OPERAND_NONE)
312
313DEFINE_LONG_MULTIPLY_DECODER_ARM(SMLAL)
314DEFINE_LONG_MULTIPLY_DECODER_ARM(SMULL)
315DEFINE_LONG_MULTIPLY_DECODER_ARM(UMLAL)
316DEFINE_LONG_MULTIPLY_DECODER_ARM(UMULL)
317
318// Begin load/store definitions
319
320DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDR, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
321DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(LDRB, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
322DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRH, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
323DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSB, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_BYTE)
324DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(LDRSH, LDR, LOAD_CYCLES, ARM_ACCESS_SIGNED_HALFWORD)
325DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STR, STR, STORE_CYCLES, ARM_ACCESS_WORD)
326DEFINE_LOAD_STORE_MODE_2_DECODER_ARM(STRB, STR, STORE_CYCLES, ARM_ACCESS_BYTE)
327DEFINE_LOAD_STORE_MODE_3_DECODER_ARM(STRH, STR, STORE_CYCLES, ARM_ACCESS_HALFWORD)
328
329DEFINE_LOAD_STORE_T_DECODER_ARM(LDRBT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
330DEFINE_LOAD_STORE_T_DECODER_ARM(LDRT, LDR, LOAD_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
331DEFINE_LOAD_STORE_T_DECODER_ARM(STRBT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_BYTE)
332DEFINE_LOAD_STORE_T_DECODER_ARM(STRT, STR, STORE_CYCLES, ARM_ACCESS_TRANSLATED_WORD)
333
334DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(LDM)
335DEFINE_LOAD_STORE_MULTIPLE_DECODER_ARM(STM)
336
337DEFINE_SWP_DECODER_ARM(SWP, ARM_ACCESS_WORD)
338DEFINE_SWP_DECODER_ARM(SWPB, ARM_ACCESS_BYTE)
339
340// End load/store definitions
341
342// Begin branch definitions
343
344DEFINE_DECODER_ARM(B, B,
345 int32_t offset = opcode << 8;
346 info->op1.immediate = offset >> 6;
347 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
348 info->branches = 1;)
349
350DEFINE_DECODER_ARM(BL, BL,
351 int32_t offset = opcode << 8;
352 info->op1.immediate = offset >> 6;
353 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
354 info->branches = 1;)
355
356DEFINE_DECODER_ARM(BX, BX,
357 info->op1.reg = opcode & 0x0000000F;
358 info->operandFormat = ARM_OPERAND_REGISTER_1;
359 info->branches = 1;)
360
361// End branch definitions
362
363// Begin coprocessor definitions
364
365DEFINE_DECODER_ARM(CDP, ILL, info->operandFormat = ARM_OPERAND_NONE;)
366DEFINE_DECODER_ARM(LDC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
367DEFINE_DECODER_ARM(STC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
368DEFINE_DECODER_ARM(MCR, ILL, info->operandFormat = ARM_OPERAND_NONE;)
369DEFINE_DECODER_ARM(MRC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
370
371// Begin miscellaneous definitions
372
373DEFINE_DECODER_ARM(BKPT, BKPT, info->operandFormat = ARM_OPERAND_NONE;) // Not strictly in ARMv4T, but here for convenience
374DEFINE_DECODER_ARM(ILL, ILL, info->operandFormat = ARM_OPERAND_NONE;) // Illegal opcode
375
376DEFINE_DECODER_ARM(MSR, MSR,
377 info->affectsCPSR = 1;
378 info->op1.reg = ARM_CPSR;
379 info->op2.reg = opcode & 0x0000000F;
380 info->operandFormat = ARM_OPERAND_REGISTER_1 |
381 ARM_OPERAND_AFFECTED_1 |
382 ARM_OPERAND_REGISTER_2;)
383
384DEFINE_DECODER_ARM(MSRR, MSR,
385 info->op1.reg = ARM_SPSR;
386 info->op2.reg = opcode & 0x0000000F;
387 info->operandFormat = ARM_OPERAND_REGISTER_1 |
388 ARM_OPERAND_AFFECTED_1 |
389 ARM_OPERAND_REGISTER_2;)
390
391DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
392 info->affectsCPSR = 1;
393 info->op1.reg = (opcode >> 12) & 0xF;
394 info->op2.reg = ARM_CPSR;
395 info->operandFormat = ARM_OPERAND_REGISTER_1 |
396 ARM_OPERAND_AFFECTED_1 |
397 ARM_OPERAND_REGISTER_2;)
398
399DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
400 info->affectsCPSR = 1;
401 info->op1.reg = (opcode >> 12) & 0xF;
402 info->op2.reg = ARM_SPSR;
403 info->operandFormat = ARM_OPERAND_REGISTER_1 |
404 ARM_OPERAND_AFFECTED_1 |
405 ARM_OPERAND_REGISTER_2;)
406
407DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;
408 int rotate = (opcode & 0x00000F00) >> 7;
409 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
410 info->affectsCPSR = 1;
411 info->op1.reg = ARM_CPSR;
412 info->op2.immediate = operand;
413 info->operandFormat = ARM_OPERAND_REGISTER_1 |
414 ARM_OPERAND_AFFECTED_1 |
415 ARM_OPERAND_IMMEDIATE_2;)
416
417DEFINE_DECODER_ARM(MSRRI, MSR, info->affectsCPSR = 1;
418 int rotate = (opcode & 0x00000F00) >> 7;
419 int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
420 info->affectsCPSR = 1;
421 info->op1.reg = ARM_SPSR;
422 info->op2.immediate = operand;
423 info->operandFormat = ARM_OPERAND_REGISTER_1 |
424 ARM_OPERAND_AFFECTED_1 |
425 ARM_OPERAND_IMMEDIATE_2;)
426
427DEFINE_DECODER_ARM(SWI, SWI,
428 info->op1.immediate = opcode & 0xFFFFFF;
429 info->operandFormat = ARM_OPERAND_IMMEDIATE_1;
430 info->traps = 1;)
431
432typedef void (*ARMDecoder)(uint32_t opcode, struct ARMInstructionInfo* info);
433
434static const ARMDecoder _armDecoderTable[0x1000] = {
435 DECLARE_ARM_EMITTER_BLOCK(_ARMDecode)
436};
437
438void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info) {
439 info->execMode = MODE_ARM;
440 info->opcode = opcode;
441 info->branches = 0;
442 info->traps = 0;
443 info->affectsCPSR = 0;
444 info->condition = opcode >> 28;
445 info->sDataCycles = 0;
446 info->nDataCycles = 0;
447 info->sInstructionCycles = 1;
448 info->nInstructionCycles = 0;
449 info->iCycles = 0;
450 info->cCycles = 0;
451 ARMDecoder decoder = _armDecoderTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
452 decoder(opcode, info);
453}