1/* Copyright (c) 2013-2015 Jeffrey Pfau
   2 *
   3 * This Source Code Form is subject to the terms of the Mozilla Public
   4 * License, v. 2.0. If a copy of the MPL was not distributed with this
   5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
   6#include "memory.h"
   7
   8#include "macros.h"
   9
  10#include "decoder.h"
  11#include "gba/hardware.h"
  12#include "gba/io.h"
  13#include "gba/serialize.h"
  14#include "gba/hle-bios.h"
  15#include "util/memory.h"
  16
  17#define IDLE_LOOP_THRESHOLD 10000
  18
  19static uint32_t _popcount32(unsigned bits);
  20static uint32_t _deadbeef[2] = { 0xDEADBEEF, 0xFEEDFACE };
  21
  22static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t region);
  23static void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info);
  24
  25static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 };
  26static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 };
  27static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 };
  28static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 };
  29static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 };
  30static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 };
  31static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
  32
  33void GBAMemoryInit(struct GBA* gba) {
  34	struct ARMCore* cpu = gba->cpu;
  35	cpu->memory.load32 = GBALoad32;
  36	cpu->memory.load16 = GBALoad16;
  37	cpu->memory.load8 = GBALoad8;
  38	cpu->memory.loadMultiple = GBALoadMultiple;
  39	cpu->memory.store32 = GBAStore32;
  40	cpu->memory.store16 = GBAStore16;
  41	cpu->memory.store8 = GBAStore8;
  42	cpu->memory.storeMultiple = GBAStoreMultiple;
  43
  44	gba->memory.bios = (uint32_t*) hleBios;
  45	gba->memory.fullBios = 0;
  46	gba->memory.wram = 0;
  47	gba->memory.iwram = 0;
  48	gba->memory.rom = 0;
  49	gba->memory.hw.p = gba;
  50
  51	int i;
  52	for (i = 0; i < 16; ++i) {
  53		gba->memory.waitstatesNonseq16[i] = GBA_BASE_WAITSTATES[i];
  54		gba->memory.waitstatesSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  55		gba->memory.waitstatesPrefetchNonseq16[i] = GBA_BASE_WAITSTATES[i];
  56		gba->memory.waitstatesPrefetchSeq16[i] = GBA_BASE_WAITSTATES_SEQ[i];
  57		gba->memory.waitstatesNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  58		gba->memory.waitstatesSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  59		gba->memory.waitstatesPrefetchNonseq32[i] = GBA_BASE_WAITSTATES_32[i];
  60		gba->memory.waitstatesPrefetchSeq32[i] = GBA_BASE_WAITSTATES_SEQ_32[i];
  61	}
  62	for (; i < 256; ++i) {
  63		gba->memory.waitstatesNonseq16[i] = 0;
  64		gba->memory.waitstatesSeq16[i] = 0;
  65		gba->memory.waitstatesNonseq32[i] = 0;
  66		gba->memory.waitstatesSeq32[i] = 0;
  67	}
  68
  69	gba->memory.activeRegion = -1;
  70	cpu->memory.activeRegion = 0;
  71	cpu->memory.activeMask = 0;
  72	cpu->memory.setActiveRegion = GBASetActiveRegion;
  73	cpu->memory.activeSeqCycles32 = 0;
  74	cpu->memory.activeSeqCycles16 = 0;
  75	cpu->memory.activeNonseqCycles32 = 0;
  76	cpu->memory.activeNonseqCycles16 = 0;
  77	cpu->memory.activeUncachedCycles32 = 0;
  78	cpu->memory.activeUncachedCycles16 = 0;
  79	gba->memory.biosPrefetch = 0;
  80}
  81
  82void GBAMemoryDeinit(struct GBA* gba) {
  83	mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  84	mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
  85	if (gba->memory.rom) {
  86		mappedMemoryFree(gba->memory.rom, gba->memory.romSize);
  87	}
  88	GBASavedataDeinit(&gba->memory.savedata);
  89}
  90
  91void GBAMemoryReset(struct GBA* gba) {
  92	if (gba->memory.wram) {
  93		mappedMemoryFree(gba->memory.wram, SIZE_WORKING_RAM);
  94	}
  95	gba->memory.wram = anonymousMemoryMap(SIZE_WORKING_RAM);
  96
  97	if (gba->memory.iwram) {
  98		mappedMemoryFree(gba->memory.iwram, SIZE_WORKING_IRAM);
  99	}
 100	gba->memory.iwram = anonymousMemoryMap(SIZE_WORKING_IRAM);
 101
 102	memset(gba->memory.io, 0, sizeof(gba->memory.io));
 103	memset(gba->memory.dma, 0, sizeof(gba->memory.dma));
 104	int i;
 105	for (i = 0; i < 4; ++i) {
 106		gba->memory.dma[i].count = 0x4000;
 107		gba->memory.dma[i].nextEvent = INT_MAX;
 108	}
 109	gba->memory.dma[3].count = 0x10000;
 110	gba->memory.activeDMA = -1;
 111	gba->memory.nextDMA = INT_MAX;
 112	gba->memory.eventDiff = 0;
 113
 114	if (!gba->memory.wram || !gba->memory.iwram) {
 115		GBAMemoryDeinit(gba);
 116		GBALog(gba, GBA_LOG_FATAL, "Could not map memory");
 117	}
 118}
 119
 120static void _analyzeForIdleLoop(struct GBA* gba, struct ARMCore* cpu, uint32_t address) {
 121	struct ARMInstructionInfo info;
 122	uint32_t nextAddress = address;
 123	memset(gba->taintedRegisters, 0, sizeof(gba->taintedRegisters));
 124	if (cpu->executionMode == MODE_THUMB) {
 125		while (true) {
 126			uint16_t opcode;
 127			LOAD_16(opcode, nextAddress & cpu->memory.activeMask, cpu->memory.activeRegion);
 128			ARMDecodeThumb(opcode, &info);
 129			switch (info.branchType) {
 130			case ARM_BRANCH_NONE:
 131				if (info.operandFormat & ARM_OPERAND_MEMORY_2) {
 132					if (info.mnemonic == ARM_MN_STR || gba->taintedRegisters[info.memory.baseReg]) {
 133						gba->idleDetectionStep = -1;
 134						return;
 135					}
 136					uint32_t loadAddress = gba->cachedRegisters[info.memory.baseReg];
 137					uint32_t offset = 0;
 138					if (info.memory.format & ARM_MEMORY_IMMEDIATE_OFFSET) {
 139						offset = info.memory.offset.immediate;
 140					} else if (info.memory.format & ARM_MEMORY_REGISTER_OFFSET) {
 141						int reg = info.memory.offset.reg;
 142						if (gba->cachedRegisters[reg]) {
 143							gba->idleDetectionStep = -1;
 144							return;
 145						}
 146						offset = gba->cachedRegisters[reg];
 147					}
 148					if (info.memory.format & ARM_MEMORY_OFFSET_SUBTRACT) {
 149						loadAddress -= offset;
 150					} else {
 151						loadAddress += offset;
 152					}
 153					if ((loadAddress >> BASE_OFFSET) == REGION_IO) {
 154						gba->idleDetectionStep = -1;
 155						return;
 156					}
 157					if ((loadAddress >> BASE_OFFSET) < REGION_CART0 || (loadAddress >> BASE_OFFSET) > REGION_CART2_EX) {
 158						gba->taintedRegisters[info.op1.reg] = true;
 159					} else {
 160						switch (info.memory.width) {
 161						case 1:
 162							gba->cachedRegisters[info.op1.reg] = GBALoad8(cpu, loadAddress, 0);
 163							break;
 164						case 2:
 165							gba->cachedRegisters[info.op1.reg] = GBALoad16(cpu, loadAddress, 0);
 166							break;
 167						case 4:
 168							gba->cachedRegisters[info.op1.reg] = GBALoad32(cpu, loadAddress, 0);
 169							break;
 170						}
 171					}
 172				} else if (info.operandFormat & ARM_OPERAND_AFFECTED_1) {
 173					gba->taintedRegisters[info.op1.reg] = true;
 174				}
 175				nextAddress += WORD_SIZE_THUMB;
 176				break;
 177			case ARM_BRANCH:
 178				if ((uint32_t) info.op1.immediate + nextAddress + WORD_SIZE_THUMB * 2 == address) {
 179					gba->idleLoop = address;
 180					gba->idleOptimization = IDLE_LOOP_REMOVE;
 181				}
 182				gba->idleDetectionStep = -1;
 183				return;
 184			default:
 185				gba->idleDetectionStep = -1;
 186				return;
 187			}
 188		}
 189	} else {
 190		gba->idleDetectionStep = -1;
 191	}
 192}
 193
 194static void GBASetActiveRegion(struct ARMCore* cpu, uint32_t address) {
 195	struct GBA* gba = (struct GBA*) cpu->master;
 196	struct GBAMemory* memory = &gba->memory;
 197
 198	int newRegion = address >> BASE_OFFSET;
 199	if (gba->idleOptimization >= IDLE_LOOP_REMOVE && memory->activeRegion != REGION_BIOS) {
 200		if (address == gba->idleLoop) {
 201			if (gba->haltPending) {
 202				gba->haltPending = false;
 203				GBAHalt(gba);
 204			} else {
 205				gba->haltPending = true;
 206			}
 207		} else if (gba->idleOptimization >= IDLE_LOOP_DETECT && newRegion == memory->activeRegion) {
 208			if (address == gba->lastJump) {
 209				switch (gba->idleDetectionStep) {
 210				case 0:
 211					memcpy(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters));
 212					++gba->idleDetectionStep;
 213					break;
 214				case 1:
 215					if (memcmp(gba->cachedRegisters, cpu->gprs, sizeof(gba->cachedRegisters))) {
 216						gba->idleDetectionStep = -1;
 217						++gba->idleDetectionFailures;
 218						if (gba->idleDetectionFailures > IDLE_LOOP_THRESHOLD) {
 219							gba->idleOptimization = IDLE_LOOP_IGNORE;
 220						}
 221						break;
 222					}
 223					_analyzeForIdleLoop(gba, cpu, address);
 224					break;
 225				}
 226			} else {
 227				gba->idleDetectionStep = 0;
 228			}
 229		}
 230	}
 231
 232	gba->lastJump = address;
 233	if (newRegion == memory->activeRegion) {
 234		return;
 235	}
 236
 237	if (memory->activeRegion == REGION_BIOS) {
 238		memory->biosPrefetch = cpu->prefetch[1];
 239	}
 240	memory->activeRegion = newRegion;
 241	switch (address & ~OFFSET_MASK) {
 242	case BASE_BIOS:
 243		cpu->memory.activeRegion = memory->bios;
 244		cpu->memory.activeMask = SIZE_BIOS - 1;
 245		break;
 246	case BASE_WORKING_RAM:
 247		cpu->memory.activeRegion = memory->wram;
 248		cpu->memory.activeMask = SIZE_WORKING_RAM - 1;
 249		break;
 250	case BASE_WORKING_IRAM:
 251		cpu->memory.activeRegion = memory->iwram;
 252		cpu->memory.activeMask = SIZE_WORKING_IRAM - 1;
 253		break;
 254	case BASE_VRAM:
 255		cpu->memory.activeRegion = (uint32_t*) gba->video.renderer->vram;
 256		cpu->memory.activeMask = 0x0000FFFF;
 257		break;
 258	case BASE_CART0:
 259	case BASE_CART0_EX:
 260	case BASE_CART1:
 261	case BASE_CART1_EX:
 262	case BASE_CART2:
 263	case BASE_CART2_EX:
 264		cpu->memory.activeRegion = memory->rom;
 265		cpu->memory.activeMask = SIZE_CART0 - 1;
 266		break;
 267	default:
 268		cpu->memory.activeRegion = _deadbeef;
 269		cpu->memory.activeMask = 0;
 270		GBALog(gba, GBA_LOG_FATAL, "Jumped to invalid address");
 271		break;
 272	}
 273	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
 274	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
 275	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
 276	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
 277	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
 278	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
 279}
 280
 281#define LOAD_BAD \
 282	if (gba->performingDMA) { \
 283		value = gba->bus; \
 284	} else { \
 285		value = cpu->prefetch[1]; \
 286		if (cpu->executionMode == MODE_THUMB) { \
 287			/* http://ngemu.com/threads/gba-open-bus.170809/ */ \
 288			switch (cpu->gprs[ARM_PC] >> BASE_OFFSET) { \
 289			case REGION_BIOS: \
 290			case REGION_OAM: \
 291				/* This isn't right half the time, but we don't have $+6 handy */ \
 292				value <<= 16; \
 293				value |= cpu->prefetch[0]; \
 294				break; \
 295			case REGION_WORKING_IRAM: \
 296				/* This doesn't handle prefetch clobbering */ \
 297				if (cpu->gprs[ARM_PC] & 2) { \
 298					value |= cpu->prefetch[0] << 16; \
 299				} else { \
 300					value <<= 16; \
 301					value |= cpu->prefetch[0]; \
 302				} \
 303			default: \
 304				value |= value << 16; \
 305			} \
 306		} \
 307	}
 308
 309#define LOAD_BIOS \
 310	if (address < SIZE_BIOS) { \
 311		if (memory->activeRegion == REGION_BIOS) { \
 312			LOAD_32(value, address, memory->bios); \
 313		} else { \
 314			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load32: 0x%08X", address); \
 315			value = memory->biosPrefetch; \
 316		} \
 317	} else { \
 318		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address); \
 319		LOAD_BAD; \
 320	}
 321
 322#define LOAD_WORKING_RAM \
 323	LOAD_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 324	wait += waitstatesRegion[REGION_WORKING_RAM];
 325
 326#define LOAD_WORKING_IRAM LOAD_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 327#define LOAD_IO value = GBAIORead(gba, (address & (SIZE_IO - 1)) & ~2) | (GBAIORead(gba, (address & (SIZE_IO - 1)) | 2) << 16);
 328
 329#define LOAD_PALETTE_RAM \
 330	LOAD_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 331	++wait;
 332
 333#define LOAD_VRAM \
 334	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 335		LOAD_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 336	} else { \
 337		LOAD_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 338	} \
 339	++wait;
 340
 341#define LOAD_OAM LOAD_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 342
 343#define LOAD_CART \
 344	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 345	if ((address & (SIZE_CART0 - 1)) < memory->romSize) { \
 346		LOAD_32(value, address & (SIZE_CART0 - 1), memory->rom); \
 347	} else { \
 348		GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load32: 0x%08X", address); \
 349		value = (address >> 1) & 0xFFFF; \
 350		value |= value << 16; \
 351	}
 352
 353#define LOAD_SRAM \
 354	wait = memory->waitstatesNonseq16[address >> BASE_OFFSET]; \
 355	value = GBALoad8(cpu, address, 0); \
 356	value |= value << 8; \
 357	value |= value << 16;
 358
 359uint32_t GBALoad32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 360	struct GBA* gba = (struct GBA*) cpu->master;
 361	struct GBAMemory* memory = &gba->memory;
 362	uint32_t value = 0;
 363	int wait = 0;
 364	char* waitstatesRegion = memory->waitstatesNonseq32;
 365
 366	switch (address >> BASE_OFFSET) {
 367	case REGION_BIOS:
 368		LOAD_BIOS;
 369		break;
 370	case REGION_WORKING_RAM:
 371		LOAD_WORKING_RAM;
 372		break;
 373	case REGION_WORKING_IRAM:
 374		LOAD_WORKING_IRAM;
 375		break;
 376	case REGION_IO:
 377		LOAD_IO;
 378		break;
 379	case REGION_PALETTE_RAM:
 380		LOAD_PALETTE_RAM;
 381		break;
 382	case REGION_VRAM:
 383		LOAD_VRAM;
 384		break;
 385	case REGION_OAM:
 386		LOAD_OAM;
 387		break;
 388	case REGION_CART0:
 389	case REGION_CART0_EX:
 390	case REGION_CART1:
 391	case REGION_CART1_EX:
 392	case REGION_CART2:
 393	case REGION_CART2_EX:
 394		LOAD_CART;
 395		break;
 396	case REGION_CART_SRAM:
 397	case REGION_CART_SRAM_MIRROR:
 398		LOAD_SRAM;
 399		break;
 400	default:
 401		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load32: 0x%08X", address);
 402		LOAD_BAD;
 403		break;
 404	}
 405
 406	if (cycleCounter) {
 407		*cycleCounter += 1 + wait;
 408	}
 409	// Unaligned 32-bit loads are "rotated" so they make some semblance of sense
 410	int rotate = (address & 3) << 3;
 411	return ROR(value, rotate);
 412}
 413
 414uint32_t GBALoad16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 415	struct GBA* gba = (struct GBA*) cpu->master;
 416	struct GBAMemory* memory = &gba->memory;
 417	uint32_t value = 0;
 418	int wait = 0;
 419
 420	switch (address >> BASE_OFFSET) {
 421	case REGION_BIOS:
 422		if (address < SIZE_BIOS) {
 423			if (memory->activeRegion == REGION_BIOS) {
 424				LOAD_16(value, address, memory->bios);
 425			} else {
 426				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load16: 0x%08X", address);
 427				LOAD_16(value, address & 2, &memory->biosPrefetch);
 428			}
 429		} else {
 430			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 431			LOAD_BAD;
 432			uint32_t v2 = value;
 433			LOAD_16(value, address & 2, &v2);
 434		}
 435		break;
 436	case REGION_WORKING_RAM:
 437		LOAD_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 438		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 439		break;
 440	case REGION_WORKING_IRAM:
 441		LOAD_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 442		break;
 443	case REGION_IO:
 444		value = GBAIORead(gba, address & (SIZE_IO - 1));
 445		break;
 446	case REGION_PALETTE_RAM:
 447		LOAD_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 448		break;
 449	case REGION_VRAM:
 450		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 451			LOAD_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 452		} else {
 453			LOAD_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 454		}
 455		break;
 456	case REGION_OAM:
 457		LOAD_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 458		break;
 459	case REGION_CART0:
 460	case REGION_CART0_EX:
 461	case REGION_CART1:
 462	case REGION_CART1_EX:
 463	case REGION_CART2:
 464		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 465		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 466			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 467		} else {
 468			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 469			value = (address >> 1) & 0xFFFF; \
 470		}
 471		break;
 472	case REGION_CART2_EX:
 473		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 474		if (memory->savedata.type == SAVEDATA_EEPROM) {
 475			value = GBASavedataReadEEPROM(&memory->savedata);
 476		} else if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 477			LOAD_16(value, address & (SIZE_CART0 - 1), memory->rom);
 478		} else {
 479			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load16: 0x%08X", address);
 480			value = (address >> 1) & 0xFFFF; \
 481		}
 482		break;
 483	case REGION_CART_SRAM:
 484	case REGION_CART_SRAM_MIRROR:
 485		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 486		value = GBALoad8(cpu, address, 0);
 487		value |= value << 8;
 488		break;
 489	default:
 490		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load16: 0x%08X", address);
 491		LOAD_BAD;
 492		uint32_t v2 = value;
 493		LOAD_16(value, address & 2, &v2);
 494		break;
 495	}
 496
 497	if (cycleCounter) {
 498		*cycleCounter += 1 + wait;
 499	}
 500	// Unaligned 16-bit loads are "unpredictable", but the GBA rotates them, so we have to, too.
 501	int rotate = (address & 1) << 3;
 502	return ROR(value, rotate);
 503}
 504
 505uint32_t GBALoad8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
 506	struct GBA* gba = (struct GBA*) cpu->master;
 507	struct GBAMemory* memory = &gba->memory;
 508	uint32_t value = 0;
 509	int wait = 0;
 510
 511	switch (address >> BASE_OFFSET) {
 512	case REGION_BIOS:
 513		if (address < SIZE_BIOS) {
 514			if (memory->activeRegion == REGION_BIOS) {
 515				value = ((uint8_t*) memory->bios)[address];
 516			} else {
 517				GBALog(gba, GBA_LOG_GAME_ERROR, "Bad BIOS Load8: 0x%08X", address);
 518				value = ((uint8_t*) &memory->biosPrefetch)[address & 3];
 519			}
 520		} else {
 521			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 522			LOAD_BAD;
 523			value = ((uint8_t*) &value)[address & 3];
 524		}
 525		break;
 526	case REGION_WORKING_RAM:
 527		value = ((uint8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)];
 528		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 529		break;
 530	case REGION_WORKING_IRAM:
 531		value = ((uint8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)];
 532		break;
 533	case REGION_IO:
 534		value = (GBAIORead(gba, address & 0xFFFE) >> ((address & 0x0001) << 3)) & 0xFF;
 535		break;
 536	case REGION_PALETTE_RAM:
 537		value = ((uint8_t*) gba->video.palette)[address & (SIZE_PALETTE_RAM - 1)];
 538		break;
 539	case REGION_VRAM:
 540		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 541			value = ((uint8_t*) gba->video.renderer->vram)[address & 0x0001FFFF];
 542		} else {
 543			value = ((uint8_t*) gba->video.renderer->vram)[address & 0x00017FFF];
 544		}
 545		break;
 546	case REGION_OAM:
 547		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Load8: 0x%08X", address);
 548		break;
 549	case REGION_CART0:
 550	case REGION_CART0_EX:
 551	case REGION_CART1:
 552	case REGION_CART1_EX:
 553	case REGION_CART2:
 554	case REGION_CART2_EX:
 555		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 556		if ((address & (SIZE_CART0 - 1)) < memory->romSize) {
 557			value = ((uint8_t*) memory->rom)[address & (SIZE_CART0 - 1)];
 558		} else {
 559			GBALog(gba, GBA_LOG_GAME_ERROR, "Out of bounds ROM Load8: 0x%08X", address);
 560			value = (address >> 1) & 0xFF; \
 561		}
 562		break;
 563	case REGION_CART_SRAM:
 564	case REGION_CART_SRAM_MIRROR:
 565		wait = memory->waitstatesNonseq16[address >> BASE_OFFSET];
 566		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 567			GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 568			GBASavedataInitSRAM(&memory->savedata);
 569		}
 570		if (memory->savedata.type == SAVEDATA_SRAM) {
 571			value = memory->savedata.data[address & (SIZE_CART_SRAM - 1)];
 572		} else if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 573			value = GBASavedataReadFlash(&memory->savedata, address);
 574		} else if (memory->hw.devices & HW_TILT) {
 575			value = GBAHardwareTiltRead(&memory->hw, address & OFFSET_MASK);
 576		} else {
 577			GBALog(gba, GBA_LOG_GAME_ERROR, "Reading from non-existent SRAM: 0x%08X", address);
 578			value = 0xFF;
 579		}
 580		value &= 0xFF;
 581		break;
 582	default:
 583		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Load8: 0x%08x", address);
 584		LOAD_BAD;
 585		value = ((uint8_t*) &value)[address & 3];
 586		break;
 587	}
 588
 589	if (cycleCounter) {
 590		*cycleCounter += 1 + wait;
 591	}
 592	return value;
 593}
 594
 595#define STORE_WORKING_RAM \
 596	STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram); \
 597	wait += waitstatesRegion[REGION_WORKING_RAM];
 598
 599#define STORE_WORKING_IRAM \
 600	STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 601
 602#define STORE_IO \
 603	GBAIOWrite32(gba, address & (SIZE_IO - 1), value);
 604
 605#define STORE_PALETTE_RAM \
 606	STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette); \
 607	gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16); \
 608	++wait; \
 609	gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 610
 611#define STORE_VRAM \
 612	if ((address & 0x0001FFFF) < SIZE_VRAM) { \
 613		STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram); \
 614	} else { \
 615		STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram); \
 616	} \
 617	++wait;
 618
 619#define STORE_OAM \
 620	STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw); \
 621	gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 4)) >> 1); \
 622	gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 4)) >> 1) + 1);
 623
 624#define STORE_CART \
 625	wait += waitstatesRegion[address >> BASE_OFFSET]; \
 626	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 627
 628#define STORE_SRAM \
 629	GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store32: 0x%08X", address);
 630
 631#define STORE_BAD \
 632	GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store32: 0x%08X", address);
 633
 634void GBAStore32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
 635	struct GBA* gba = (struct GBA*) cpu->master;
 636	struct GBAMemory* memory = &gba->memory;
 637	int wait = 0;
 638	char* waitstatesRegion = memory->waitstatesNonseq32;
 639
 640	switch (address >> BASE_OFFSET) {
 641	case REGION_WORKING_RAM:
 642		STORE_WORKING_RAM;
 643		break;
 644	case REGION_WORKING_IRAM:
 645		STORE_WORKING_IRAM
 646		break;
 647	case REGION_IO:
 648		STORE_IO;
 649		break;
 650	case REGION_PALETTE_RAM:
 651		STORE_PALETTE_RAM;
 652		break;
 653	case REGION_VRAM:
 654		STORE_VRAM;
 655		break;
 656	case REGION_OAM:
 657		STORE_OAM;
 658		break;
 659	case REGION_CART0:
 660	case REGION_CART0_EX:
 661	case REGION_CART1:
 662	case REGION_CART1_EX:
 663	case REGION_CART2:
 664	case REGION_CART2_EX:
 665		STORE_CART;
 666		break;
 667	case REGION_CART_SRAM:
 668	case REGION_CART_SRAM_MIRROR:
 669		STORE_SRAM;
 670		break;
 671	default:
 672		STORE_BAD;
 673		break;
 674	}
 675
 676	if (cycleCounter) {
 677		*cycleCounter += 1 + wait;
 678	}
 679}
 680
 681void GBAStore16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
 682	struct GBA* gba = (struct GBA*) cpu->master;
 683	struct GBAMemory* memory = &gba->memory;
 684	int wait = 0;
 685
 686	switch (address >> BASE_OFFSET) {
 687	case REGION_WORKING_RAM:
 688		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 689		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 690		break;
 691	case REGION_WORKING_IRAM:
 692		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 693		break;
 694	case REGION_IO:
 695		GBAIOWrite(gba, address & (SIZE_IO - 1), value);
 696		break;
 697	case REGION_PALETTE_RAM:
 698		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 699		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 700		break;
 701	case REGION_VRAM:
 702		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 703			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 704		} else {
 705			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 706		}
 707		break;
 708	case REGION_OAM:
 709		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 710		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 711		break;
 712	case REGION_CART0:
 713		if (memory->hw.devices != HW_NONE && IS_GPIO_REGISTER(address & 0xFFFFFF)) {
 714			uint32_t reg = address & 0xFFFFFF;
 715			GBAHardwareGPIOWrite(&memory->hw, reg, value);
 716		} else {
 717			GBALog(gba, GBA_LOG_GAME_ERROR, "Bad cartridge Store16: 0x%08X", address);
 718		}
 719		break;
 720	case REGION_CART2_EX:
 721		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 722			GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
 723			GBASavedataInitEEPROM(&memory->savedata);
 724		}
 725		GBASavedataWriteEEPROM(&memory->savedata, value, 1);
 726		break;
 727	case REGION_CART_SRAM:
 728	case REGION_CART_SRAM_MIRROR:
 729		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store16: 0x%08X", address);
 730		break;
 731	default:
 732		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store16: 0x%08X", address);
 733		break;
 734	}
 735
 736	if (cycleCounter) {
 737		*cycleCounter += 1 + wait;
 738	}
 739}
 740
 741void GBAStore8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
 742	struct GBA* gba = (struct GBA*) cpu->master;
 743	struct GBAMemory* memory = &gba->memory;
 744	int wait = 0;
 745
 746	switch (address >> BASE_OFFSET) {
 747	case REGION_WORKING_RAM:
 748		((int8_t*) memory->wram)[address & (SIZE_WORKING_RAM - 1)] = value;
 749		wait = memory->waitstatesNonseq16[REGION_WORKING_RAM];
 750		break;
 751	case REGION_WORKING_IRAM:
 752		((int8_t*) memory->iwram)[address & (SIZE_WORKING_IRAM - 1)] = value;
 753		break;
 754	case REGION_IO:
 755		GBAIOWrite8(gba, address & (SIZE_IO - 1), value);
 756		break;
 757	case REGION_PALETTE_RAM:
 758		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 759		break;
 760	case REGION_VRAM:
 761		if (address >= 0x06018000) {
 762			// TODO: check BG mode
 763			GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OBJ: 0x%08X", address);
 764			break;
 765		}
 766		((int8_t*) gba->video.renderer->vram)[address & 0x1FFFE] = value;
 767		((int8_t*) gba->video.renderer->vram)[(address & 0x1FFFE) | 1] = value;
 768		break;
 769	case REGION_OAM:
 770		GBALog(gba, GBA_LOG_GAME_ERROR, "Cannot Store8 to OAM: 0x%08X", address);
 771		break;
 772	case REGION_CART0:
 773		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Store8: 0x%08X", address);
 774		break;
 775	case REGION_CART_SRAM:
 776	case REGION_CART_SRAM_MIRROR:
 777		if (memory->savedata.type == SAVEDATA_AUTODETECT) {
 778			if (address == SAVEDATA_FLASH_BASE) {
 779				GBALog(gba, GBA_LOG_INFO, "Detected Flash savegame");
 780				GBASavedataInitFlash(&memory->savedata, gba->realisticTiming);
 781			} else {
 782				GBALog(gba, GBA_LOG_INFO, "Detected SRAM savegame");
 783				GBASavedataInitSRAM(&memory->savedata);
 784			}
 785		}
 786		if (memory->savedata.type == SAVEDATA_FLASH512 || memory->savedata.type == SAVEDATA_FLASH1M) {
 787			GBASavedataWriteFlash(&memory->savedata, address, value);
 788		} else if (memory->savedata.type == SAVEDATA_SRAM) {
 789			memory->savedata.data[address & (SIZE_CART_SRAM - 1)] = value;
 790		} else if (memory->hw.devices & HW_TILT) {
 791			GBAHardwareTiltWrite(&memory->hw, address & OFFSET_MASK, value);
 792		} else {
 793			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 794		}
 795		wait = memory->waitstatesNonseq16[REGION_CART_SRAM];
 796		break;
 797	default:
 798		GBALog(gba, GBA_LOG_GAME_ERROR, "Bad memory Store8: 0x%08X", address);
 799		break;
 800	}
 801
 802	if (cycleCounter) {
 803		*cycleCounter += 1 + wait;
 804	}
 805}
 806
 807void GBAPatch32(struct ARMCore* cpu, uint32_t address, int32_t value, int32_t* old) {
 808	struct GBA* gba = (struct GBA*) cpu->master;
 809	struct GBAMemory* memory = &gba->memory;
 810	int32_t oldValue = -1;
 811
 812	switch (address >> BASE_OFFSET) {
 813	case REGION_WORKING_RAM:
 814		LOAD_32(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 815		STORE_32(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 816		break;
 817	case REGION_WORKING_IRAM:
 818		LOAD_32(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 819		STORE_32(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 820		break;
 821	case REGION_IO:
 822		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch32: 0x%08X", address);
 823		break;
 824	case REGION_PALETTE_RAM:
 825		LOAD_32(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 826		STORE_32(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 827		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 828		gba->video.renderer->writePalette(gba->video.renderer, (address & (SIZE_PALETTE_RAM - 1)) + 2, value >> 16);
 829		break;
 830	case REGION_VRAM:
 831		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 832			LOAD_32(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 833			STORE_32(value, address & 0x0001FFFF, gba->video.renderer->vram);
 834		} else {
 835			LOAD_32(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 836			STORE_32(value, address & 0x00017FFF, gba->video.renderer->vram);
 837		}
 838		break;
 839	case REGION_OAM:
 840		LOAD_32(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 841		STORE_32(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 842		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 843		gba->video.renderer->writeOAM(gba->video.renderer, ((address & (SIZE_OAM - 1)) + 2) >> 1);
 844		break;
 845	case REGION_CART0:
 846	case REGION_CART0_EX:
 847	case REGION_CART1:
 848	case REGION_CART1_EX:
 849	case REGION_CART2:
 850	case REGION_CART2_EX:
 851		if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
 852			LOAD_32(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 853			STORE_32(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 854		} else {
 855			GBALog(gba, GBA_LOG_WARN, "Bad memory Patch32: 0x%08X", address);
 856		}
 857		break;
 858	case REGION_CART_SRAM:
 859	case REGION_CART_SRAM_MIRROR:
 860		if (memory->savedata.type == SAVEDATA_SRAM) {
 861			LOAD_32(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 862			STORE_32(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 863		} else {
 864			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 865		}
 866		break;
 867	default:
 868		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 869		break;
 870	}
 871	if (old) {
 872		*old = oldValue;
 873	}
 874}
 875
 876void GBAPatch16(struct ARMCore* cpu, uint32_t address, int16_t value, int16_t* old) {
 877	struct GBA* gba = (struct GBA*) cpu->master;
 878	struct GBAMemory* memory = &gba->memory;
 879	int16_t oldValue = -1;
 880
 881	switch (address >> BASE_OFFSET) {
 882	case REGION_WORKING_RAM:
 883		LOAD_16(oldValue, address & (SIZE_WORKING_RAM - 1), memory->wram);
 884		STORE_16(value, address & (SIZE_WORKING_RAM - 1), memory->wram);
 885		break;
 886	case REGION_WORKING_IRAM:
 887		LOAD_16(oldValue, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 888		STORE_16(value, address & (SIZE_WORKING_IRAM - 1), memory->iwram);
 889		break;
 890	case REGION_IO:
 891		GBALog(gba, GBA_LOG_STUB, "Unimplemented memory Patch16: 0x%08X", address);
 892		break;
 893	case REGION_PALETTE_RAM:
 894		LOAD_16(oldValue, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 895		STORE_16(value, address & (SIZE_PALETTE_RAM - 1), gba->video.palette);
 896		gba->video.renderer->writePalette(gba->video.renderer, address & (SIZE_PALETTE_RAM - 1), value);
 897		break;
 898	case REGION_VRAM:
 899		if ((address & 0x0001FFFF) < SIZE_VRAM) {
 900			LOAD_16(oldValue, address & 0x0001FFFF, gba->video.renderer->vram);
 901			STORE_16(value, address & 0x0001FFFF, gba->video.renderer->vram);
 902		} else {
 903			LOAD_16(oldValue, address & 0x00017FFF, gba->video.renderer->vram);
 904			STORE_16(value, address & 0x00017FFF, gba->video.renderer->vram);
 905		}
 906		break;
 907	case REGION_OAM:
 908		LOAD_16(oldValue, address & (SIZE_OAM - 1), gba->video.oam.raw);
 909		STORE_16(value, address & (SIZE_OAM - 1), gba->video.oam.raw);
 910		gba->video.renderer->writeOAM(gba->video.renderer, (address & (SIZE_OAM - 1)) >> 1);
 911		break;
 912	case REGION_CART0:
 913	case REGION_CART0_EX:
 914	case REGION_CART1:
 915	case REGION_CART1_EX:
 916	case REGION_CART2:
 917	case REGION_CART2_EX:
 918		if ((address & (SIZE_CART0 - 1)) < gba->memory.romSize) {
 919			LOAD_16(oldValue, address & (SIZE_CART0 - 1), gba->memory.rom);
 920			STORE_16(value, address & (SIZE_CART0 - 1), gba->memory.rom);
 921		} else {
 922			GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 923		}
 924		break;
 925	case REGION_CART_SRAM:
 926	case REGION_CART_SRAM_MIRROR:
 927		if (memory->savedata.type == SAVEDATA_SRAM) {
 928			LOAD_16(oldValue, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 929			STORE_16(value, address & (SIZE_CART_SRAM - 1), memory->savedata.data);
 930		} else {
 931			GBALog(gba, GBA_LOG_GAME_ERROR, "Writing to non-existent SRAM: 0x%08X", address);
 932		}
 933		break;
 934	default:
 935		GBALog(gba, GBA_LOG_WARN, "Bad memory Patch16: 0x%08X", address);
 936		break;
 937	}
 938	if (old) {
 939		*old = oldValue;
 940	}
 941}
 942
 943#define LDM_LOOP(LDM) \
 944	for (i = 0; i < 16; i += 4) { \
 945		if (UNLIKELY(mask & (1 << i))) { \
 946			LDM; \
 947			waitstatesRegion = memory->waitstatesSeq32; \
 948			cpu->gprs[i] = value; \
 949			++wait; \
 950			address += 4; \
 951		} \
 952		if (UNLIKELY(mask & (2 << i))) { \
 953			LDM; \
 954			waitstatesRegion = memory->waitstatesSeq32; \
 955			cpu->gprs[i + 1] = value; \
 956			++wait; \
 957			address += 4; \
 958		} \
 959		if (UNLIKELY(mask & (4 << i))) { \
 960			LDM; \
 961			waitstatesRegion = memory->waitstatesSeq32; \
 962			cpu->gprs[i + 2] = value; \
 963			++wait; \
 964			address += 4; \
 965		} \
 966		if (UNLIKELY(mask & (8 << i))) { \
 967			LDM; \
 968			waitstatesRegion = memory->waitstatesSeq32; \
 969			cpu->gprs[i + 3] = value; \
 970			++wait; \
 971			address += 4; \
 972		} \
 973	}
 974
 975uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
 976	struct GBA* gba = (struct GBA*) cpu->master;
 977	struct GBAMemory* memory = &gba->memory;
 978	uint32_t value;
 979	int wait = 0;
 980	char* waitstatesRegion = memory->waitstatesNonseq32;
 981
 982	int i;
 983	int offset = 4;
 984	int popcount = 0;
 985	if (direction & LSM_D) {
 986		offset = -4;
 987		popcount = _popcount32(mask);
 988		address -= (popcount << 2) - 4;
 989	}
 990
 991	if (direction & LSM_B) {
 992		address += offset;
 993	}
 994
 995	uint32_t addressMisalign = address & 0x3;
 996	address &= 0xFFFFFFFC;
 997
 998	switch (address >> BASE_OFFSET) {
 999	case REGION_BIOS:
1000		LDM_LOOP(LOAD_BIOS);
1001		break;
1002	case REGION_WORKING_RAM:
1003		LDM_LOOP(LOAD_WORKING_RAM);
1004		break;
1005	case REGION_WORKING_IRAM:
1006		LDM_LOOP(LOAD_WORKING_IRAM);
1007		break;
1008	case REGION_IO:
1009		LDM_LOOP(LOAD_IO);
1010		break;
1011	case REGION_PALETTE_RAM:
1012		LDM_LOOP(LOAD_PALETTE_RAM);
1013		break;
1014	case REGION_VRAM:
1015		LDM_LOOP(LOAD_VRAM);
1016		break;
1017	case REGION_OAM:
1018		LDM_LOOP(LOAD_OAM);
1019		break;
1020	case REGION_CART0:
1021	case REGION_CART0_EX:
1022	case REGION_CART1:
1023	case REGION_CART1_EX:
1024	case REGION_CART2:
1025	case REGION_CART2_EX:
1026		LDM_LOOP(LOAD_CART);
1027		break;
1028	case REGION_CART_SRAM:
1029	case REGION_CART_SRAM_MIRROR:
1030		LDM_LOOP(LOAD_SRAM);
1031		break;
1032	default:
1033		LDM_LOOP(LOAD_BAD);
1034		break;
1035	}
1036
1037	if (cycleCounter) {
1038		*cycleCounter += wait;
1039	}
1040
1041	if (direction & LSM_B) {
1042		address -= offset;
1043	}
1044
1045	if (direction & LSM_D) {
1046		address -= (popcount << 2) + 4;
1047	}
1048
1049	return address | addressMisalign;
1050}
1051
1052#define STM_LOOP(STM) \
1053	for (i = 0; i < 16; i += 4) { \
1054		if (UNLIKELY(mask & (1 << i))) { \
1055			value = cpu->gprs[i]; \
1056			STM; \
1057			waitstatesRegion = memory->waitstatesSeq32; \
1058			++wait; \
1059			address += 4; \
1060		} \
1061		if (UNLIKELY(mask & (2 << i))) { \
1062			value = cpu->gprs[i + 1]; \
1063			STM; \
1064			waitstatesRegion = memory->waitstatesSeq32; \
1065			++wait; \
1066			address += 4; \
1067		} \
1068		if (UNLIKELY(mask & (4 << i))) { \
1069			value = cpu->gprs[i + 2]; \
1070			STM; \
1071			waitstatesRegion = memory->waitstatesSeq32; \
1072			++wait; \
1073			address += 4; \
1074		} \
1075		if (UNLIKELY(mask & (8 << i))) { \
1076			value = cpu->gprs[i + 3]; \
1077			STM; \
1078			waitstatesRegion = memory->waitstatesSeq32; \
1079			++wait; \
1080			address += 4; \
1081		} \
1082	}
1083
1084uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
1085	struct GBA* gba = (struct GBA*) cpu->master;
1086	struct GBAMemory* memory = &gba->memory;
1087	uint32_t value;
1088	int wait = 0;
1089	char* waitstatesRegion = memory->waitstatesNonseq32;
1090
1091	int i;
1092	int offset = 4;
1093	int popcount = 0;
1094	if (direction & LSM_D) {
1095		offset = -4;
1096		popcount = _popcount32(mask);
1097		address -= (popcount << 2) - 4;
1098	}
1099
1100	if (direction & LSM_B) {
1101		address += offset;
1102	}
1103
1104	uint32_t addressMisalign = address & 0x3;
1105	address &= 0xFFFFFFFC;
1106
1107	switch (address >> BASE_OFFSET) {
1108	case REGION_WORKING_RAM:
1109		STM_LOOP(STORE_WORKING_RAM);
1110		break;
1111	case REGION_WORKING_IRAM:
1112		STM_LOOP(STORE_WORKING_IRAM);
1113		break;
1114	case REGION_IO:
1115		STM_LOOP(STORE_IO);
1116		break;
1117	case REGION_PALETTE_RAM:
1118		STM_LOOP(STORE_PALETTE_RAM);
1119		break;
1120	case REGION_VRAM:
1121		STM_LOOP(STORE_VRAM);
1122		break;
1123	case REGION_OAM:
1124		STM_LOOP(STORE_OAM);
1125		break;
1126	case REGION_CART0:
1127	case REGION_CART0_EX:
1128	case REGION_CART1:
1129	case REGION_CART1_EX:
1130	case REGION_CART2:
1131	case REGION_CART2_EX:
1132		STM_LOOP(STORE_CART);
1133		break;
1134	case REGION_CART_SRAM:
1135	case REGION_CART_SRAM_MIRROR:
1136		STM_LOOP(STORE_SRAM);
1137		break;
1138	default:
1139		STM_LOOP(STORE_BAD);
1140		break;
1141	}
1142
1143	if (cycleCounter) {
1144		*cycleCounter += wait;
1145	}
1146
1147	if (direction & LSM_B) {
1148		address -= offset;
1149	}
1150
1151	if (direction & LSM_D) {
1152		address -= (popcount << 2) + 4;
1153	}
1154
1155	return address | addressMisalign;
1156}
1157
1158void GBAAdjustWaitstates(struct GBA* gba, uint16_t parameters) {
1159	struct GBAMemory* memory = &gba->memory;
1160	struct ARMCore* cpu = gba->cpu;
1161	int sram = parameters & 0x0003;
1162	int ws0 = (parameters & 0x000C) >> 2;
1163	int ws0seq = (parameters & 0x0010) >> 4;
1164	int ws1 = (parameters & 0x0060) >> 5;
1165	int ws1seq = (parameters & 0x0080) >> 7;
1166	int ws2 = (parameters & 0x0300) >> 8;
1167	int ws2seq = (parameters & 0x0400) >> 10;
1168	int prefetch = parameters & 0x4000;
1169
1170	memory->waitstatesNonseq16[REGION_CART_SRAM] = memory->waitstatesNonseq16[REGION_CART_SRAM_MIRROR] =  GBA_ROM_WAITSTATES[sram];
1171	memory->waitstatesSeq16[REGION_CART_SRAM] = memory->waitstatesSeq16[REGION_CART_SRAM_MIRROR] = GBA_ROM_WAITSTATES[sram];
1172	memory->waitstatesNonseq32[REGION_CART_SRAM] = memory->waitstatesNonseq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1173	memory->waitstatesSeq32[REGION_CART_SRAM] = memory->waitstatesSeq32[REGION_CART_SRAM_MIRROR] = 2 * GBA_ROM_WAITSTATES[sram] + 1;
1174
1175	memory->waitstatesNonseq16[REGION_CART0] = memory->waitstatesNonseq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES[ws0];
1176	memory->waitstatesNonseq16[REGION_CART1] = memory->waitstatesNonseq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES[ws1];
1177	memory->waitstatesNonseq16[REGION_CART2] = memory->waitstatesNonseq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES[ws2];
1178
1179	memory->waitstatesSeq16[REGION_CART0] = memory->waitstatesSeq16[REGION_CART0_EX] = GBA_ROM_WAITSTATES_SEQ[ws0seq];
1180	memory->waitstatesSeq16[REGION_CART1] = memory->waitstatesSeq16[REGION_CART1_EX] = GBA_ROM_WAITSTATES_SEQ[ws1seq + 2];
1181	memory->waitstatesSeq16[REGION_CART2] = memory->waitstatesSeq16[REGION_CART2_EX] = GBA_ROM_WAITSTATES_SEQ[ws2seq + 4];
1182
1183	memory->waitstatesNonseq32[REGION_CART0] = memory->waitstatesNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0] + 1 + memory->waitstatesSeq16[REGION_CART0];
1184	memory->waitstatesNonseq32[REGION_CART1] = memory->waitstatesNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1] + 1 + memory->waitstatesSeq16[REGION_CART1];
1185	memory->waitstatesNonseq32[REGION_CART2] = memory->waitstatesNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2] + 1 + memory->waitstatesSeq16[REGION_CART2];
1186
1187	memory->waitstatesSeq32[REGION_CART0] = memory->waitstatesSeq32[REGION_CART0_EX] = 2 * memory->waitstatesSeq16[REGION_CART0] + 1;
1188	memory->waitstatesSeq32[REGION_CART1] = memory->waitstatesSeq32[REGION_CART1_EX] = 2 * memory->waitstatesSeq16[REGION_CART1] + 1;
1189	memory->waitstatesSeq32[REGION_CART2] = memory->waitstatesSeq32[REGION_CART2_EX] = 2 * memory->waitstatesSeq16[REGION_CART2] + 1;
1190
1191	if (!prefetch) {
1192		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = memory->waitstatesSeq16[REGION_CART0];
1193		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = memory->waitstatesSeq16[REGION_CART1];
1194		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = memory->waitstatesSeq16[REGION_CART2];
1195
1196		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = memory->waitstatesSeq32[REGION_CART0];
1197		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = memory->waitstatesSeq32[REGION_CART1];
1198		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = memory->waitstatesSeq32[REGION_CART2];
1199
1200		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = memory->waitstatesNonseq16[REGION_CART0];
1201		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = memory->waitstatesNonseq16[REGION_CART1];
1202		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = memory->waitstatesNonseq16[REGION_CART2];
1203
1204		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = memory->waitstatesNonseq32[REGION_CART0];
1205		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = memory->waitstatesNonseq32[REGION_CART1];
1206		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = memory->waitstatesNonseq32[REGION_CART2];
1207	} else {
1208		memory->waitstatesPrefetchSeq16[REGION_CART0] = memory->waitstatesPrefetchSeq16[REGION_CART0_EX] = 0;
1209		memory->waitstatesPrefetchSeq16[REGION_CART1] = memory->waitstatesPrefetchSeq16[REGION_CART1_EX] = 0;
1210		memory->waitstatesPrefetchSeq16[REGION_CART2] = memory->waitstatesPrefetchSeq16[REGION_CART2_EX] = 0;
1211
1212		memory->waitstatesPrefetchSeq32[REGION_CART0] = memory->waitstatesPrefetchSeq32[REGION_CART0_EX] = 0;
1213		memory->waitstatesPrefetchSeq32[REGION_CART1] = memory->waitstatesPrefetchSeq32[REGION_CART1_EX] = 0;
1214		memory->waitstatesPrefetchSeq32[REGION_CART2] = memory->waitstatesPrefetchSeq32[REGION_CART2_EX] = 0;
1215
1216		memory->waitstatesPrefetchNonseq16[REGION_CART0] = memory->waitstatesPrefetchNonseq16[REGION_CART0_EX] = 0;
1217		memory->waitstatesPrefetchNonseq16[REGION_CART1] = memory->waitstatesPrefetchNonseq16[REGION_CART1_EX] = 0;
1218		memory->waitstatesPrefetchNonseq16[REGION_CART2] = memory->waitstatesPrefetchNonseq16[REGION_CART2_EX] = 0;
1219
1220		memory->waitstatesPrefetchNonseq32[REGION_CART0] = memory->waitstatesPrefetchNonseq32[REGION_CART0_EX] = 0;
1221		memory->waitstatesPrefetchNonseq32[REGION_CART1] = memory->waitstatesPrefetchNonseq32[REGION_CART1_EX] = 0;
1222		memory->waitstatesPrefetchNonseq32[REGION_CART2] = memory->waitstatesPrefetchNonseq32[REGION_CART2_EX] = 0;
1223	}
1224
1225	cpu->memory.activeSeqCycles32 = memory->waitstatesPrefetchSeq32[memory->activeRegion];
1226	cpu->memory.activeSeqCycles16 = memory->waitstatesPrefetchSeq16[memory->activeRegion];
1227
1228	cpu->memory.activeNonseqCycles32 = memory->waitstatesPrefetchNonseq32[memory->activeRegion];
1229	cpu->memory.activeNonseqCycles16 = memory->waitstatesPrefetchNonseq16[memory->activeRegion];
1230
1231	cpu->memory.activeUncachedCycles32 = memory->waitstatesNonseq32[memory->activeRegion];
1232	cpu->memory.activeUncachedCycles16 = memory->waitstatesNonseq16[memory->activeRegion];
1233}
1234
1235void GBAMemoryWriteDMASAD(struct GBA* gba, int dma, uint32_t address) {
1236	struct GBAMemory* memory = &gba->memory;
1237	memory->dma[dma].source = address & 0x0FFFFFFE;
1238}
1239
1240void GBAMemoryWriteDMADAD(struct GBA* gba, int dma, uint32_t address) {
1241	struct GBAMemory* memory = &gba->memory;
1242	memory->dma[dma].dest = address & 0x0FFFFFFE;
1243}
1244
1245void GBAMemoryWriteDMACNT_LO(struct GBA* gba, int dma, uint16_t count) {
1246	struct GBAMemory* memory = &gba->memory;
1247	memory->dma[dma].count = count ? count : (dma == 3 ? 0x10000 : 0x4000);
1248}
1249
1250uint16_t GBAMemoryWriteDMACNT_HI(struct GBA* gba, int dma, uint16_t control) {
1251	struct GBAMemory* memory = &gba->memory;
1252	struct GBADMA* currentDma = &memory->dma[dma];
1253	int wasEnabled = GBADMARegisterIsEnable(currentDma->reg);
1254	int oldTiming = GBADMARegisterGetTiming(currentDma->reg);
1255	int newTiming = GBADMARegisterGetTiming(control);
1256	// This is probably a huge hack...verify what this does on hardware
1257	if (oldTiming && oldTiming != DMA_TIMING_CUSTOM && oldTiming != newTiming) {
1258		wasEnabled = false;
1259	}
1260	currentDma->reg = control;
1261
1262	if (GBADMARegisterIsDRQ(currentDma->reg)) {
1263		GBALog(gba, GBA_LOG_STUB, "DRQ not implemented");
1264	}
1265
1266	if (!wasEnabled && GBADMARegisterIsEnable(currentDma->reg)) {
1267		currentDma->nextSource = currentDma->source;
1268		currentDma->nextDest = currentDma->dest;
1269		currentDma->nextCount = currentDma->count;
1270		GBAMemoryScheduleDMA(gba, dma, currentDma);
1271	}
1272	// If the DMA has already occurred, this value might have changed since the function started
1273	return currentDma->reg;
1274};
1275
1276void GBAMemoryScheduleDMA(struct GBA* gba, int number, struct GBADMA* info) {
1277	struct ARMCore* cpu = gba->cpu;
1278	switch (GBADMARegisterGetTiming(info->reg)) {
1279	case DMA_TIMING_NOW:
1280		info->nextEvent = cpu->cycles;
1281		GBAMemoryUpdateDMAs(gba, 0);
1282		break;
1283	case DMA_TIMING_HBLANK:
1284		// Handled implicitly
1285		info->nextEvent = INT_MAX;
1286		break;
1287	case DMA_TIMING_VBLANK:
1288		// Handled implicitly
1289		info->nextEvent = INT_MAX;
1290		break;
1291	case DMA_TIMING_CUSTOM:
1292		info->nextEvent = INT_MAX;
1293		switch (number) {
1294		case 0:
1295			GBALog(gba, GBA_LOG_WARN, "Discarding invalid DMA0 scheduling");
1296			break;
1297		case 1:
1298		case 2:
1299			GBAAudioScheduleFifoDma(&gba->audio, number, info);
1300			break;
1301		case 3:
1302			// GBAVideoScheduleVCaptureDma(dma, info);
1303			break;
1304		}
1305	}
1306}
1307
1308void GBAMemoryRunHblankDMAs(struct GBA* gba, int32_t cycles) {
1309	struct GBAMemory* memory = &gba->memory;
1310	struct GBADMA* dma;
1311	int i;
1312	for (i = 0; i < 4; ++i) {
1313		dma = &memory->dma[i];
1314		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_HBLANK) {
1315			dma->nextEvent = cycles;
1316		}
1317	}
1318	GBAMemoryUpdateDMAs(gba, 0);
1319}
1320
1321void GBAMemoryRunVblankDMAs(struct GBA* gba, int32_t cycles) {
1322	struct GBAMemory* memory = &gba->memory;
1323	struct GBADMA* dma;
1324	int i;
1325	for (i = 0; i < 4; ++i) {
1326		dma = &memory->dma[i];
1327		if (GBADMARegisterIsEnable(dma->reg) && GBADMARegisterGetTiming(dma->reg) == DMA_TIMING_VBLANK) {
1328			dma->nextEvent = cycles;
1329		}
1330	}
1331	GBAMemoryUpdateDMAs(gba, 0);
1332}
1333
1334int32_t GBAMemoryRunDMAs(struct GBA* gba, int32_t cycles) {
1335	struct GBAMemory* memory = &gba->memory;
1336	if (memory->nextDMA == INT_MAX) {
1337		return INT_MAX;
1338	}
1339	memory->nextDMA -= cycles;
1340	memory->eventDiff += cycles;
1341	if (memory->nextDMA <= 0) {
1342		struct GBADMA* dma = &memory->dma[memory->activeDMA];
1343		GBAMemoryServiceDMA(gba, memory->activeDMA, dma);
1344		GBAMemoryUpdateDMAs(gba, memory->eventDiff);
1345		memory->eventDiff = 0;
1346	}
1347	return memory->nextDMA;
1348}
1349
1350void GBAMemoryUpdateDMAs(struct GBA* gba, int32_t cycles) {
1351	int i;
1352	struct GBAMemory* memory = &gba->memory;
1353	struct ARMCore* cpu = gba->cpu;
1354	memory->activeDMA = -1;
1355	memory->nextDMA = INT_MAX;
1356	for (i = 3; i >= 0; --i) {
1357		struct GBADMA* dma = &memory->dma[i];
1358		if (dma->nextEvent != INT_MAX) {
1359			dma->nextEvent -= cycles;
1360			if (GBADMARegisterIsEnable(dma->reg)) {
1361				memory->activeDMA = i;
1362				memory->nextDMA = dma->nextEvent;
1363			}
1364		}
1365	}
1366	if (memory->nextDMA < cpu->nextEvent) {
1367		cpu->nextEvent = memory->nextDMA;
1368	}
1369}
1370
1371void GBAMemoryServiceDMA(struct GBA* gba, int number, struct GBADMA* info) {
1372	struct GBAMemory* memory = &gba->memory;
1373	struct ARMCore* cpu = gba->cpu;
1374	uint32_t width = GBADMARegisterGetWidth(info->reg) ? 4 : 2;
1375	int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
1376	int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;
1377	int32_t wordsRemaining = info->nextCount;
1378	uint32_t source = info->nextSource;
1379	uint32_t dest = info->nextDest;
1380	uint32_t sourceRegion = source >> BASE_OFFSET;
1381	uint32_t destRegion = dest >> BASE_OFFSET;
1382	int32_t cycles = 2;
1383
1384	if (source == info->source) {
1385		// TODO: support 4 cycles for ROM access
1386		cycles += 2;
1387		if (width == 4) {
1388			cycles += memory->waitstatesNonseq32[sourceRegion] + memory->waitstatesNonseq32[destRegion];
1389			source &= 0xFFFFFFFC;
1390			dest &= 0xFFFFFFFC;
1391		} else {
1392			cycles += memory->waitstatesNonseq16[sourceRegion] + memory->waitstatesNonseq16[destRegion];
1393		}
1394	} else {
1395		if (width == 4) {
1396			cycles += memory->waitstatesSeq32[sourceRegion] + memory->waitstatesSeq32[destRegion];
1397		} else {
1398			cycles += memory->waitstatesSeq16[sourceRegion] + memory->waitstatesSeq16[destRegion];
1399		}
1400	}
1401
1402	gba->performingDMA = true;
1403	int32_t word;
1404	if (width == 4) {
1405		word = cpu->memory.load32(cpu, source, 0);
1406		gba->bus = word;
1407		cpu->memory.store32(cpu, dest, word, 0);
1408		source += sourceOffset;
1409		dest += destOffset;
1410		--wordsRemaining;
1411	} else {
1412		if (sourceRegion == REGION_CART2_EX && memory->savedata.type == SAVEDATA_EEPROM) {
1413			word = GBASavedataReadEEPROM(&memory->savedata);
1414			gba->bus = word | (word << 16);
1415			cpu->memory.store16(cpu, dest, word, 0);
1416			source += sourceOffset;
1417			dest += destOffset;
1418			--wordsRemaining;
1419		} else if (destRegion == REGION_CART2_EX) {
1420			if (memory->savedata.type == SAVEDATA_AUTODETECT) {
1421				GBALog(gba, GBA_LOG_INFO, "Detected EEPROM savegame");
1422				GBASavedataInitEEPROM(&memory->savedata);
1423			}
1424			word = cpu->memory.load16(cpu, source, 0);
1425			gba->bus = word | (word << 16);
1426			GBASavedataWriteEEPROM(&memory->savedata, word, wordsRemaining);
1427			source += sourceOffset;
1428			dest += destOffset;
1429			--wordsRemaining;
1430		} else {
1431			word = cpu->memory.load16(cpu, source, 0);
1432			gba->bus = word | (word << 16);
1433			cpu->memory.store16(cpu, dest, word, 0);
1434			source += sourceOffset;
1435			dest += destOffset;
1436			--wordsRemaining;
1437		}
1438	}
1439	gba->performingDMA = false;
1440
1441	if (!wordsRemaining) {
1442		if (!GBADMARegisterIsRepeat(info->reg) || GBADMARegisterGetTiming(info->reg) == DMA_TIMING_NOW) {
1443			info->reg = GBADMARegisterClearEnable(info->reg);
1444			info->nextEvent = INT_MAX;
1445
1446			// Clear the enable bit in memory
1447			memory->io[(REG_DMA0CNT_HI + number * (REG_DMA1CNT_HI - REG_DMA0CNT_HI)) >> 1] &= 0x7FE0;
1448		} else {
1449			info->nextCount = info->count;
1450			if (GBADMARegisterGetDestControl(info->reg) == DMA_INCREMENT_RELOAD) {
1451				info->nextDest = info->dest;
1452			}
1453			GBAMemoryScheduleDMA(gba, number, info);
1454		}
1455		if (GBADMARegisterIsDoIRQ(info->reg)) {
1456			GBARaiseIRQ(gba, IRQ_DMA0 + number);
1457		}
1458	} else {
1459		info->nextDest = dest;
1460		info->nextCount = wordsRemaining;
1461	}
1462	info->nextSource = source;
1463
1464	if (info->nextEvent != INT_MAX) {
1465		info->nextEvent += cycles;
1466	}
1467	cpu->cycles += cycles;
1468}
1469
1470void GBAMemorySerialize(const struct GBAMemory* memory, struct GBASerializedState* state) {
1471	memcpy(state->wram, memory->wram, SIZE_WORKING_RAM);
1472	memcpy(state->iwram, memory->iwram, SIZE_WORKING_IRAM);
1473}
1474
1475void GBAMemoryDeserialize(struct GBAMemory* memory, const struct GBASerializedState* state) {
1476	memcpy(memory->wram, state->wram, SIZE_WORKING_RAM);
1477	memcpy(memory->iwram, state->iwram, SIZE_WORKING_IRAM);
1478}
1479
1480uint32_t _popcount32(unsigned bits) {
1481	bits = bits - ((bits >> 1) & 0x55555555);
1482	bits = (bits & 0x33333333) + ((bits >> 2) & 0x33333333);
1483	return (((bits + (bits >> 4)) & 0xF0F0F0F) * 0x1010101) >> 24;
1484}