src/ds/ds.c (view raw)
1/* Copyright (c) 2013-2016 Jeffrey Pfau
2 *
3 * This Source Code Form is subject to the terms of the Mozilla Public
4 * License, v. 2.0. If a copy of the MPL was not distributed with this
5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */
6#include <mgba/internal/ds/ds.h>
7
8#include <mgba/internal/arm/decoder.h>
9#include <mgba/internal/arm/debugger/debugger.h>
10#include <mgba/internal/arm/isa-inlines.h>
11#include <mgba/internal/ds/bios.h>
12
13#include <mgba-util/crc32.h>
14#include <mgba-util/memory.h>
15#include <mgba-util/math.h>
16#include <mgba-util/vfs.h>
17
18#define SLICE_CYCLES 2048
19
20mLOG_DEFINE_CATEGORY(DS, "DS");
21
22const uint32_t DS_ARM946ES_FREQUENCY = 0x1FF61FE;
23const uint32_t DS_ARM7TDMI_FREQUENCY = 0xFFB0FF;
24const uint32_t DS_COMPONENT_MAGIC = 0x1FF61FE;
25
26static const size_t DS_ROM_MAGIC_OFFSET = 0x15C;
27static const uint8_t DS_ROM_MAGIC[] = { 0x56, 0xCF };
28
29enum {
30 DS7_SP_BASE = 0x380FD80,
31 DS7_SP_BASE_IRQ = 0x380FF80,
32 DS7_SP_BASE_SVC = 0x380FFC0,
33
34 DS9_SP_BASE = 0x3002F7C,
35 DS9_SP_BASE_IRQ = 0x3003F80,
36 DS9_SP_BASE_SVC = 0x3003FC0,
37};
38
39static void DSInit(void* cpu, struct mCPUComponent* component);
40
41static void DS7Reset(struct ARMCore* cpu);
42static void DS7TestIRQ(struct ARMCore* cpu);
43static void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh);
44static void DS7ProcessEvents(struct ARMCore* cpu);
45
46static void DS9Reset(struct ARMCore* cpu);
47static void DS9TestIRQ(struct ARMCore* cpu);
48static void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value);
49static void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh);
50static void DS9ProcessEvents(struct ARMCore* cpu);
51
52static void DSProcessEvents(struct DSCommon* dscore);
53static void DSHitStub(struct ARMCore* cpu, uint32_t opcode);
54static void DSIllegal(struct ARMCore* cpu, uint32_t opcode);
55static void DSBreakpoint(struct ARMCore* cpu, int immediate);
56
57static void _slice(struct mTiming* timing, void* context, uint32_t cyclesLate) {
58 UNUSED(cyclesLate);
59 struct DS* ds = context;
60 uint32_t cycles = mTimingCurrentTime(timing) - ds->sliceStart;
61 if (ds->activeCpu == ds->ds9.cpu) {
62 ds->activeCpu = ds->ds7.cpu;
63 ds->cycleDrift += cycles;
64 cycles = ds->cycleDrift >> 1;
65 timing = &ds->ds7.timing;
66 } else {
67 ds->activeCpu = ds->ds9.cpu;
68 ds->cycleDrift -= cycles << 1;
69 cycles = ds->cycleDrift + SLICE_CYCLES;
70 timing = &ds->ds9.timing;
71 }
72 mTimingSchedule(timing, &ds->slice, cycles);
73 ds->sliceStart = mTimingCurrentTime(timing);
74}
75
76void DSCreate(struct DS* ds) {
77 ds->d.id = DS_COMPONENT_MAGIC;
78 ds->d.init = DSInit;
79 ds->d.deinit = NULL;
80 ds->ds7.p = ds;
81 ds->ds9.p = ds;
82 ds->ds7.cpu = NULL;
83 ds->ds9.cpu = NULL;
84 ds->ds7.ipc = &ds->ds9;
85 ds->ds9.ipc = &ds->ds7;
86}
87
88static void DSInit(void* cpu, struct mCPUComponent* component) {
89 struct DS* ds = (struct DS*) component;
90 struct ARMCore* core = cpu;
91 if (!ds->ds7.cpu) {
92 // The ARM7 must get initialized first
93 ds->ds7.cpu = core;
94 ds->debugger = 0;
95 ds->sync = 0;
96 return;
97 }
98 ds->ds9.cpu = cpu;
99 ds->activeCpu = NULL;
100
101 ds->ds9.cpu->cp15.r1.c0 = ARMControlRegFillVE(0);
102
103 ds->slice.name = "DS CPU Time Slicing";
104 ds->slice.callback = _slice;
105 ds->slice.context = ds;
106 ds->slice.priority = UINT_MAX;
107
108 CircleBufferInit(&ds->ds7.fifo, 64);
109 CircleBufferInit(&ds->ds9.fifo, 64);
110
111 DS7InterruptHandlerInit(&ds->ds7.cpu->irqh);
112 DS9InterruptHandlerInit(&ds->ds9.cpu->irqh);
113 DSMemoryInit(ds);
114 DSDMAInit(ds);
115
116 ds->video.p = ds;
117
118 ds->ds7.springIRQ = 0;
119 ds->ds9.springIRQ = 0;
120 DSTimerInit(ds);
121 ds->keySource = NULL;
122 ds->rtcSource = NULL;
123 ds->rumble = NULL;
124
125 ds->romVf = NULL;
126
127 ds->keyCallback = NULL;
128
129 mTimingInit(&ds->ds7.timing, &ds->ds7.cpu->cycles, &ds->ds7.cpu->nextEvent);
130 mTimingInit(&ds->ds9.timing, &ds->ds9.cpu->cycles, &ds->ds9.cpu->nextEvent);
131}
132
133void DSUnloadROM(struct DS* ds) {
134 if (ds->romVf) {
135 ds->romVf->close(ds->romVf);
136 ds->romVf = NULL;
137 }
138}
139
140void DSDestroy(struct DS* ds) {
141 CircleBufferDeinit(&ds->ds7.fifo);
142 CircleBufferDeinit(&ds->ds9.fifo);
143 DSUnloadROM(ds);
144 DSMemoryDeinit(ds);
145 mTimingDeinit(&ds->ds7.timing);
146 mTimingDeinit(&ds->ds9.timing);
147}
148
149void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
150 irqh->reset = DS7Reset;
151 irqh->processEvents = DS7ProcessEvents;
152 irqh->swi16 = DS7Swi16;
153 irqh->swi32 = DS7Swi32;
154 irqh->hitIllegal = DSIllegal;
155 irqh->readCPSR = DS7TestIRQ;
156 irqh->writeCP15 = NULL;
157 irqh->hitStub = DSHitStub;
158 irqh->bkpt16 = DSBreakpoint;
159 irqh->bkpt32 = DSBreakpoint;
160}
161
162void DS9InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
163 irqh->reset = DS9Reset;
164 irqh->processEvents = DS9ProcessEvents;
165 irqh->swi16 = NULL;
166 irqh->swi32 = NULL;
167 irqh->hitIllegal = DSIllegal;
168 irqh->readCPSR = DS9TestIRQ;
169 irqh->writeCP15 = DS9WriteCP15;
170 irqh->hitStub = DSHitStub;
171 irqh->bkpt16 = DSBreakpoint;
172 irqh->bkpt32 = DSBreakpoint;
173}
174
175void DS7Reset(struct ARMCore* cpu) {
176 ARMSetPrivilegeMode(cpu, MODE_IRQ);
177 cpu->gprs[ARM_SP] = DS7_SP_BASE_IRQ;
178 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
179 cpu->gprs[ARM_SP] = DS7_SP_BASE_SVC;
180 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
181 cpu->gprs[ARM_SP] = DS7_SP_BASE;
182
183 struct DS* ds = (struct DS*) cpu->master;
184 mTimingClear(&ds->ds7.timing);
185 CircleBufferInit(&ds->ds7.fifo, 64);
186 DSMemoryReset(ds);
187 DSDMAReset(&ds->ds7);
188 DS7IOInit(ds);
189
190 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
191 if (header) {
192 // TODO: Error check
193 ds->romVf->seek(ds->romVf, header->arm7Offset, SEEK_SET);
194 uint32_t base = header->arm7Base - DS_BASE_RAM;
195 uint32_t* basePointer = &ds->memory.ram[base >> 2];
196 if (base < DS_SIZE_RAM && base + header->arm7Size <= DS_SIZE_RAM) {
197 ds->romVf->read(ds->romVf, basePointer, header->arm7Size);
198 }
199 cpu->gprs[12] = header->arm7Entry;
200 cpu->gprs[ARM_LR] = header->arm7Entry;
201 cpu->gprs[ARM_PC] = header->arm7Entry;
202 int currentCycles = 0;
203 ARM_WRITE_PC;
204
205 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
206 }
207}
208
209void DS9Reset(struct ARMCore* cpu) {
210 ARMSetPrivilegeMode(cpu, MODE_IRQ);
211 cpu->gprs[ARM_SP] = DS9_SP_BASE_IRQ;
212 ARMSetPrivilegeMode(cpu, MODE_SUPERVISOR);
213 cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
214 ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
215 cpu->gprs[ARM_SP] = DS9_SP_BASE;
216
217 struct DS* ds = (struct DS*) cpu->master;
218 mTimingClear(&ds->ds9.timing);
219 CircleBufferInit(&ds->ds9.fifo, 64);
220 DSDMAReset(&ds->ds9);
221 DS9IOInit(ds);
222
223 ds->activeCpu = cpu;
224 mTimingSchedule(&ds->ds9.timing, &ds->slice, SLICE_CYCLES);
225 ds->cycleDrift = 0;
226 ds->sliceStart = mTimingCurrentTime(&ds->ds9.timing);
227
228 struct DSCartridge* header = ds->romVf->map(ds->romVf, sizeof(*header), MAP_READ);
229 if (header) {
230 // TODO: Error check
231 ds->romVf->seek(ds->romVf, header->arm9Offset, SEEK_SET);
232 uint32_t base = header->arm9Base - DS_BASE_RAM;
233 uint32_t* basePointer = &ds->memory.ram[base >> 2];
234 if (base < DS_SIZE_RAM && base + header->arm9Size <= DS_SIZE_RAM) {
235 ds->romVf->read(ds->romVf, basePointer, header->arm9Size);
236 }
237 cpu->gprs[12] = header->arm9Entry;
238 cpu->gprs[ARM_LR] = header->arm9Entry;
239 cpu->gprs[ARM_PC] = header->arm9Entry;
240 int currentCycles = 0;
241 ARM_WRITE_PC;
242
243 ds->romVf->unmap(ds->romVf, header, sizeof(*header));
244 }
245}
246
247static void DS7ProcessEvents(struct ARMCore* cpu) {
248 struct DS* ds = (struct DS*) cpu->master;
249 DSProcessEvents(&ds->ds7);
250}
251
252static void DS9ProcessEvents(struct ARMCore* cpu) {
253 struct DS* ds = (struct DS*) cpu->master;
254 DSProcessEvents(&ds->ds9);
255}
256
257static void DSProcessEvents(struct DSCommon* dscore) {
258 struct ARMCore* cpu = dscore->cpu;
259 struct DS* ds = dscore->p;
260 if (dscore->springIRQ && !cpu->cpsr.i) {
261 ARMRaiseIRQ(cpu);
262 dscore->springIRQ = 0;
263 }
264
265 int32_t nextEvent = cpu->nextEvent;
266 while (cpu->cycles >= nextEvent) {
267 int32_t cycles = cpu->cycles;
268
269 cpu->cycles = 0;
270 cpu->nextEvent = INT_MAX;
271
272#ifndef NDEBUG
273 if (cycles < 0) {
274 mLOG(DS, FATAL, "Negative cycles passed: %i", cycles);
275 }
276#endif
277 nextEvent = cycles;
278 do {
279 nextEvent = mTimingTick(&dscore->timing, nextEvent);
280 } while (ds->cpuBlocked);
281
282 cpu->nextEvent = nextEvent;
283
284 if (ds->earlyExit) {
285 ds->earlyExit = false;
286 break;
287 }
288 if (cpu->halted) {
289 cpu->cycles = nextEvent;
290 }
291#ifndef NDEBUG
292 else if (nextEvent < 0) {
293 mLOG(DS, FATAL, "Negative cycles will pass: %i", nextEvent);
294 }
295#endif
296 }
297}
298
299void DSRunLoop(struct DS* ds) {
300 if (ds->activeCpu == ds->ds9.cpu) {
301 ARMv5RunLoop(ds->ds9.cpu);
302 } else {
303 ARMv4RunLoop(ds->ds7.cpu);
304 }
305}
306
307void DS7Step(struct DS* ds) {
308 while (ds->activeCpu == ds->ds9.cpu) {
309 ARMv5RunLoop(ds->ds9.cpu);
310 }
311 ARMv4Run(ds->ds7.cpu);
312}
313
314void DS9Step(struct DS* ds) {
315 while (ds->activeCpu == ds->ds7.cpu) {
316 ARMv4RunLoop(ds->ds7.cpu);
317 }
318 ARMv5Run(ds->ds9.cpu);
319}
320
321void DSAttachDebugger(struct DS* ds, struct mDebugger* debugger) {
322 ds->debugger = (struct ARMDebugger*) debugger->platform;
323 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
324 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = &debugger->d;
325 ARMHotplugAttach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
326 ARMHotplugAttach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
327}
328
329void DSDetachDebugger(struct DS* ds) {
330 ds->debugger = NULL;
331 ARMHotplugDetach(ds->ds7.cpu, CPU_COMPONENT_DEBUGGER);
332 ARMHotplugDetach(ds->ds9.cpu, CPU_COMPONENT_DEBUGGER);
333 ds->ds7.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
334 ds->ds9.cpu->components[CPU_COMPONENT_DEBUGGER] = NULL;
335}
336
337bool DSLoadROM(struct DS* ds, struct VFile* vf) {
338 DSUnloadROM(ds);
339 ds->romVf = vf;
340 // TODO: error check
341 return true;
342}
343
344bool DSIsROM(struct VFile* vf) {
345 if (vf->seek(vf, DS_ROM_MAGIC_OFFSET, SEEK_SET) < 0) {
346 return false;
347 }
348 uint8_t signature[sizeof(DS_ROM_MAGIC)];
349 if (vf->read(vf, &signature, sizeof(signature)) != sizeof(signature)) {
350 return false;
351 }
352 return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
353}
354
355bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
356 size_t size = vf->size(vf);
357 void* data = NULL;
358 uint32_t crc;
359 if (size == DS7_SIZE_BIOS) {
360 data = vf->map(vf, size, MAP_READ);
361 } else if (size == 0x1000) {
362 data = vf->map(vf, size, MAP_READ);
363 }
364 if (!data) {
365 return false;
366 }
367 crc = doCrc32(data, size);
368 if (crc == DS7_BIOS_CHECKSUM) {
369 ds->bios7Vf = vf;
370 ds->memory.bios7 = data;
371 mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
372 } else if (crc == DS9_BIOS_CHECKSUM) {
373 ds->bios9Vf = vf;
374 ds->memory.bios9 = data;
375 mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
376 } else {
377 mLOG(DS, WARN, "BIOS checksum incorrect");
378 vf->unmap(vf, data, size);
379 return false;
380 }
381 return true;
382}
383
384void DSGetGameCode(struct DS* ds, char* out) {
385 memset(out, 0, 8);
386 if (!ds->romVf) {
387 return;
388 }
389
390 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
391 memcpy(out, "NTR-", 4);
392 memcpy(&out[4], &cart->id, 4);
393 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
394}
395
396void DSGetGameTitle(struct DS* ds, char* out) {
397 memset(out, 0, 12);
398 if (!ds->romVf) {
399 return;
400 }
401
402 struct DSCartridge* cart = ds->romVf->map(ds->romVf, sizeof(*cart), MAP_READ);
403 memcpy(out, &cart->title, 4);
404 ds->romVf->unmap(ds->romVf, cart, sizeof(*cart));
405}
406
407void DSHitStub(struct ARMCore* cpu, uint32_t opcode) {
408 struct DS* ds = (struct DS*) cpu->master;
409 if (ds->debugger) {
410 struct mDebuggerEntryInfo info = {
411 .address = _ARMPCAddress(cpu),
412 .opcode = opcode
413 };
414 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
415 }
416 // TODO: More sensible category?
417 mLOG(DS, ERROR, "Stub opcode: %08x", opcode);
418}
419
420void DSIllegal(struct ARMCore* cpu, uint32_t opcode) {
421 struct DS* ds = (struct DS*) cpu->master;
422 if (ds->debugger) {
423 struct mDebuggerEntryInfo info = {
424 .address = _ARMPCAddress(cpu),
425 .opcode = opcode
426 };
427 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_ILLEGAL_OP, &info);
428 } else {
429 ARMRaiseUndefined(cpu);
430 }
431}
432
433void DSBreakpoint(struct ARMCore* cpu, int immediate) {
434 struct DS* ds = (struct DS*) cpu->master;
435 if (immediate >= CPU_COMPONENT_MAX) {
436 return;
437 }
438 switch (immediate) {
439 case CPU_COMPONENT_DEBUGGER:
440 if (ds->debugger) {
441 struct mDebuggerEntryInfo info = {
442 .address = _ARMPCAddress(cpu)
443 };
444 mDebuggerEnter(ds->debugger->d.p, DEBUGGER_ENTER_BREAKPOINT, &info);
445 }
446 break;
447 default:
448 break;
449 }
450}
451
452void DS7TestIRQ(struct ARMCore* cpu) {
453 struct DS* ds = (struct DS*) cpu->master;
454 if (0) {
455 ds->ds7.springIRQ = 1;
456 cpu->nextEvent = cpu->cycles;
457 }
458}
459
460void DS9TestIRQ(struct ARMCore* cpu) {
461 struct DS* ds = (struct DS*) cpu->master;
462 if (0) {
463 ds->ds9.springIRQ = 1;
464 cpu->nextEvent = cpu->cycles;
465 }
466}
467
468static void _writeSysControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
469 mLOG(DS, STUB, "CP15 system control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
470}
471
472static void _writeCacheControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
473 mLOG(DS, STUB, "CP15 cache control control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
474 switch (opcode2) {
475 case 0:
476 cpu->cp15.r2.d = value;
477 break;
478 case 1:
479 cpu->cp15.r2.i = value;
480 break;
481 default:
482 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
483 break;
484 }
485}
486
487static void _writeWriteBufferControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
488 mLOG(DS, STUB, "CP15 write buffer control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
489 switch (opcode2) {
490 case 0:
491 cpu->cp15.r3.d = value;
492 break;
493 default:
494 mLOG(DS, GAME_ERROR, "CP15 cache control control bad op2: %i", opcode2);
495 break;
496 }
497}
498
499static void _writeAccessControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
500 mLOG(DS, STUB, "CP15 access control write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
501}
502
503static void _writeRegionConfiguration(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
504 cpu->cp15.r6.region[crm] = value;
505 uint32_t base = ARMProtectionGetBase(value) << 12;
506 uint32_t size = 2 << ARMProtectionGetSize(value);
507 mLOG(DS, STUB, "CP15 region configuration write: Region: %i, Insn: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
508}
509
510static void _writeCache(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
511 mLOG(DS, STUB, "CP15 cache write: CRm: %i, Op2: %i, Value: 0x%08X", crm, opcode2, value);
512}
513
514static void _writeTCMControl(struct ARMCore* cpu, int crm, int opcode2, uint32_t value) {
515 uint32_t base = ARMTCMControlGetBase(value) << 12;
516 uint32_t size = 512 << ARMTCMControlGetVirtualSize(value);
517 mLOG(DS, STUB, "CP15 TCM control write: CRm: %i, Op2: %i, Base: %08X, Size: %08X", crm, opcode2, base, size);
518 switch (opcode2) {
519 case 0:
520 cpu->cp15.r9.d = value;
521 break;
522 case 1:
523 cpu->cp15.r9.i = value;
524 break;
525 default:
526 mLOG(DS, GAME_ERROR, "CP15 TCM control bad op2: %i", opcode2);
527 break;
528 }
529}
530
531void DS9WriteCP15(struct ARMCore* cpu, int crn, int crm, int opcode1, int opcode2, uint32_t value) {
532 switch (crn) {
533 default:
534 mLOG(DS, STUB, "CP15 unknown write: CRn: %i, CRm: %i, Op1: %i, Op2: %i, Value: 0x%08X", crn, crm, opcode1, opcode2, value);
535 break;
536 case 0:
537 mLOG(DS, GAME_ERROR, "Attempted to write to read-only cp15 register");
538 ARMRaiseUndefined(cpu);
539 break;
540 case 1:
541 _writeSysControl(cpu, crm, opcode2, value);
542 break;
543 case 2:
544 _writeCacheControl(cpu, crm, opcode2, value);
545 break;
546 case 3:
547 _writeWriteBufferControl(cpu, crm, opcode2, value);
548 break;
549 case 5:
550 _writeAccessControl(cpu, crm, opcode2, value);
551 break;
552 case 6:
553 _writeRegionConfiguration(cpu, crm, opcode2, value);
554 break;
555 case 7:
556 _writeCache(cpu, crm, opcode2, value);
557 break;
558 case 9:
559 _writeTCMControl(cpu, crm, opcode2, value);
560 break;
561 }
562}
563
564void DSWriteIE(struct ARMCore* cpu, uint16_t* io, uint32_t value) {
565 if (io[DS_REG_IME >> 1] && (value & io[DS_REG_IF_LO >> 1] || (value >> 16) & io[DS_REG_IF_HI >> 1])) {
566 ARMRaiseIRQ(cpu);
567 }
568}
569void DSWriteIME(struct ARMCore* cpu, uint16_t* io, uint16_t value) {
570 if (value && (io[DS_REG_IE_LO >> 1] & io[DS_REG_IF_LO >> 1] || io[DS_REG_IE_HI >> 1] & io[DS_REG_IF_HI >> 1])) {
571 ARMRaiseIRQ(cpu);
572 }
573}
574
575void DSRaiseIRQ(struct ARMCore* cpu, uint16_t* io, enum DSIRQ irq) {
576 if (irq < 16) {
577 io[DS_REG_IF_LO >> 1] |= 1 << irq;
578 } else {
579 io[DS_REG_IF_HI >> 1] |= 1 << (irq - 16);
580 }
581
582 if ((irq < 16 && (io[DS_REG_IE_LO >> 1] & 1 << irq)) || (io[DS_REG_IE_HI >> 1] & 1 << (irq - 16))) {
583 cpu->halted = 0;
584 if (io[DS_REG_IME >> 1]) {
585 ARMRaiseIRQ(cpu);
586 }
587 }
588}